[PATCH] D39289: [SelectionDAG] Support 'bit preserving' floating points bitcasts on computeKnownBits/ComputeNumSignBits

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

In IR, we generally assume a store+load preserves the exact bit-pattern (for example, GVN depends on this).  I guess that could be wrong if we lower a "load" instruction to an x87 "fld" (which transforms SNaN->QNaN), but as as far as I know no other architecture has that particular quirk.

The hasBitPreservingFPLogic hook is supposed to detect cases where fneg is lowered to a floating-point subtraction; it has nothing to do with any property of the underlying registers.


Repository:
  rL LLVM

https://reviews.llvm.org/D39289