[llvm] r316553 - AMDGPU: Add max-mix-insts subtarget feature

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Wed Oct 25 00:00:51 2017
New Revision: 316553

URL: http://llvm.org/viewvc/llvm-project?rev=316553&view=rev
Log:
AMDGPU: Add max-mix-insts subtarget feature

Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPU.td
    llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
    llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
    llvm/trunk/lib/Target/AMDGPU/VOP3PInstructions.td

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPU.td?rev=316553&r1=316552&r2=316553&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPU.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPU.td Wed Oct 25 00:00:51 2017
@@ -109,6 +109,12 @@ def FeatureApertureRegs : SubtargetFeatu
   "Has Memory Aperture Base and Size Registers"
 >;
 
+def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
+  "HasMadMixInsts",
+  "true",
+  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
+>;
+
 // XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
 // XNACK. The current default kernel driver setting is:
 // - graphics ring: XNACK disabled
@@ -553,19 +559,25 @@ def FeatureISAVersion8_1_0 : SubtargetFe
 
 def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
   [FeatureGFX9,
-   FeatureLDSBankCount32]>;
+   FeatureMadMixInsts,
+   FeatureLDSBankCount32
+   ]>;
 
 def FeatureISAVersion9_0_1 : SubtargetFeatureISAVersion <9,0,1,
   [FeatureGFX9,
+   FeatureMadMixInsts,
    FeatureLDSBankCount32,
    FeatureXNACK]>;
 
 def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
   [FeatureGFX9,
-   FeatureLDSBankCount32]>;
+   FeatureMadMixInsts,
+   FeatureLDSBankCount32
+   ]>;
 
 def FeatureISAVersion9_0_3 : SubtargetFeatureISAVersion <9,0,3,
   [FeatureGFX9,
+   FeatureMadMixInsts,
    FeatureLDSBankCount32,
    FeatureXNACK]>;
 
@@ -728,8 +740,8 @@ def HasDPP : Predicate<"Subtarget->hasDP
 def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
   AssemblerPredicate<"FeatureIntClamp">;
 
-def HasMadMix : Predicate<"Subtarget->hasMadMixInsts()">,
-  AssemblerPredicate<"FeatureGFX9Insts">;
+def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
+  AssemblerPredicate<"FeatureMadMixInsts">;
 
 def EnableLateCFGStructurize : Predicate<
   "EnableLateStructurizeCFG">;

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp?rev=316553&r1=316552&r2=316553&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp Wed Oct 25 00:00:51 2017
@@ -138,6 +138,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(const T
     Has16BitInsts(false),
     HasIntClamp(false),
     HasVOP3PInsts(false),
+    HasMadMixInsts(false),
     HasMovrel(false),
     HasVGPRIndexMode(false),
     HasScalarStores(false),

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h?rev=316553&r1=316552&r2=316553&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h Wed Oct 25 00:00:51 2017
@@ -148,6 +148,7 @@ protected:
   bool Has16BitInsts;
   bool HasIntClamp;
   bool HasVOP3PInsts;
+  bool HasMadMixInsts;
   bool HasMovrel;
   bool HasVGPRIndexMode;
   bool HasScalarStores;
@@ -319,7 +320,7 @@ public:
   }
 
   bool hasMadMixInsts() const {
-    return getGeneration() >= GFX9;
+    return HasMadMixInsts;
   }
 
   bool hasCARRY() const {

Modified: llvm/trunk/lib/Target/AMDGPU/VOP3PInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP3PInstructions.td?rev=316553&r1=316552&r2=316553&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOP3PInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOP3PInstructions.td Wed Oct 25 00:00:51 2017
@@ -68,6 +68,8 @@ def V_PK_LSHLREV_B16 : VOP3PInst<"v_pk_l
 def V_PK_ASHRREV_I16 : VOP3PInst<"v_pk_ashrrev_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, ashr_rev>;
 def V_PK_LSHRREV_B16 : VOP3PInst<"v_pk_lshrrev_b16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, lshr_rev>;
 
+
+let SubtargetPredicate = HasMadMixInsts in {
 // These are VOP3a-like opcodes which accept no omod.
 // Size of src arguments (16/32) is controlled by op_sel.
 // For 16-bit src arguments their location (hi/lo) are controlled by op_sel_hi.
@@ -82,8 +84,6 @@ def V_MAD_MIXHI_F16 : VOP3_VOP3PInst<"v_
 }
 }
 
-let OtherPredicates = [HasMadMix] in {
-
 def : GCNPat <
   (f16 (fpround (fmad (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)),
                       (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_modifiers)),
@@ -141,7 +141,7 @@ def : GCNPat <
                                            (i32 (IMPLICIT_DEF)))))
 >;
 
-} // End Predicates = [HasMadMix]
+} // End SubtargetPredicate = [HasMadMixInsts]
 
 multiclass VOP3P_Real_vi<bits<10> op> {
   def _vi : VOP3P_Real<!cast<VOP3P_Pseudo>(NAME), SIEncodingFamily.VI>,