[PATCH] D39264: Make the combiner check if shifts are legal before creating them
Aditya Nandakumar via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 24 17:10:46 PDT 2017
aditya_nandakumar created this revision.
Make sure shifts are legal/specified by the legalizerinfo before creating it
https://reviews.llvm.org/D39264
Files:
include/llvm/CodeGen/GlobalISel/LegalizerCombiner.h
include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
lib/CodeGen/GlobalISel/Legalizer.cpp
Index: lib/CodeGen/GlobalISel/Legalizer.cpp
===================================================================
--- lib/CodeGen/GlobalISel/Legalizer.cpp
+++ lib/CodeGen/GlobalISel/Legalizer.cpp
@@ -97,7 +97,8 @@
}
});
WorkList.insert(&*MI);
- LegalizerCombiner C(Helper.MIRBuilder, MF.getRegInfo());
+ LegalizerCombiner C(Helper.MIRBuilder, MF.getRegInfo(),
+ Helper.getLegalizerInfo());
bool Changed = false;
LegalizerHelper::LegalizeResult Res;
do {
@@ -158,7 +159,7 @@
MachineRegisterInfo &MRI = MF.getRegInfo();
MachineIRBuilder MIRBuilder(MF);
- LegalizerCombiner C(MIRBuilder, MRI);
+ LegalizerCombiner C(MIRBuilder, MRI, Helper.getLegalizerInfo());
for (auto &MBB : MF) {
for (auto MI = MBB.begin(); MI != MBB.end(); MI = NextMI) {
// Get the next Instruction before we try to legalize, because there's a
Index: include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
===================================================================
--- include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
+++ include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
@@ -89,6 +89,9 @@
/// functions
MachineIRBuilder MIRBuilder;
+ /// Expose LegalizerInfo so the clients can re-use.
+ const LegalizerInfo &getLegalizerInfo() const { return LI; }
+
private:
/// Helper function to split a wide generic register into bitwise blocks with
Index: include/llvm/CodeGen/GlobalISel/LegalizerCombiner.h
===================================================================
--- include/llvm/CodeGen/GlobalISel/LegalizerCombiner.h
+++ include/llvm/CodeGen/GlobalISel/LegalizerCombiner.h
@@ -13,6 +13,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/GlobalISel/Legalizer.h"
+#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -24,10 +25,12 @@
class LegalizerCombiner {
MachineIRBuilder &Builder;
MachineRegisterInfo &MRI;
+ const LegalizerInfo &LI;
public:
- LegalizerCombiner(MachineIRBuilder &B, MachineRegisterInfo &MRI)
- : Builder(B), MRI(MRI) {}
+ LegalizerCombiner(MachineIRBuilder &B, MachineRegisterInfo &MRI,
+ const LegalizerInfo &LI)
+ : Builder(B), MRI(MRI), LI(LI) {}
bool tryCombineAnyExt(MachineInstr &MI,
SmallVectorImpl<MachineInstr *> &DeadInsts) {
@@ -79,10 +82,18 @@
return false;
MachineInstr *DefMI = MRI.getVRegDef(MI.getOperand(1).getReg());
if (DefMI->getOpcode() == TargetOpcode::G_TRUNC) {
- DEBUG(dbgs() << ".. Combine MI: " << MI;);
- Builder.setInstr(MI);
unsigned DstReg = MI.getOperand(0).getReg();
LLT DstTy = MRI.getType(DstReg);
+ auto SHLAction = LI.getAction({TargetOpcode::G_SHL, 0, DstTy});
+ if (SHLAction.first == LegalizerInfo::LegalizeAction::Unsupported ||
+ SHLAction.first == LegalizerInfo::LegalizeAction::NotFound)
+ return false;
+ auto ASHRAction = LI.getAction({TargetOpcode::G_ASHR, 0, DstTy});
+ if (ASHRAction.first == LegalizerInfo::LegalizeAction::Unsupported ||
+ ASHRAction.first == LegalizerInfo::LegalizeAction::NotFound)
+ return false;
+ DEBUG(dbgs() << ".. Combine MI: " << MI;);
+ Builder.setInstr(MI);
unsigned SExtSrc = MI.getOperand(1).getReg();
LLT SExtSrcTy = MRI.getType(SExtSrc);
unsigned SizeDiff = DstTy.getSizeInBits() - SExtSrcTy.getSizeInBits();
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D39264.120153.patch
Type: text/x-patch
Size: 3615 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20171025/fe4eecb1/attachment.bin>
More information about the llvm-commits
mailing list