[llvm] r316479 - MIR: Print the register class or bank in vreg defs
Justin Bogner via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 24 11:04:55 PDT 2017
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-constant.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-constant.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-constant.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-constant.mir Tue Oct 24 11:04:54 2017
@@ -46,9 +46,7 @@ registers:
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: const_i8
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: gr8
- ; CHECK: [[MOV8ri:%[0-9]+]] = MOV8ri 2
+ ; CHECK: [[MOV8ri:%[0-9]+]]:gr8 = MOV8ri 2
; CHECK: %al = COPY [[MOV8ri]]
; CHECK: RET 0, implicit %al
%0(s8) = G_CONSTANT i8 2
@@ -66,9 +64,7 @@ registers:
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: const_i16
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: gr16
- ; CHECK: [[MOV16ri:%[0-9]+]] = MOV16ri 3
+ ; CHECK: [[MOV16ri:%[0-9]+]]:gr16 = MOV16ri 3
; CHECK: %ax = COPY [[MOV16ri]]
; CHECK: RET 0, implicit %ax
%0(s16) = G_CONSTANT i16 3
@@ -86,9 +82,7 @@ registers:
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: const_i32
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: gr32
- ; CHECK: [[MOV32ri:%[0-9]+]] = MOV32ri 4
+ ; CHECK: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 4
; CHECK: %eax = COPY [[MOV32ri]]
; CHECK: RET 0, implicit %eax
%0(s32) = G_CONSTANT i32 4
@@ -105,9 +99,7 @@ registers:
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: const_i32_0
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: gr32
- ; CHECK: [[MOV32r0_:%[0-9]+]] = MOV32r0 implicit-def %eflags
+ ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def %eflags
; CHECK: %eax = COPY [[MOV32r0_]]
; CHECK: RET 0, implicit %eax
%0(s32) = G_CONSTANT i32 0
@@ -125,9 +117,7 @@ registers:
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: const_i64
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: gr64
- ; CHECK: [[MOV64ri:%[0-9]+]] = MOV64ri 68719476720
+ ; CHECK: [[MOV64ri:%[0-9]+]]:gr64 = MOV64ri 68719476720
; CHECK: %rax = COPY [[MOV64ri]]
; CHECK: RET 0, implicit %rax
%0(s64) = G_CONSTANT i64 68719476720
@@ -146,9 +136,7 @@ registers:
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: const_i64_u32
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: gr64
- ; CHECK: [[MOV64ri32_:%[0-9]+]] = MOV64ri32 1879048192
+ ; CHECK: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 1879048192
; CHECK: %rax = COPY [[MOV64ri32_]]
; CHECK: RET 0, implicit %rax
%0(s64) = G_CONSTANT i64 1879048192
@@ -166,9 +154,7 @@ registers:
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: const_i64_i32
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: gr64
- ; CHECK: [[MOV64ri32_:%[0-9]+]] = MOV64ri32 -1
+ ; CHECK: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 -1
; CHECK: %rax = COPY [[MOV64ri32_]]
; CHECK: RET 0, implicit %rax
%0(s64) = G_CONSTANT i64 -1
@@ -189,11 +175,8 @@ body: |
liveins: %rdi
; CHECK-LABEL: name: main
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: gr64
- ; CHECK-NEXT: id: 1, class: gr64
- ; CHECK: [[COPY:%[0-9]+]] = COPY %rdi
- ; CHECK: [[MOV64ri32_:%[0-9]+]] = MOV64ri32 0
+ ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+ ; CHECK: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 0
; CHECK: MOV64mr [[COPY]], 1, _, 0, _, [[MOV64ri32_]] :: (store 8 into %ir.data)
; CHECK: RET 0
%0(p0) = COPY %rdi
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-copy.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-copy.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-copy.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-copy.mir Tue Oct 24 11:04:54 2017
@@ -41,9 +41,9 @@ regBankSelected: true
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
-# ALL: %0 = COPY %al
-# ALL-NEXT: %2 = SUBREG_TO_REG 0, %0, 1
-# ALL-NEXT: %1 = AND32ri8 %2, 1, implicit-def %eflags
+# ALL: %0:gr8 = COPY %al
+# ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %0, 1
+# ALL-NEXT: %1:gr32 = AND32ri8 %2, 1, implicit-def %eflags
# ALL-NEXT: %eax = COPY %1
# ALL-NEXT: RET 0, implicit %eax
body: |
@@ -68,8 +68,8 @@ regBankSelected: true
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
-# ALL: %0 = COPY %al
-# ALL-NEXT: %1 = MOVZX32rr8 %0
+# ALL: %0:gr8 = COPY %al
+# ALL-NEXT: %1:gr32 = MOVZX32rr8 %0
# ALL-NEXT: %eax = COPY %1
# ALL-NEXT: RET 0, implicit %eax
body: |
@@ -94,8 +94,8 @@ regBankSelected: true
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
-# ALL: %0 = COPY %al
-# ALL-NEXT: %1 = MOVZX32rr8 %0
+# ALL: %0:gr8 = COPY %al
+# ALL-NEXT: %1:gr32 = MOVZX32rr8 %0
# ALL-NEXT: %eax = COPY %1
# ALL-NEXT: RET 0, implicit %eax
body: |
@@ -120,8 +120,8 @@ regBankSelected: true
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
-# ALL: %0 = COPY %ax
-# ALL-NEXT: %1 = MOVZX32rr16 %0
+# ALL: %0:gr16 = COPY %ax
+# ALL-NEXT: %1:gr32 = MOVZX32rr16 %0
# ALL-NEXT: %eax = COPY %1
# ALL-NEXT: RET 0, implicit %eax
body: |
@@ -145,8 +145,8 @@ regBankSelected: true
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr, preferred-register: '' }
-# ALL: %0 = COPY %dl
-# ALL-NEXT: %1 = SUBREG_TO_REG 0, %0, 1
+# ALL: %0:gr8 = COPY %dl
+# ALL-NEXT: %1:gr32 = SUBREG_TO_REG 0, %0, 1
# ALL-NEXT: %eax = COPY %1
# ALL-NEXT: RET 0, implicit %eax
body: |
@@ -169,8 +169,8 @@ regBankSelected: true
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr, preferred-register: '' }
-# ALL: %0 = COPY %dx
-# ALL-NEXT: %1 = SUBREG_TO_REG 0, %0, 3
+# ALL: %0:gr16 = COPY %dx
+# ALL-NEXT: %1:gr32 = SUBREG_TO_REG 0, %0, 3
# ALL-NEXT: %eax = COPY %1
# ALL-NEXT: RET 0, implicit %eax
body: |
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir Tue Oct 24 11:04:54 2017
@@ -37,15 +37,10 @@ body: |
liveins: %edi
; ALL-LABEL: name: test_zext_i1
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr8
- ; ALL-NEXT: id: 1, class: gr8
- ; ALL-NEXT: id: 2, class: gr64
- ; ALL-NEXT: id: 3, class: gr64
- ; ALL: [[COPY:%[0-9]+]] = COPY %dil
- ; ALL: [[COPY1:%[0-9]+]] = COPY [[COPY]]
- ; ALL: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY1]], 1
- ; ALL: [[AND64ri8_:%[0-9]+]] = AND64ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
+ ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY %dil
+ ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]]
+ ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], 1
+ ; ALL: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
; ALL: %rax = COPY [[AND64ri8_]]
; ALL: RET 0, implicit %rax
%0(s8) = COPY %dil
@@ -68,11 +63,8 @@ body: |
liveins: %edi
; ALL-LABEL: name: test_sext_i8
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr8
- ; ALL-NEXT: id: 1, class: gr64
- ; ALL: [[COPY:%[0-9]+]] = COPY %dil
- ; ALL: [[MOVSX64rr8_:%[0-9]+]] = MOVSX64rr8 [[COPY]]
+ ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY %dil
+ ; ALL: [[MOVSX64rr8_:%[0-9]+]]:gr64 = MOVSX64rr8 [[COPY]]
; ALL: %rax = COPY [[MOVSX64rr8_]]
; ALL: RET 0, implicit %rax
%0(s8) = COPY %dil
@@ -94,11 +86,8 @@ body: |
liveins: %edi
; ALL-LABEL: name: test_sext_i16
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr16
- ; ALL-NEXT: id: 1, class: gr64
- ; ALL: [[COPY:%[0-9]+]] = COPY %di
- ; ALL: [[MOVSX64rr16_:%[0-9]+]] = MOVSX64rr16 [[COPY]]
+ ; ALL: [[COPY:%[0-9]+]]:gr16 = COPY %di
+ ; ALL: [[MOVSX64rr16_:%[0-9]+]]:gr64 = MOVSX64rr16 [[COPY]]
; ALL: %rax = COPY [[MOVSX64rr16_]]
; ALL: RET 0, implicit %rax
%0(s16) = COPY %di
@@ -121,13 +110,9 @@ body: |
liveins: %edi
; ALL-LABEL: name: anyext_s64_from_s1
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr64_with_sub_8bit
- ; ALL-NEXT: id: 1, class: gr8
- ; ALL-NEXT: id: 2, class: gr64
- ; ALL: [[COPY:%[0-9]+]] = COPY %rdi
- ; ALL: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_8bit
- ; ALL: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY1]], 1
+ ; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY %rdi
+ ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+ ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], 1
; ALL: %rax = COPY [[SUBREG_TO_REG]]
; ALL: RET 0, implicit %rax
%0(s64) = COPY %rdi
@@ -150,13 +135,9 @@ body: |
liveins: %edi
; ALL-LABEL: name: anyext_s64_from_s8
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr64_with_sub_8bit
- ; ALL-NEXT: id: 1, class: gr8
- ; ALL-NEXT: id: 2, class: gr64
- ; ALL: [[COPY:%[0-9]+]] = COPY %rdi
- ; ALL: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_8bit
- ; ALL: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY1]], 1
+ ; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY %rdi
+ ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+ ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], 1
; ALL: %rax = COPY [[SUBREG_TO_REG]]
; ALL: RET 0, implicit %rax
%0(s64) = COPY %rdi
@@ -179,13 +160,9 @@ body: |
liveins: %edi
; ALL-LABEL: name: anyext_s64_from_s16
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr64
- ; ALL-NEXT: id: 1, class: gr16
- ; ALL-NEXT: id: 2, class: gr64
- ; ALL: [[COPY:%[0-9]+]] = COPY %rdi
- ; ALL: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_16bit
- ; ALL: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY1]], 3
+ ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+ ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+ ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], 3
; ALL: %rax = COPY [[SUBREG_TO_REG]]
; ALL: RET 0, implicit %rax
%0(s64) = COPY %rdi
@@ -208,13 +185,9 @@ body: |
liveins: %edi
; ALL-LABEL: name: anyext_s64_from_s32
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr64
- ; ALL-NEXT: id: 1, class: gr32
- ; ALL-NEXT: id: 2, class: gr64
- ; ALL: [[COPY:%[0-9]+]] = COPY %rdi
- ; ALL: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32bit
- ; ALL: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY1]], 4
+ ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+ ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]].sub_32bit
+ ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], 4
; ALL: %rax = COPY [[SUBREG_TO_REG]]
; ALL: RET 0, implicit %rax
%0(s64) = COPY %rdi
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext.mir Tue Oct 24 11:04:54 2017
@@ -57,8 +57,8 @@ regBankSelected: true
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
-# ALL: %0 = COPY %dil
-# ALL-NEXT: %1 = AND8ri %0, 1, implicit-def %eflags
+# ALL: %0:gr8 = COPY %dil
+# ALL-NEXT: %1:gr8 = AND8ri %0, 1, implicit-def %eflags
# ALL-NEXT: %al = COPY %1
# ALL-NEXT: RET 0, implicit %al
body: |
@@ -84,9 +84,9 @@ regBankSelected: true
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
-# ALL: %0 = COPY %dil
-# ALL-NEXT: %2 = SUBREG_TO_REG 0, %0, 1
-# ALL-NEXT: %1 = AND16ri8 %2, 1, implicit-def %eflags
+# ALL: %0:gr8 = COPY %dil
+# ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %0, 1
+# ALL-NEXT: %1:gr16 = AND16ri8 %2, 1, implicit-def %eflags
# ALL-NEXT: %ax = COPY %1
# ALL-NEXT: RET 0, implicit %ax
body: |
@@ -112,9 +112,9 @@ regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
-# ALL: %0 = COPY %dil
-# ALL-NEXT: %2 = SUBREG_TO_REG 0, %0, 1
-# ALL-NEXT: %1 = AND32ri8 %2, 1, implicit-def %eflags
+# ALL: %0:gr8 = COPY %dil
+# ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %0, 1
+# ALL-NEXT: %1:gr32 = AND32ri8 %2, 1, implicit-def %eflags
# ALL-NEXT: %eax = COPY %1
# ALL-NEXT: RET 0, implicit %eax
body: |
@@ -139,8 +139,8 @@ regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
-# ALL: %0 = COPY %dil
-# ALL-NEXT: %1 = MOVZX32rr8 %0
+# ALL: %0:gr8 = COPY %dil
+# ALL-NEXT: %1:gr32 = MOVZX32rr8 %0
# ALL-NEXT: %eax = COPY %1
# ALL-NEXT: RET 0, implicit %eax
body: |
@@ -165,8 +165,8 @@ regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
-# ALL: %0 = COPY %di
-# ALL-NEXT: %1 = MOVZX32rr16 %0
+# ALL: %0:gr16 = COPY %di
+# ALL-NEXT: %1:gr32 = MOVZX32rr16 %0
# ALL-NEXT: %eax = COPY %1
# ALL-NEXT: RET 0, implicit %eax
body: |
@@ -191,8 +191,8 @@ regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
-# ALL: %0 = COPY %dil
-# ALL-NEXT: %1 = MOVSX32rr8 %0
+# ALL: %0:gr8 = COPY %dil
+# ALL-NEXT: %1:gr32 = MOVSX32rr8 %0
# ALL-NEXT: %eax = COPY %1
# ALL-NEXT: RET 0, implicit %eax
body: |
@@ -217,8 +217,8 @@ regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
-# ALL: %0 = COPY %di
-# ALL-NEXT: %1 = MOVSX32rr16 %0
+# ALL: %0:gr16 = COPY %di
+# ALL-NEXT: %1:gr32 = MOVSX32rr16 %0
# ALL-NEXT: %eax = COPY %1
# ALL-NEXT: RET 0, implicit %eax
body: |
@@ -250,9 +250,10 @@ registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
-# ALL: %0 = COPY %edi
-# ALL-NEXT: %1 = COPY %0.sub_8bit
-# ALL-NEXT: %2 = COPY %1
+# X32: %0:gr32_abcd = COPY %edi
+# X64: %0:gr32 = COPY %edi
+# ALL-NEXT: %1:gr8 = COPY %0.sub_8bit
+# ALL-NEXT: %2:gr8 = COPY %1
# ALL-NEXT: %al = COPY %2
# ALL-NEXT: RET 0, implicit %al
body: |
@@ -284,9 +285,10 @@ registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
-# ALL: %0 = COPY %edi
-# ALL-NEXT: %1 = COPY %0.sub_8bit
-# ALL-NEXT: %2 = SUBREG_TO_REG 0, %1, 1
+# X32: %0:gr32_abcd = COPY %edi
+# X64: %0:gr32 = COPY %edi
+# ALL-NEXT: %1:gr8 = COPY %0.sub_8bit
+# ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %1, 1
# ALL-NEXT: %ax = COPY %2
# ALL-NEXT: RET 0, implicit %ax
body: |
@@ -318,9 +320,10 @@ registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
-# ALL: %0 = COPY %edi
-# ALL-NEXT: %1 = COPY %0.sub_8bit
-# ALL-NEXT: %2 = SUBREG_TO_REG 0, %1, 1
+# X32: %0:gr32_abcd = COPY %edi
+# X64: %0:gr32 = COPY %edi
+# ALL-NEXT: %1:gr8 = COPY %0.sub_8bit
+# ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %1, 1
# ALL-NEXT: %eax = COPY %2
# ALL-NEXT: RET 0, implicit %eax
body: |
@@ -352,9 +355,10 @@ registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
-# ALL: %0 = COPY %edi
-# ALL-NEXT: %1 = COPY %0.sub_8bit
-# ALL-NEXT: %2 = SUBREG_TO_REG 0, %1, 1
+# X32: %0:gr32_abcd = COPY %edi
+# X64: %0:gr32 = COPY %edi
+# ALL-NEXT: %1:gr8 = COPY %0.sub_8bit
+# ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %1, 1
# ALL-NEXT: %ax = COPY %2
# ALL-NEXT: RET 0, implicit %ax
body: |
@@ -386,9 +390,10 @@ registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
-# ALL: %0 = COPY %edi
-# ALL-NEXT: %1 = COPY %0.sub_8bit
-# ALL-NEXT: %2 = MOVZX32rr8 %1
+# X32: %0:gr32_abcd = COPY %edi
+# X64: %0:gr32 = COPY %edi
+# ALL-NEXT: %1:gr8 = COPY %0.sub_8bit
+# ALL-NEXT: %2:gr32 = MOVZX32rr8 %1
# ALL-NEXT: %eax = COPY %2
# ALL-NEXT: RET 0, implicit %eax
body: |
@@ -415,9 +420,9 @@ registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
-# ALL: %0 = COPY %edi
-# ALL-NEXT: %1 = COPY %0.sub_16bit
-# ALL-NEXT: %2 = SUBREG_TO_REG 0, %1, 3
+# ALL: %0:gr32 = COPY %edi
+# ALL-NEXT: %1:gr16 = COPY %0.sub_16bit
+# ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %1, 3
# ALL-NEXT: %eax = COPY %2
# ALL-NEXT: RET 0, implicit %eax
body: |
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir Tue Oct 24 11:04:54 2017
@@ -27,8 +27,10 @@ regBankSelected: true
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
-# ALL: %0 = COPY %ymm1
-# ALL-NEXT: %1 = COPY %0.sub_xmm
+# AVX: %0:vr256 = COPY %ymm1
+# AVX-NEXT: %1:vr128 = COPY %0.sub_xmm
+# AVX512VL: %0:vr256x = COPY %ymm1
+# AVX512VL-NEXT: %1:vr128x = COPY %0.sub_xmm
# ALL-NEXT: %xmm0 = COPY %1
# ALL-NEXT: RET 0, implicit %xmm0
body: |
@@ -57,13 +59,13 @@ regBankSelected: true
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
-# AVX: %0 = COPY %ymm1
-# AVX-NEXT: %1 = VEXTRACTF128rr %0, 1
+# AVX: %0:vr256 = COPY %ymm1
+# AVX-NEXT: %1:vr128 = VEXTRACTF128rr %0, 1
# AVX-NEXT: %xmm0 = COPY %1
# AVX-NEXT: RET 0, implicit %xmm0
#
-# AVX512VL: %0 = COPY %ymm1
-# AVX512VL-NEXT: %1 = VEXTRACTF32x4Z256rr %0, 1
+# AVX512VL: %0:vr256x = COPY %ymm1
+# AVX512VL-NEXT: %1:vr128x = VEXTRACTF32x4Z256rr %0, 1
# AVX512VL-NEXT: %xmm0 = COPY %1
# AVX512VL-NEXT: RET 0, implicit %xmm0
body: |
@@ -76,5 +78,3 @@ body: |
RET 0, implicit %xmm0
...
-
-
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir Tue Oct 24 11:04:54 2017
@@ -32,8 +32,8 @@ regBankSelected: true
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
-# ALL: %0 = COPY %zmm1
-# ALL-NEXT: %1 = COPY %0.sub_xmm
+# ALL: %0:vr512 = COPY %zmm1
+# ALL-NEXT: %1:vr128x = COPY %0.sub_xmm
# ALL-NEXT: %xmm0 = COPY %1
# ALL-NEXT: RET 0, implicit %xmm0
body: |
@@ -58,8 +58,8 @@ regBankSelected: true
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
-# ALL: %0 = COPY %zmm1
-# ALL-NEXT: %1 = VEXTRACTF32x4Zrr %0, 1
+# ALL: %0:vr512 = COPY %zmm1
+# ALL-NEXT: %1:vr128x = VEXTRACTF32x4Zrr %0, 1
# ALL-NEXT: %xmm0 = COPY %1
# ALL-NEXT: RET 0, implicit %xmm0
body: |
@@ -84,8 +84,8 @@ regBankSelected: true
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
-# ALL: %0 = COPY %zmm1
-# ALL-NEXT: %1 = COPY %0.sub_ymm
+# ALL: %0:vr512 = COPY %zmm1
+# ALL-NEXT: %1:vr256x = COPY %0.sub_ymm
# ALL-NEXT: %ymm0 = COPY %1
# ALL-NEXT: RET 0, implicit %ymm0
body: |
@@ -110,8 +110,8 @@ regBankSelected: true
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
-# ALL: %0 = COPY %zmm1
-# ALL-NEXT: %1 = VEXTRACTF64x4Zrr %0, 1
+# ALL: %0:vr512 = COPY %zmm1
+# ALL-NEXT: %1:vr256x = VEXTRACTF64x4Zrr %0, 1
# ALL-NEXT: %ymm0 = COPY %1
# ALL-NEXT: RET 0, implicit %ymm0
body: |
@@ -124,4 +124,3 @@ body: |
RET 0, implicit %ymm0
...
-
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir Tue Oct 24 11:04:54 2017
@@ -38,21 +38,21 @@ liveins:
fixedStack:
stack:
constants:
-# SSE: %0 = COPY %xmm0
-# SSE-NEXT: %1 = COPY %xmm1
-# SSE-NEXT: %2 = ADDSSrr %0, %1
+# SSE: %0:fr32 = COPY %xmm0
+# SSE-NEXT: %1:fr32 = COPY %xmm1
+# SSE-NEXT: %2:fr32 = ADDSSrr %0, %1
# SSE-NEXT: %xmm0 = COPY %2
# SSE-NEXT: RET 0, implicit %xmm0
#
-# AVX: %0 = COPY %xmm0
-# AVX-NEXT: %1 = COPY %xmm1
-# AVX-NEXT: %2 = VADDSSrr %0, %1
+# AVX: %0:fr32 = COPY %xmm0
+# AVX-NEXT: %1:fr32 = COPY %xmm1
+# AVX-NEXT: %2:fr32 = VADDSSrr %0, %1
# AVX-NEXT: %xmm0 = COPY %2
# AVX-NEXT: RET 0, implicit %xmm0
#
-# AVX512ALL: %0 = COPY %xmm0
-# AVX512ALL-NEXT: %1 = COPY %xmm1
-# AVX512ALL-NEXT: %2 = VADDSSZrr %0, %1
+# AVX512ALL: %0:fr32x = COPY %xmm0
+# AVX512ALL-NEXT: %1:fr32x = COPY %xmm1
+# AVX512ALL-NEXT: %2:fr32x = VADDSSZrr %0, %1
# AVX512ALL-NEXT: %xmm0 = COPY %2
# AVX512ALL-NEXT: RET 0, implicit %xmm0
body: |
@@ -89,21 +89,21 @@ liveins:
fixedStack:
stack:
constants:
-# SSE: %0 = COPY %xmm0
-# SSE-NEXT: %1 = COPY %xmm1
-# SSE-NEXT: %2 = ADDSDrr %0, %1
+# SSE: %0:fr64 = COPY %xmm0
+# SSE-NEXT: %1:fr64 = COPY %xmm1
+# SSE-NEXT: %2:fr64 = ADDSDrr %0, %1
# SSE-NEXT: %xmm0 = COPY %2
# SSE-NEXT: RET 0, implicit %xmm0
#
-# AVX: %0 = COPY %xmm0
-# AVX-NEXT: %1 = COPY %xmm1
-# AVX-NEXT: %2 = VADDSDrr %0, %1
+# AVX: %0:fr64 = COPY %xmm0
+# AVX-NEXT: %1:fr64 = COPY %xmm1
+# AVX-NEXT: %2:fr64 = VADDSDrr %0, %1
# AVX-NEXT: %xmm0 = COPY %2
# AVX-NEXT: RET 0, implicit %xmm0
#
-# AVX512ALL: %0 = COPY %xmm0
-# AVX512ALL-NEXT: %1 = COPY %xmm1
-# AVX512ALL-NEXT: %2 = VADDSDZrr %0, %1
+# AVX512ALL: %0:fr64x = COPY %xmm0
+# AVX512ALL-NEXT: %1:fr64x = COPY %xmm1
+# AVX512ALL-NEXT: %2:fr64x = VADDSDZrr %0, %1
# AVX512ALL-NEXT: %xmm0 = COPY %2
# AVX512ALL-NEXT: RET 0, implicit %xmm0
body: |
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-fconstant.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-fconstant.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-fconstant.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-fconstant.mir Tue Oct 24 11:04:54 2017
@@ -23,27 +23,18 @@ alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
-# CHECK_SMALL64: registers:
-# CHECK_SMALL64-NEXT: - { id: 0, class: fr32, preferred-register: '' }
-#
-# CHECK_LARGE64: registers:
-# CHECK_LARGE64-NEXT: - { id: 0, class: fr32, preferred-register: '' }
-# CHECK_LARGE64-NEXT: - { id: 1, class: gr64, preferred-register: '' }
-#
-# CHECK32: registers:
-# CHECK32-NEXT: - { id: 0, class: fr32, preferred-register: '' }
registers:
- { id: 0, class: vecr, preferred-register: '' }
-# CHECK_SMALL64: %0 = MOVSSrm %rip, 1, _, %const.0, _
+# CHECK_SMALL64: %0:fr32 = MOVSSrm %rip, 1, _, %const.0, _
# CHECK_SMALL64-NEXT: %xmm0 = COPY %0
# CHECK_SMALL64-NEXT: RET 0, implicit %xmm0
#
-# CHECK_LARGE64: %1 = MOV64ri %const.0
-# CHECK_LARGE64-NEXT: %0 = MOVSSrm %1, 1, _, 0, _ :: (load 8 from constant-pool, align 32)
+# CHECK_LARGE64: %1:gr64 = MOV64ri %const.0
+# CHECK_LARGE64-NEXT: %0:fr32 = MOVSSrm %1, 1, _, 0, _ :: (load 8 from constant-pool, align 32)
# CHECK_LARGE64-NEXT: %xmm0 = COPY %0
# CHECK_LARGE64-NEXT: RET 0, implicit %xmm0
#
-# CHECK32: %0 = MOVSSrm _, 1, _, %const.0, _
+# CHECK32: %0:fr32 = MOVSSrm _, 1, _, %const.0, _
# CHECK32-NEXT: %xmm0 = COPY %0
# CHECK32-NEXT: RET 0, implicit %xmm0
body: |
@@ -73,16 +64,16 @@ tracksRegLiveness: true
# CHECK32-NEXT: - { id: 0, class: fr64, preferred-register: '' }
registers:
- { id: 0, class: vecr, preferred-register: '' }
-# CHECK_SMALL64: %0 = MOVSDrm %rip, 1, _, %const.0, _
+# CHECK_SMALL64: %0:fr64 = MOVSDrm %rip, 1, _, %const.0, _
# CHECK_SMALL64-NEXT: %xmm0 = COPY %0
# CHECK_SMALL64-NEXT: RET 0, implicit %xmm0
#
-# CHECK_LARGE64: %1 = MOV64ri %const.0
-# CHECK_LARGE64-NEXT: %0 = MOVSDrm %1, 1, _, 0, _ :: (load 8 from constant-pool, align 64)
+# CHECK_LARGE64: %1:gr64 = MOV64ri %const.0
+# CHECK_LARGE64-NEXT: %0:fr64 = MOVSDrm %1, 1, _, 0, _ :: (load 8 from constant-pool, align 64)
# CHECK_LARGE64-NEXT: %xmm0 = COPY %0
# CHECK_LARGE64-NEXT: RET 0, implicit %xmm0
#
-# CHECK32: %0 = MOVSDrm _, 1, _, %const.0, _
+# CHECK32: %0:fr64 = MOVSDrm _, 1, _, %const.0, _
# CHECK32-NEXT: %xmm0 = COPY %0
# CHECK32-NEXT: RET 0, implicit %xmm0
body: |
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir Tue Oct 24 11:04:54 2017
@@ -38,21 +38,21 @@ liveins:
fixedStack:
stack:
constants:
-# SSE: %0 = COPY %xmm0
-# SSE-NEXT: %1 = COPY %xmm1
-# SSE-NEXT: %2 = DIVSSrr %0, %1
+# SSE: %0:fr32 = COPY %xmm0
+# SSE-NEXT: %1:fr32 = COPY %xmm1
+# SSE-NEXT: %2:fr32 = DIVSSrr %0, %1
# SSE-NEXT: %xmm0 = COPY %2
# SSE-NEXT: RET 0, implicit %xmm0
#
-# AVX: %0 = COPY %xmm0
-# AVX-NEXT: %1 = COPY %xmm1
-# AVX-NEXT: %2 = VDIVSSrr %0, %1
+# AVX: %0:fr32 = COPY %xmm0
+# AVX-NEXT: %1:fr32 = COPY %xmm1
+# AVX-NEXT: %2:fr32 = VDIVSSrr %0, %1
# AVX-NEXT: %xmm0 = COPY %2
# AVX-NEXT: RET 0, implicit %xmm0
#
-# AVX512ALL: %0 = COPY %xmm0
-# AVX512ALL-NEXT: %1 = COPY %xmm1
-# AVX512ALL-NEXT: %2 = VDIVSSZrr %0, %1
+# AVX512ALL: %0:fr32x = COPY %xmm0
+# AVX512ALL-NEXT: %1:fr32x = COPY %xmm1
+# AVX512ALL-NEXT: %2:fr32x = VDIVSSZrr %0, %1
# AVX512ALL-NEXT: %xmm0 = COPY %2
# AVX512ALL-NEXT: RET 0, implicit %xmm0
body: |
@@ -89,21 +89,21 @@ liveins:
fixedStack:
stack:
constants:
-# SSE: %0 = COPY %xmm0
-# SSE-NEXT: %1 = COPY %xmm1
-# SSE-NEXT: %2 = DIVSDrr %0, %1
+# SSE: %0:fr64 = COPY %xmm0
+# SSE-NEXT: %1:fr64 = COPY %xmm1
+# SSE-NEXT: %2:fr64 = DIVSDrr %0, %1
# SSE-NEXT: %xmm0 = COPY %2
# SSE-NEXT: RET 0, implicit %xmm0
#
-# AVX: %0 = COPY %xmm0
-# AVX-NEXT: %1 = COPY %xmm1
-# AVX-NEXT: %2 = VDIVSDrr %0, %1
+# AVX: %0:fr64 = COPY %xmm0
+# AVX-NEXT: %1:fr64 = COPY %xmm1
+# AVX-NEXT: %2:fr64 = VDIVSDrr %0, %1
# AVX-NEXT: %xmm0 = COPY %2
# AVX-NEXT: RET 0, implicit %xmm0
#
-# AVX512ALL: %0 = COPY %xmm0
-# AVX512ALL-NEXT: %1 = COPY %xmm1
-# AVX512ALL-NEXT: %2 = VDIVSDZrr %0, %1
+# AVX512ALL: %0:fr64x = COPY %xmm0
+# AVX512ALL-NEXT: %1:fr64x = COPY %xmm1
+# AVX512ALL-NEXT: %2:fr64x = VDIVSDZrr %0, %1
# AVX512ALL-NEXT: %xmm0 = COPY %2
# AVX512ALL-NEXT: RET 0, implicit %xmm0
body: |
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir Tue Oct 24 11:04:54 2017
@@ -38,21 +38,21 @@ liveins:
fixedStack:
stack:
constants:
-# SSE: %0 = COPY %xmm0
-# SSE-NEXT: %1 = COPY %xmm1
-# SSE-NEXT: %2 = MULSSrr %0, %1
+# SSE: %0:fr32 = COPY %xmm0
+# SSE-NEXT: %1:fr32 = COPY %xmm1
+# SSE-NEXT: %2:fr32 = MULSSrr %0, %1
# SSE-NEXT: %xmm0 = COPY %2
# SSE-NEXT: RET 0, implicit %xmm0
#
-# AVX: %0 = COPY %xmm0
-# AVX-NEXT: %1 = COPY %xmm1
-# AVX-NEXT: %2 = VMULSSrr %0, %1
+# AVX: %0:fr32 = COPY %xmm0
+# AVX-NEXT: %1:fr32 = COPY %xmm1
+# AVX-NEXT: %2:fr32 = VMULSSrr %0, %1
# AVX-NEXT: %xmm0 = COPY %2
# AVX-NEXT: RET 0, implicit %xmm0
#
-# AVX512ALL: %0 = COPY %xmm0
-# AVX512ALL-NEXT: %1 = COPY %xmm1
-# AVX512ALL-NEXT: %2 = VMULSSZrr %0, %1
+# AVX512ALL: %0:fr32x = COPY %xmm0
+# AVX512ALL-NEXT: %1:fr32x = COPY %xmm1
+# AVX512ALL-NEXT: %2:fr32x = VMULSSZrr %0, %1
# AVX512ALL-NEXT: %xmm0 = COPY %2
# AVX512ALL-NEXT: RET 0, implicit %xmm0
body: |
@@ -89,21 +89,21 @@ liveins:
fixedStack:
stack:
constants:
-# SSE: %0 = COPY %xmm0
-# SSE-NEXT: %1 = COPY %xmm1
-# SSE-NEXT: %2 = MULSDrr %0, %1
+# SSE: %0:fr64 = COPY %xmm0
+# SSE-NEXT: %1:fr64 = COPY %xmm1
+# SSE-NEXT: %2:fr64 = MULSDrr %0, %1
# SSE-NEXT: %xmm0 = COPY %2
# SSE-NEXT: RET 0, implicit %xmm0
#
-# AVX: %0 = COPY %xmm0
-# AVX-NEXT: %1 = COPY %xmm1
-# AVX-NEXT: %2 = VMULSDrr %0, %1
+# AVX: %0:fr64 = COPY %xmm0
+# AVX-NEXT: %1:fr64 = COPY %xmm1
+# AVX-NEXT: %2:fr64 = VMULSDrr %0, %1
# AVX-NEXT: %xmm0 = COPY %2
# AVX-NEXT: RET 0, implicit %xmm0
#
-# AVX512ALL: %0 = COPY %xmm0
-# AVX512ALL-NEXT: %1 = COPY %xmm1
-# AVX512ALL-NEXT: %2 = VMULSDZrr %0, %1
+# AVX512ALL: %0:fr64x = COPY %xmm0
+# AVX512ALL-NEXT: %1:fr64x = COPY %xmm1
+# AVX512ALL-NEXT: %2:fr64x = VMULSDZrr %0, %1
# AVX512ALL-NEXT: %xmm0 = COPY %2
# AVX512ALL-NEXT: RET 0, implicit %xmm0
body: |
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir Tue Oct 24 11:04:54 2017
@@ -26,11 +26,8 @@ body: |
liveins: %xmm0
; ALL-LABEL: name: test
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: fr32
- ; ALL-NEXT: id: 1, class: fr64
- ; ALL: [[COPY:%[0-9]+]] = COPY %xmm0
- ; ALL: [[CVTSS2SDrr:%[0-9]+]] = CVTSS2SDrr [[COPY]]
+ ; ALL: [[COPY:%[0-9]+]]:fr32 = COPY %xmm0
+ ; ALL: [[CVTSS2SDrr:%[0-9]+]]:fr64 = CVTSS2SDrr [[COPY]]
; ALL: %xmm0 = COPY [[CVTSS2SDrr]]
; ALL: RET 0, implicit %xmm0
%0(s32) = COPY %xmm0
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir Tue Oct 24 11:04:54 2017
@@ -38,21 +38,21 @@ liveins:
fixedStack:
stack:
constants:
-# SSE: %0 = COPY %xmm0
-# SSE-NEXT: %1 = COPY %xmm1
-# SSE-NEXT: %2 = SUBSSrr %0, %1
+# SSE: %0:fr32 = COPY %xmm0
+# SSE-NEXT: %1:fr32 = COPY %xmm1
+# SSE-NEXT: %2:fr32 = SUBSSrr %0, %1
# SSE-NEXT: %xmm0 = COPY %2
# SSE-NEXT: RET 0, implicit %xmm0
#
-# AVX: %0 = COPY %xmm0
-# AVX-NEXT: %1 = COPY %xmm1
-# AVX-NEXT: %2 = VSUBSSrr %0, %1
+# AVX: %0:fr32 = COPY %xmm0
+# AVX-NEXT: %1:fr32 = COPY %xmm1
+# AVX-NEXT: %2:fr32 = VSUBSSrr %0, %1
# AVX-NEXT: %xmm0 = COPY %2
# AVX-NEXT: RET 0, implicit %xmm0
#
-# AVX512ALL: %0 = COPY %xmm0
-# AVX512ALL-NEXT: %1 = COPY %xmm1
-# AVX512ALL-NEXT: %2 = VSUBSSZrr %0, %1
+# AVX512ALL: %0:fr32x = COPY %xmm0
+# AVX512ALL-NEXT: %1:fr32x = COPY %xmm1
+# AVX512ALL-NEXT: %2:fr32x = VSUBSSZrr %0, %1
# AVX512ALL-NEXT: %xmm0 = COPY %2
# AVX512ALL-NEXT: RET 0, implicit %xmm0
body: |
@@ -89,21 +89,21 @@ liveins:
fixedStack:
stack:
constants:
-# SSE: %0 = COPY %xmm0
-# SSE-NEXT: %1 = COPY %xmm1
-# SSE-NEXT: %2 = SUBSDrr %0, %1
+# SSE: %0:fr64 = COPY %xmm0
+# SSE-NEXT: %1:fr64 = COPY %xmm1
+# SSE-NEXT: %2:fr64 = SUBSDrr %0, %1
# SSE-NEXT: %xmm0 = COPY %2
# SSE-NEXT: RET 0, implicit %xmm0
#
-# AVX: %0 = COPY %xmm0
-# AVX-NEXT: %1 = COPY %xmm1
-# AVX-NEXT: %2 = VSUBSDrr %0, %1
+# AVX: %0:fr64 = COPY %xmm0
+# AVX-NEXT: %1:fr64 = COPY %xmm1
+# AVX-NEXT: %2:fr64 = VSUBSDrr %0, %1
# AVX-NEXT: %xmm0 = COPY %2
# AVX-NEXT: RET 0, implicit %xmm0
#
-# AVX512ALL: %0 = COPY %xmm0
-# AVX512ALL-NEXT: %1 = COPY %xmm1
-# AVX512ALL-NEXT: %2 = VSUBSDZrr %0, %1
+# AVX512ALL: %0:fr64x = COPY %xmm0
+# AVX512ALL-NEXT: %1:fr64x = COPY %xmm1
+# AVX512ALL-NEXT: %2:fr64x = VSUBSDZrr %0, %1
# AVX512ALL-NEXT: %xmm0 = COPY %2
# AVX512ALL-NEXT: RET 0, implicit %xmm0
body: |
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-gep.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-gep.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-gep.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-gep.mir Tue Oct 24 11:04:54 2017
@@ -22,13 +22,9 @@ body: |
liveins: %rdi
; CHECK-LABEL: name: test_gep_i32
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: gr64
- ; CHECK-NEXT: id: 1, class: gr64_nosp
- ; CHECK-NEXT: id: 2, class: gr64
- ; CHECK: [[COPY:%[0-9]+]] = COPY %rdi
- ; CHECK: [[MOV64ri32_:%[0-9]+]] = MOV64ri32 20
- ; CHECK: [[LEA64r:%[0-9]+]] = LEA64r [[COPY]], 1, [[MOV64ri32_]], 0, _
+ ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+ ; CHECK: [[MOV64ri32_:%[0-9]+]]:gr64_nosp = MOV64ri32 20
+ ; CHECK: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri32_]], 0, _
; CHECK: %rax = COPY [[LEA64r]]
; CHECK: RET 0, implicit %rax
%0(p0) = COPY %rdi
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-inc.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-inc.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-inc.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-inc.mir Tue Oct 24 11:04:54 2017
@@ -21,9 +21,9 @@ registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
-# ALL: %0 = COPY %al
-# INC-NEXT: %2 = INC8r %0
-# ADD-NEXT: %2 = ADD8ri %0, 1
+# ALL: %0:gr8 = COPY %al
+# INC-NEXT: %2:gr8 = INC8r %0
+# ADD-NEXT: %2:gr8 = ADD8ri %0, 1
body: |
bb.1 (%ir-block.0):
liveins: %al
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir Tue Oct 24 11:04:54 2017
@@ -24,28 +24,19 @@ name: test_insert_128_idx0
alignment: 4
legalized: true
regBankSelected: true
-# AVX: registers:
-# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '' }
-# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '' }
-# AVX-NEXT: - { id: 2, class: vr256, preferred-register: '' }
-#
-# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
-# AVX: %0 = COPY %ymm0
-# AVX-NEXT: %1 = COPY %xmm1
-# AVX-NEXT: %2 = VINSERTF128rr %0, %1, 0
+# AVX: %0:vr256 = COPY %ymm0
+# AVX-NEXT: %1:vr128 = COPY %xmm1
+# AVX-NEXT: %2:vr256 = VINSERTF128rr %0, %1, 0
# AVX-NEXT: %ymm0 = COPY %2
# AVX-NEXT: RET 0, implicit %ymm0
#
-# AVX512VL: %0 = COPY %ymm0
-# AVX512VL-NEXT: %1 = COPY %xmm1
-# AVX512VL-NEXT: %2 = VINSERTF32x4Z256rr %0, %1, 0
+# AVX512VL: %0:vr256x = COPY %ymm0
+# AVX512VL-NEXT: %1:vr128x = COPY %xmm1
+# AVX512VL-NEXT: %2:vr256x = VINSERTF32x4Z256rr %0, %1, 0
# AVX512VL-NEXT: %ymm0 = COPY %2
# AVX512VL-NEXT: RET 0, implicit %ymm0
body: |
@@ -65,23 +56,19 @@ name: test_insert_128_idx0_un
alignment: 4
legalized: true
regBankSelected: true
-# AVX: registers:
-# AVX-NEXT: - { id: 0, class: vecr, preferred-register: '' }
-# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '' }
-# AVX-NEXT: - { id: 2, class: vr256, preferred-register: '' }
-#
-# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vecr, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
-# ALL: %1 = COPY %xmm1
-# ALL-NEXT: undef %2.sub_xmm = COPY %1
-# ALL-NEXT: %ymm0 = COPY %2
-# ALL-NEXT: RET 0, implicit %ymm0
+# AVX: %1:vr128 = COPY %xmm1
+# AVX-NEXT: undef %2.sub_xmm:vr256 = COPY %1
+# AVX-NEXT: %ymm0 = COPY %2
+# AVX-NEXT: RET 0, implicit %ymm0
+#
+# AVX512VL: %1:vr128x = COPY %xmm1
+# AVX512VL-NEXT: undef %2.sub_xmm:vr256x = COPY %1
+# AVX512VL-NEXT: %ymm0 = COPY %2
+# AVX512VL-NEXT: RET 0, implicit %ymm0
body: |
bb.1 (%ir-block.0):
liveins: %ymm0, %ymm1
@@ -99,28 +86,19 @@ name: test_insert_128_idx1
alignment: 4
legalized: true
regBankSelected: true
-# AVX: registers:
-# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '' }
-# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '' }
-# AVX-NEXT: - { id: 2, class: vr256, preferred-register: '' }
-#
-# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
-# AVX: %0 = COPY %ymm0
-# AVX-NEXT: %1 = COPY %xmm1
-# AVX-NEXT: %2 = VINSERTF128rr %0, %1, 1
+# AVX: %0:vr256 = COPY %ymm0
+# AVX-NEXT: %1:vr128 = COPY %xmm1
+# AVX-NEXT: %2:vr256 = VINSERTF128rr %0, %1, 1
# AVX-NEXT: %ymm0 = COPY %2
# AVX-NEXT: RET 0, implicit %ymm0
#
-# AVX512VL: %0 = COPY %ymm0
-# AVX512VL-NEXT: %1 = COPY %xmm1
-# AVX512VL-NEXT: %2 = VINSERTF32x4Z256rr %0, %1, 1
+# AVX512VL: %0:vr256x = COPY %ymm0
+# AVX512VL-NEXT: %1:vr128x = COPY %xmm1
+# AVX512VL-NEXT: %2:vr256x = VINSERTF32x4Z256rr %0, %1, 1
# AVX512VL-NEXT: %ymm0 = COPY %2
# AVX512VL-NEXT: RET 0, implicit %ymm0
body: |
@@ -139,28 +117,19 @@ name: test_insert_128_idx1_un
alignment: 4
legalized: true
regBankSelected: true
-# AVX: registers:
-# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '' }
-# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '' }
-# AVX-NEXT: - { id: 2, class: vr256, preferred-register: '' }
-#
-# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
-# AVX: %0 = IMPLICIT_DEF
-# AVX-NEXT: %1 = COPY %xmm1
-# AVX-NEXT: %2 = VINSERTF128rr %0, %1, 1
+# AVX: %0:vr256 = IMPLICIT_DEF
+# AVX-NEXT: %1:vr128 = COPY %xmm1
+# AVX-NEXT: %2:vr256 = VINSERTF128rr %0, %1, 1
# AVX-NEXT: %ymm0 = COPY %2
# AVX-NEXT: RET 0, implicit %ymm0
#
-# AVX512VL: %0 = IMPLICIT_DEF
-# AVX512VL-NEXT: %1 = COPY %xmm1
-# AVX512VL-NEXT: %2 = VINSERTF32x4Z256rr %0, %1, 1
+# AVX512VL: %0:vr256x = IMPLICIT_DEF
+# AVX512VL-NEXT: %1:vr128x = COPY %xmm1
+# AVX512VL-NEXT: %2:vr256x = VINSERTF32x4Z256rr %0, %1, 1
# AVX512VL-NEXT: %ymm0 = COPY %2
# AVX512VL-NEXT: RET 0, implicit %ymm0
body: |
@@ -173,4 +142,3 @@ body: |
%ymm0 = COPY %2(<8 x s32>)
RET 0, implicit %ymm0
...
-
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir Tue Oct 24 11:04:54 2017
@@ -49,13 +49,9 @@ body: |
liveins: %zmm0, %ymm1
; ALL-LABEL: name: test_insert_128_idx0
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: vr512
- ; ALL-NEXT: id: 1, class: vr128x
- ; ALL-NEXT: id: 2, class: vr512
- ; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
- ; ALL: [[COPY1:%[0-9]+]] = COPY %xmm1
- ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]] = VINSERTF32x4Zrr [[COPY]], [[COPY1]], 0
+ ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+ ; ALL: [[COPY1:%[0-9]+]]:vr128x = COPY %xmm1
+ ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[COPY]], [[COPY1]], 0
; ALL: %zmm0 = COPY [[VINSERTF32x4Zrr]]
; ALL: RET 0, implicit %ymm0
%0(<16 x s32>) = COPY %zmm0
@@ -79,12 +75,8 @@ body: |
liveins: %ymm0, %ymm1
; ALL-LABEL: name: test_insert_128_idx0_undef
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: vecr
- ; ALL-NEXT: id: 1, class: vr128x
- ; ALL-NEXT: id: 2, class: vr512
- ; ALL: [[COPY:%[0-9]+]] = COPY %xmm1
- ; ALL: undef %2.sub_xmm = COPY [[COPY]]
+ ; ALL: [[COPY:%[0-9]+]]:vr128x = COPY %xmm1
+ ; ALL: undef %2.sub_xmm:vr512 = COPY [[COPY]]
; ALL: %zmm0 = COPY %2
; ALL: RET 0, implicit %ymm0
%0(<16 x s32>) = IMPLICIT_DEF
@@ -108,13 +100,9 @@ body: |
liveins: %ymm0, %ymm1
; ALL-LABEL: name: test_insert_128_idx1
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: vr512
- ; ALL-NEXT: id: 1, class: vr128x
- ; ALL-NEXT: id: 2, class: vr512
- ; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
- ; ALL: [[COPY1:%[0-9]+]] = COPY %xmm1
- ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]] = VINSERTF32x4Zrr [[COPY]], [[COPY1]], 1
+ ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+ ; ALL: [[COPY1:%[0-9]+]]:vr128x = COPY %xmm1
+ ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[COPY]], [[COPY1]], 1
; ALL: %zmm0 = COPY [[VINSERTF32x4Zrr]]
; ALL: RET 0, implicit %ymm0
%0(<16 x s32>) = COPY %zmm0
@@ -137,13 +125,9 @@ body: |
liveins: %ymm0, %ymm1
; ALL-LABEL: name: test_insert_128_idx1_undef
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: vr512
- ; ALL-NEXT: id: 1, class: vr128x
- ; ALL-NEXT: id: 2, class: vr512
- ; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
- ; ALL: [[COPY:%[0-9]+]] = COPY %xmm1
- ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]] = VINSERTF32x4Zrr [[DEF]], [[COPY]], 1
+ ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF
+ ; ALL: [[COPY:%[0-9]+]]:vr128x = COPY %xmm1
+ ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[DEF]], [[COPY]], 1
; ALL: %zmm0 = COPY [[VINSERTF32x4Zrr]]
; ALL: RET 0, implicit %ymm0
%0(<16 x s32>) = IMPLICIT_DEF
@@ -166,13 +150,9 @@ body: |
liveins: %zmm0, %ymm1
; ALL-LABEL: name: test_insert_256_idx0
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: vr512
- ; ALL-NEXT: id: 1, class: vr256x
- ; ALL-NEXT: id: 2, class: vr512
- ; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
- ; ALL: [[COPY1:%[0-9]+]] = COPY %ymm1
- ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]] = VINSERTF64x4Zrr [[COPY]], [[COPY1]], 0
+ ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+ ; ALL: [[COPY1:%[0-9]+]]:vr256x = COPY %ymm1
+ ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]]:vr512 = VINSERTF64x4Zrr [[COPY]], [[COPY1]], 0
; ALL: %zmm0 = COPY [[VINSERTF64x4Zrr]]
; ALL: RET 0, implicit %ymm0
%0(<16 x s32>) = COPY %zmm0
@@ -196,12 +176,8 @@ body: |
liveins: %ymm0, %ymm1
; ALL-LABEL: name: test_insert_256_idx0_undef
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: vecr
- ; ALL-NEXT: id: 1, class: vr256x
- ; ALL-NEXT: id: 2, class: vr512
- ; ALL: [[COPY:%[0-9]+]] = COPY %ymm1
- ; ALL: undef %2.sub_ymm = COPY [[COPY]]
+ ; ALL: [[COPY:%[0-9]+]]:vr256x = COPY %ymm1
+ ; ALL: undef %2.sub_ymm:vr512 = COPY [[COPY]]
; ALL: %zmm0 = COPY %2
; ALL: RET 0, implicit %ymm0
%0(<16 x s32>) = IMPLICIT_DEF
@@ -225,13 +201,9 @@ body: |
liveins: %ymm0, %ymm1
; ALL-LABEL: name: test_insert_256_idx1
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: vr512
- ; ALL-NEXT: id: 1, class: vr256x
- ; ALL-NEXT: id: 2, class: vr512
- ; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
- ; ALL: [[COPY1:%[0-9]+]] = COPY %ymm1
- ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]] = VINSERTF64x4Zrr [[COPY]], [[COPY1]], 1
+ ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+ ; ALL: [[COPY1:%[0-9]+]]:vr256x = COPY %ymm1
+ ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]]:vr512 = VINSERTF64x4Zrr [[COPY]], [[COPY1]], 1
; ALL: %zmm0 = COPY [[VINSERTF64x4Zrr]]
; ALL: RET 0, implicit %ymm0
%0(<16 x s32>) = COPY %zmm0
@@ -254,13 +226,9 @@ body: |
liveins: %ymm0, %ymm1
; ALL-LABEL: name: test_insert_256_idx1_undef
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: vr512
- ; ALL-NEXT: id: 1, class: vr256x
- ; ALL-NEXT: id: 2, class: vr512
- ; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
- ; ALL: [[COPY:%[0-9]+]] = COPY %ymm1
- ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]] = VINSERTF64x4Zrr [[DEF]], [[COPY]], 1
+ ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF
+ ; ALL: [[COPY:%[0-9]+]]:vr256x = COPY %ymm1
+ ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]]:vr512 = VINSERTF64x4Zrr [[DEF]], [[COPY]], 1
; ALL: %zmm0 = COPY [[VINSERTF64x4Zrr]]
; ALL: RET 0, implicit %ymm0
%0(<16 x s32>) = IMPLICIT_DEF
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-intrinsic-x86-flags-read-u32.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-intrinsic-x86-flags-read-u32.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-intrinsic-x86-flags-read-u32.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-intrinsic-x86-flags-read-u32.mir Tue Oct 24 11:04:54 2017
@@ -19,11 +19,8 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: read_flags
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: gr32
- ; CHECK-NEXT: id: 1, class: gr64
- ; CHECK: [[RDFLAGS32_:%[0-9]+]] = RDFLAGS32 implicit-def %esp, implicit %esp
- ; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[RDFLAGS32_]], 4
+ ; CHECK: [[RDFLAGS32_:%[0-9]+]]:gr32 = RDFLAGS32 implicit-def %esp, implicit %esp
+ ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[RDFLAGS32_]], 4
; CHECK: %rax = COPY [[SUBREG_TO_REG]]
%0(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.flags.read.u32)
%rax = COPY %0(s32)
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir Tue Oct 24 11:04:54 2017
@@ -33,9 +33,7 @@ registers:
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: const_i32_1
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: gr32
- ; CHECK: [[MOV32ri:%[0-9]+]] = MOV32ri 1
+ ; CHECK: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1
; CHECK: %eax = COPY [[MOV32ri]]
; CHECK: RET 0, implicit %eax
%0(s32) = G_CONSTANT i32 1
@@ -52,9 +50,7 @@ registers:
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: const_i32_1_optsize
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: gr32
- ; CHECK: [[MOV32r1_:%[0-9]+]] = MOV32r1 implicit-def %eflags
+ ; CHECK: [[MOV32r1_:%[0-9]+]]:gr32 = MOV32r1 implicit-def %eflags
; CHECK: %eax = COPY [[MOV32r1_]]
; CHECK: RET 0, implicit %eax
%0(s32) = G_CONSTANT i32 1
@@ -71,9 +67,7 @@ registers:
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: const_i32_1b
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: gr32
- ; CHECK: [[MOV32ri:%[0-9]+]] = MOV32ri 1
+ ; CHECK: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1
; CHECK: %eax = COPY [[MOV32ri]]
; CHECK: RET 0, implicit %eax
%0(s32) = G_CONSTANT i32 1
@@ -90,9 +84,7 @@ registers:
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: const_i32_1_optsizeb
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: gr32
- ; CHECK: [[MOV32r1_:%[0-9]+]] = MOV32r1 implicit-def %eflags
+ ; CHECK: [[MOV32r1_:%[0-9]+]]:gr32 = MOV32r1 implicit-def %eflags
; CHECK: %eax = COPY [[MOV32r1_]]
; CHECK: RET 0, implicit %eax
%0(s32) = G_CONSTANT i32 1
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir Tue Oct 24 11:04:54 2017
@@ -57,12 +57,8 @@ fixedStack:
body: |
bb.1 (%ir-block.0):
; ALL-LABEL: name: test_load_i8
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr32
- ; ALL-NEXT: id: 1, class: gpr
- ; ALL-NEXT: id: 2, class: gr8
- ; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
- ; ALL: [[MOV8rm:%[0-9]+]] = MOV8rm [[MOV32rm]], 1, _, 0, _ :: (load 1 from %ir.p1)
+ ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
+ ; ALL: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[MOV32rm]], 1, _, 0, _ :: (load 1 from %ir.p1)
; ALL: %al = COPY [[MOV8rm]]
; ALL: RET 0, implicit %al
%1(p0) = G_FRAME_INDEX %fixed-stack.0
@@ -86,12 +82,8 @@ fixedStack:
body: |
bb.1 (%ir-block.0):
; ALL-LABEL: name: test_load_i16
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr32
- ; ALL-NEXT: id: 1, class: gpr
- ; ALL-NEXT: id: 2, class: gr16
- ; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
- ; ALL: [[MOV16rm:%[0-9]+]] = MOV16rm [[MOV32rm]], 1, _, 0, _ :: (load 2 from %ir.p1)
+ ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
+ ; ALL: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[MOV32rm]], 1, _, 0, _ :: (load 2 from %ir.p1)
; ALL: %ax = COPY [[MOV16rm]]
; ALL: RET 0, implicit %ax
%1(p0) = G_FRAME_INDEX %fixed-stack.0
@@ -115,12 +107,8 @@ fixedStack:
body: |
bb.1 (%ir-block.0):
; ALL-LABEL: name: test_load_i32
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr32
- ; ALL-NEXT: id: 1, class: gpr
- ; ALL-NEXT: id: 2, class: gr32
- ; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
- ; ALL: [[MOV32rm1:%[0-9]+]] = MOV32rm [[MOV32rm]], 1, _, 0, _ :: (load 4 from %ir.p1)
+ ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
+ ; ALL: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm [[MOV32rm]], 1, _, 0, _ :: (load 4 from %ir.p1)
; ALL: %eax = COPY [[MOV32rm1]]
; ALL: RET 0, implicit %eax
%1(p0) = G_FRAME_INDEX %fixed-stack.0
@@ -146,13 +134,8 @@ fixedStack:
body: |
bb.1 (%ir-block.0):
; ALL-LABEL: name: test_store_i8
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr8
- ; ALL-NEXT: id: 1, class: gr32
- ; ALL-NEXT: id: 2, class: gpr
- ; ALL-NEXT: id: 3, class: gpr
- ; ALL: [[MOV8rm:%[0-9]+]] = MOV8rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 1 from %fixed-stack.0, align 0)
- ; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
+ ; ALL: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 1 from %fixed-stack.0, align 0)
+ ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
; ALL: MOV8mr [[MOV32rm]], 1, _, 0, _, [[MOV8rm]] :: (store 1 into %ir.p1)
; ALL: %eax = COPY [[MOV32rm]]
; ALL: RET 0, implicit %eax
@@ -181,13 +164,8 @@ fixedStack:
body: |
bb.1 (%ir-block.0):
; ALL-LABEL: name: test_store_i16
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr16
- ; ALL-NEXT: id: 1, class: gr32
- ; ALL-NEXT: id: 2, class: gpr
- ; ALL-NEXT: id: 3, class: gpr
- ; ALL: [[MOV16rm:%[0-9]+]] = MOV16rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 2 from %fixed-stack.0, align 0)
- ; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
+ ; ALL: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 2 from %fixed-stack.0, align 0)
+ ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
; ALL: MOV16mr [[MOV32rm]], 1, _, 0, _, [[MOV16rm]] :: (store 2 into %ir.p1)
; ALL: %eax = COPY [[MOV32rm]]
; ALL: RET 0, implicit %eax
@@ -216,13 +194,8 @@ fixedStack:
body: |
bb.1 (%ir-block.0):
; ALL-LABEL: name: test_store_i32
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr32
- ; ALL-NEXT: id: 1, class: gr32
- ; ALL-NEXT: id: 2, class: gpr
- ; ALL-NEXT: id: 3, class: gpr
- ; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
- ; ALL: [[MOV32rm1:%[0-9]+]] = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
+ ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
+ ; ALL: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
; ALL: MOV32mr [[MOV32rm1]], 1, _, 0, _, [[MOV32rm]] :: (store 4 into %ir.p1)
; ALL: %eax = COPY [[MOV32rm1]]
; ALL: RET 0, implicit %eax
@@ -249,12 +222,8 @@ fixedStack:
body: |
bb.1 (%ir-block.0):
; ALL-LABEL: name: test_load_ptr
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr32
- ; ALL-NEXT: id: 1, class: gpr
- ; ALL-NEXT: id: 2, class: gr32
- ; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
- ; ALL: [[MOV32rm1:%[0-9]+]] = MOV32rm [[MOV32rm]], 1, _, 0, _ :: (load 4 from %ir.ptr1)
+ ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
+ ; ALL: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm [[MOV32rm]], 1, _, 0, _ :: (load 4 from %ir.ptr1)
; ALL: %eax = COPY [[MOV32rm1]]
; ALL: RET 0, implicit %eax
%1(p0) = G_FRAME_INDEX %fixed-stack.0
@@ -280,13 +249,8 @@ fixedStack:
body: |
bb.1 (%ir-block.0):
; ALL-LABEL: name: test_store_ptr
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr32
- ; ALL-NEXT: id: 1, class: gr32
- ; ALL-NEXT: id: 2, class: gpr
- ; ALL-NEXT: id: 3, class: gpr
- ; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
- ; ALL: [[MOV32rm1:%[0-9]+]] = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
+ ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
+ ; ALL: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
; ALL: MOV32mr [[MOV32rm]], 1, _, 0, _, [[MOV32rm1]] :: (store 4 into %ir.ptr1)
; ALL: RET 0
%2(p0) = G_FRAME_INDEX %fixed-stack.1
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir Tue Oct 24 11:04:54 2017
@@ -109,8 +109,8 @@ registers:
# ALL: - { id: 1, class: gr8, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: gpr }
-# ALL: %0 = COPY %rdi
-# ALL: %1 = MOV8rm %0, 1, _, 0, _ :: (load 1 from %ir.p1)
+# ALL: %0:gr64 = COPY %rdi
+# ALL: %1:gr8 = MOV8rm %0, 1, _, 0, _ :: (load 1 from %ir.p1)
# ALL: %al = COPY %1
body: |
bb.1 (%ir-block.0):
@@ -133,8 +133,8 @@ registers:
# ALL: - { id: 1, class: gr16, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: gpr }
-# ALL: %0 = COPY %rdi
-# ALL: %1 = MOV16rm %0, 1, _, 0, _ :: (load 2 from %ir.p1)
+# ALL: %0:gr64 = COPY %rdi
+# ALL: %1:gr16 = MOV16rm %0, 1, _, 0, _ :: (load 2 from %ir.p1)
# ALL: %ax = COPY %1
body: |
bb.1 (%ir-block.0):
@@ -157,8 +157,8 @@ registers:
# ALL: - { id: 1, class: gr32, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: gpr }
-# ALL: %0 = COPY %rdi
-# ALL: %1 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
+# ALL: %0:gr64 = COPY %rdi
+# ALL: %1:gr32 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
# ALL: %eax = COPY %1
body: |
bb.1 (%ir-block.0):
@@ -181,8 +181,8 @@ registers:
# ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: gpr }
-# ALL: %0 = COPY %rdi
-# ALL: %1 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
+# ALL: %0:gr64 = COPY %rdi
+# ALL: %1:gr64 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
# ALL: %rax = COPY %1
body: |
bb.1 (%ir-block.0):
@@ -205,8 +205,8 @@ registers:
# ALL: - { id: 1, class: gr32, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: gpr }
-# ALL: %0 = COPY %rdi
-# ALL: %1 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
+# ALL: %0:gr64 = COPY %rdi
+# ALL: %1:gr32 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
# ALL: %xmm0 = COPY %1
body: |
bb.1 (%ir-block.0):
@@ -225,15 +225,12 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
-# ALL: - { id: 0, class: gr64, preferred-register: '' }
-# NO_AVX512F: - { id: 1, class: fr32, preferred-register: '' }
-# AVX512ALL: - { id: 1, class: fr32x, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: vecr }
-# ALL: %0 = COPY %rdi
-# SSE: %1 = MOVSSrm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
-# AVX: %1 = VMOVSSrm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
-# AVX512ALL: %1 = VMOVSSZrm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
+# ALL: %0:gr64 = COPY %rdi
+# SSE: %1:fr32 = MOVSSrm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
+# AVX: %1:fr32 = VMOVSSrm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
+# AVX512ALL: %1:fr32x = VMOVSSZrm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
# ALL: %xmm0 = COPY %1
body: |
bb.1 (%ir-block.0):
@@ -256,8 +253,8 @@ registers:
# ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: gpr }
-# ALL: %0 = COPY %rdi
-# ALL: %1 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
+# ALL: %0:gr64 = COPY %rdi
+# ALL: %1:gr64 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
# ALL: %xmm0 = COPY %1
body: |
bb.1 (%ir-block.0):
@@ -276,15 +273,12 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
-# ALL: - { id: 0, class: gr64, preferred-register: '' }
-# NO_AVX512F: - { id: 1, class: fr64, preferred-register: '' }
-# AVX512ALL: - { id: 1, class: fr64x, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: vecr }
-# ALL: %0 = COPY %rdi
-# SSE: %1 = MOVSDrm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
-# AVX: %1 = VMOVSDrm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
-# AVX512ALL: %1 = VMOVSDZrm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
+# ALL: %0:gr64 = COPY %rdi
+# SSE: %1:fr64 = MOVSDrm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
+# AVX: %1:fr64 = VMOVSDrm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
+# AVX512ALL: %1:fr64x = VMOVSDZrm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
# ALL: %xmm0 = COPY %1
body: |
bb.1 (%ir-block.0):
@@ -307,8 +301,8 @@ registers:
# ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: gpr }
-# ALL: %0 = COPY %edi
-# ALL: %1 = COPY %rsi
+# ALL: %0:gr32 = COPY %edi
+# ALL: %1:gr64 = COPY %rsi
# ALL: MOV32mr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
# ALL: %rax = COPY %1
body: |
@@ -333,8 +327,8 @@ registers:
# ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: gpr }
-# ALL: %0 = COPY %rdi
-# ALL: %1 = COPY %rsi
+# ALL: %0:gr64 = COPY %rdi
+# ALL: %1:gr64 = COPY %rsi
# ALL: MOV64mr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1)
# ALL: %rax = COPY %1
body: |
@@ -354,22 +348,14 @@ name: test_store_float
alignment: 4
legalized: true
regBankSelected: true
-# NO_AVX512F: registers:
-# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 2, class: gr32, preferred-register: '' }
-#
-# AVX512ALL: registers:
-# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
-# ALL: %0 = COPY %xmm0
-# ALL: %1 = COPY %rdi
-# ALL: %2 = COPY %0
+# NO_AVX512F: %0:fr32 = COPY %xmm0
+# AVX512ALL: %0:fr32x = COPY %xmm0
+# ALL: %1:gr64 = COPY %rdi
+# ALL: %2:gr32 = COPY %0
# ALL: MOV32mr %1, 1, _, 0, _, %2 :: (store 4 into %ir.p1)
# ALL: %rax = COPY %1
body: |
@@ -391,13 +377,11 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
-# NO_AVX512F: - { id: 0, class: fr32, preferred-register: '' }
-# AVX512ALL: - { id: 0, class: fr32x, preferred-register: '' }
-# ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: vecr }
- { id: 1, class: gpr }
-# ALL: %0 = COPY %xmm0
-# ALL: %1 = COPY %rdi
+# NO_AVX512F: %0:fr32 = COPY %xmm0
+# AVX512ALL: %0:fr32x = COPY %xmm0
+# ALL: %1:gr64 = COPY %rdi
# SSE: MOVSSmr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
# AVX: VMOVSSmr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
# AVX512ALL: VMOVSSZmr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
@@ -419,22 +403,14 @@ name: test_store_double
alignment: 4
legalized: true
regBankSelected: true
-# NO_AVX512F: registers:
-# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 2, class: gr64, preferred-register: '' }
-#
-# AVX512ALL: registers:
-# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
-# ALL: %0 = COPY %xmm0
-# ALL: %1 = COPY %rdi
-# ALL: %2 = COPY %0
+# NO_AVX512X: %0:fr64 = COPY %xmm0
+# AVX512ALL: %0:fr64x = COPY %xmm0
+# ALL: %1:gr64 = COPY %rdi
+# ALL: %2:gr64 = COPY %0
# ALL: MOV64mr %1, 1, _, 0, _, %2 :: (store 8 into %ir.p1)
# ALL: %rax = COPY %1
body: |
@@ -456,13 +432,11 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
-# NO_AVX512F: - { id: 0, class: fr64, preferred-register: '' }
-# AVX512ALL: - { id: 0, class: fr64x, preferred-register: '' }
-# ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: vecr }
- { id: 1, class: gpr }
-# ALL: %0 = COPY %xmm0
-# ALL: %1 = COPY %rdi
+# NO_AVX512F: %0:fr64 = COPY %xmm0
+# AVX512ALL: %0:fr64x = COPY %xmm0
+# ALL: %1:gr64 = COPY %rdi
# SSE: MOVSDmr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1)
# AVX: VMOVSDmr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1)
# AVX512ALL: VMOVSDZmr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1)
@@ -490,7 +464,7 @@ registers:
# ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: gpr }
-# ALL: %1 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.ptr1)
+# ALL: %1:gr64 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.ptr1)
body: |
bb.1 (%ir-block.0):
liveins: %rdi
@@ -542,10 +516,10 @@ registers:
- { id: 2, class: gpr }
- { id: 3, class: gpr }
- { id: 4, class: gpr }
-# ALL: %0 = COPY %rdi
-# ALL-NEXT: %1 = COPY %esi
+# ALL: %0:gr64 = COPY %rdi
+# ALL-NEXT: %1:gr32 = COPY %esi
# ALL-NEXT: MOV32mr %0, 1, _, 20, _, %1 :: (store 4 into %ir.arrayidx)
-# ALL-NEXT: %4 = MOV32rm %0, 1, _, 20, _ :: (load 4 from %ir.arrayidx)
+# ALL-NEXT: %4:gr32 = MOV32rm %0, 1, _, 20, _ :: (load 4 from %ir.arrayidx)
# ALL-NEXT: %eax = COPY %4
# ALL-NEXT: RET 0, implicit %eax
body: |
@@ -580,12 +554,12 @@ registers:
- { id: 2, class: gpr }
- { id: 3, class: gpr }
- { id: 4, class: gpr }
-# ALL: %0 = COPY %rdi
-# ALL-NEXT: %1 = COPY %esi
-# ALL-NEXT: %2 = MOV64ri 228719476720
-# ALL-NEXT: %3 = LEA64r %0, 1, %2, 0, _
+# ALL: %0:gr64 = COPY %rdi
+# ALL-NEXT: %1:gr32 = COPY %esi
+# ALL-NEXT: %2:gr64_nosp = MOV64ri 228719476720
+# ALL-NEXT: %3:gr64 = LEA64r %0, 1, %2, 0, _
# ALL-NEXT: MOV32mr %3, 1, _, 0, _, %1 :: (store 4 into %ir.arrayidx)
-# ALL-NEXT: %4 = MOV32rm %3, 1, _, 0, _ :: (load 4 from %ir.arrayidx)
+# ALL-NEXT: %4:gr32 = MOV32rm %3, 1, _, 0, _ :: (load 4 from %ir.arrayidx)
# ALL-NEXT: %eax = COPY %4
# ALL-NEXT: RET 0, implicit %eax
body: |
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v128.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v128.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v128.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v128.mir Tue Oct 24 11:04:54 2017
@@ -32,16 +32,13 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
-# ALL: - { id: 0, class: gr64, preferred-register: '' }
-# NO_AVX512F: - { id: 1, class: vr128, preferred-register: '' }
-# AVX512ALL: - { id: 1, class: vr128x, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: vecr }
-# ALL: %0 = COPY %rdi
-# SSE: %1 = MOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
-# AVX: %1 = VMOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
-# AVX512F: %1 = VMOVUPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
-# AVX512VL: %1 = VMOVUPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
+# ALL: %0:gr64 = COPY %rdi
+# SSE: %1:vr128 = MOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
+# AVX: %1:vr128 = VMOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
+# AVX512F: %1:vr128x = VMOVUPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
+# AVX512VL: %1:vr128x = VMOVUPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
# ALL: %xmm0 = COPY %1
body: |
bb.1 (%ir-block.0):
@@ -60,16 +57,13 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
-# ALL: - { id: 0, class: gr64, preferred-register: '' }
-# NO_AVX512F: - { id: 1, class: vr128, preferred-register: '' }
-# AVX512ALL: - { id: 1, class: vr128x, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: vecr }
-# ALL: %0 = COPY %rdi
-# SSE: %1 = MOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
-# AVX: %1 = VMOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
-# AVX512F: %1 = VMOVAPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1)
-# AVX512VL: %1 = VMOVAPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
+# ALL: %0:gr64 = COPY %rdi
+# SSE: %1:vr128 = MOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
+# AVX: %1:vr128 = VMOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
+# AVX512F: %1:vr128x = VMOVAPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1)
+# AVX512VL: %1:vr128x = VMOVAPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
# ALL: %xmm0 = COPY %1
body: |
bb.1 (%ir-block.0):
@@ -88,13 +82,11 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
-# NO_AVX512F: - { id: 0, class: vr128, preferred-register: '' }
-# AVX512ALL: - { id: 0, class: vr128x, preferred-register: '' }
-# ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: vecr }
- { id: 1, class: gpr }
-# ALL: %0 = COPY %xmm0
-# ALL: %1 = COPY %rdi
+# NO_AVX512F: %0:vr128 = COPY %xmm0
+# AVX512ALL: %0:vr128x = COPY %xmm0
+# ALL: %1:gr64 = COPY %rdi
# SSE: MOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
# AVX: VMOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
# AVX512F: VMOVAPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
@@ -118,13 +110,11 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
-# NO_AVX512F: - { id: 0, class: vr128, preferred-register: '' }
-# AVX512ALL: - { id: 0, class: vr128x, preferred-register: '' }
-# ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: vecr }
- { id: 1, class: gpr }
-# ALL: %0 = COPY %xmm0
-# ALL: %1 = COPY %rdi
+# NO_AVX512F: %0:vr128 = COPY %xmm0
+# AVX512ALL: %0:vr128x = COPY %xmm0
+# ALL: %1:gr64 = COPY %rdi
# SSE: MOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
# AVX: VMOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
# AVX512F: VMOVUPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v256.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v256.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v256.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v256.mir Tue Oct 24 11:04:54 2017
@@ -42,18 +42,18 @@ regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: vecr }
-# NO_AVX512F: %0 = COPY %rdi
-# NO_AVX512F-NEXT: %1 = VMOVUPSYrm %0, 1, _, 0, _ :: (load 32 from %ir.p1, align 1)
+# NO_AVX512F: %0:gr64 = COPY %rdi
+# NO_AVX512F-NEXT: %1:vr256 = VMOVUPSYrm %0, 1, _, 0, _ :: (load 32 from %ir.p1, align 1)
# NO_AVX512F-NEXT: %ymm0 = COPY %1
# NO_AVX512F-NEXT: RET 0, implicit %ymm0
#
-# AVX512F: %0 = COPY %rdi
-# AVX512F-NEXT: %1 = VMOVUPSZ256rm_NOVLX %0, 1, _, 0, _ :: (load 32 from %ir.p1, align 1)
+# AVX512F: %0:gr64 = COPY %rdi
+# AVX512F-NEXT: %1:vr256x = VMOVUPSZ256rm_NOVLX %0, 1, _, 0, _ :: (load 32 from %ir.p1, align 1)
# AVX512F-NEXT: %ymm0 = COPY %1
# AVX512F-NEXT: RET 0, implicit %ymm0
#
-# AVX512VL: %0 = COPY %rdi
-# AVX512VL-NEXT: %1 = VMOVUPSZ256rm %0, 1, _, 0, _ :: (load 32 from %ir.p1, align 1)
+# AVX512VL: %0:gr64 = COPY %rdi
+# AVX512VL-NEXT: %1:vr256x = VMOVUPSZ256rm %0, 1, _, 0, _ :: (load 32 from %ir.p1, align 1)
# AVX512VL-NEXT: %ymm0 = COPY %1
# AVX512VL-NEXT: RET 0, implicit %ymm0
body: |
@@ -72,28 +72,21 @@ name: test_load_v8i32_align
alignment: 4
legalized: true
regBankSelected: true
-# NO_AVX512F: registers:
-# NO_AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 1, class: vr256, preferred-register: '' }
-#
-# AVX512ALL: registers:
-# AVX512ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: vecr }
-# NO_AVX512F: %0 = COPY %rdi
-# NO_AVX512F-NEXT: %1 = VMOVAPSYrm %0, 1, _, 0, _ :: (load 32 from %ir.p1)
+# NO_AVX512F: %0:gr64 = COPY %rdi
+# NO_AVX512F-NEXT: %1:vr256 = VMOVAPSYrm %0, 1, _, 0, _ :: (load 32 from %ir.p1)
# NO_AVX512F-NEXT: %ymm0 = COPY %1
# NO_AVX512F-NEXT: RET 0, implicit %ymm0
#
-# AVX512F: %0 = COPY %rdi
-# AVX512F-NEXT: %1 = VMOVAPSZ256rm_NOVLX %0, 1, _, 0, _ :: (load 32 from %ir.p1)
+# AVX512F: %0:gr64 = COPY %rdi
+# AVX512F-NEXT: %1:vr256x = VMOVAPSZ256rm_NOVLX %0, 1, _, 0, _ :: (load 32 from %ir.p1)
# AVX512F-NEXT: %ymm0 = COPY %1
# AVX512F-NEXT: RET 0, implicit %ymm0
#
-# AVX512VL: %0 = COPY %rdi
-# AVX512VL-NEXT: %1 = VMOVAPSZ256rm %0, 1, _, 0, _ :: (load 32 from %ir.p1)
+# AVX512VL: %0:gr64 = COPY %rdi
+# AVX512VL-NEXT: %1:vr256x = VMOVAPSZ256rm %0, 1, _, 0, _ :: (load 32 from %ir.p1)
# AVX512VL-NEXT: %ymm0 = COPY %1
# AVX512VL-NEXT: RET 0, implicit %ymm0
body: |
@@ -122,18 +115,18 @@ regBankSelected: true
registers:
- { id: 0, class: vecr }
- { id: 1, class: gpr }
-# NO_AVX512F: %0 = COPY %ymm0
-# NO_AVX512F-NEXT: %1 = COPY %rdi
+# NO_AVX512F: %0:vr256 = COPY %ymm0
+# NO_AVX512F-NEXT: %1:gr64 = COPY %rdi
# NO_AVX512F-NEXT: VMOVUPSYmr %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1, align 1)
# NO_AVX512F-NEXT: RET 0
#
-# AVX512F: %0 = COPY %ymm0
-# AVX512F-NEXT: %1 = COPY %rdi
+# AVX512F: %0:vr256x = COPY %ymm0
+# AVX512F-NEXT: %1:gr64 = COPY %rdi
# AVX512F-NEXT: VMOVUPSZ256mr_NOVLX %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1, align 1)
# AVX512F-NEXT: RET 0
#
-# AVX512VL: %0 = COPY %ymm0
-# AVX512VL-NEXT: %1 = COPY %rdi
+# AVX512VL: %0:vr256x = COPY %ymm0
+# AVX512VL-NEXT: %1:gr64 = COPY %rdi
# AVX512VL-NEXT: VMOVUPSZ256mr %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1, align 1)
# AVX512VL-NEXT: RET 0
body: |
@@ -162,18 +155,18 @@ regBankSelected: true
registers:
- { id: 0, class: vecr }
- { id: 1, class: gpr }
-# NO_AVX512F: %0 = COPY %ymm0
-# NO_AVX512F-NEXT: %1 = COPY %rdi
+# NO_AVX512F: %0:vr256 = COPY %ymm0
+# NO_AVX512F-NEXT: %1:gr64 = COPY %rdi
# NO_AVX512F-NEXT: VMOVAPSYmr %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1)
# NO_AVX512F-NEXT: RET 0
#
-# AVX512F: %0 = COPY %ymm0
-# AVX512F-NEXT: %1 = COPY %rdi
+# AVX512F: %0:vr256x = COPY %ymm0
+# AVX512F-NEXT: %1:gr64 = COPY %rdi
# AVX512F-NEXT: VMOVAPSZ256mr_NOVLX %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1)
# AVX512F-NEXT: RET 0
#
-# AVX512VL: %0 = COPY %ymm0
-# AVX512VL-NEXT: %1 = COPY %rdi
+# AVX512VL: %0:vr256x = COPY %ymm0
+# AVX512VL-NEXT: %1:gr64 = COPY %rdi
# AVX512VL-NEXT: VMOVAPSZ256mr %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1)
# AVX512VL-NEXT: RET 0
body: |
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v512.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v512.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v512.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v512.mir Tue Oct 24 11:04:54 2017
@@ -35,11 +35,8 @@ body: |
liveins: %rdi
; AVX512F-LABEL: name: test_load_v16i32_noalign
- ; AVX512F: registers:
- ; AVX512F-NEXT: id: 0, class: gr64
- ; AVX512F-NEXT: id: 1, class: vr512
- ; AVX512F: [[COPY:%[0-9]+]] = COPY %rdi
- ; AVX512F: [[VMOVUPSZrm:%[0-9]+]] = VMOVUPSZrm [[COPY]], 1, _, 0, _ :: (load 64 from %ir.p1, align 1)
+ ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+ ; AVX512F: [[VMOVUPSZrm:%[0-9]+]]:vr512 = VMOVUPSZrm [[COPY]], 1, _, 0, _ :: (load 64 from %ir.p1, align 1)
; AVX512F: %zmm0 = COPY [[VMOVUPSZrm]]
; AVX512F: RET 0, implicit %zmm0
%0(p0) = COPY %rdi
@@ -61,11 +58,8 @@ body: |
liveins: %rdi
; AVX512F-LABEL: name: test_load_v16i32_align
- ; AVX512F: registers:
- ; AVX512F-NEXT: id: 0, class: gr64
- ; AVX512F-NEXT: id: 1, class: vr512
- ; AVX512F: [[COPY:%[0-9]+]] = COPY %rdi
- ; AVX512F: [[VMOVUPSZrm:%[0-9]+]] = VMOVUPSZrm [[COPY]], 1, _, 0, _ :: (load 64 from %ir.p1, align 32)
+ ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+ ; AVX512F: [[VMOVUPSZrm:%[0-9]+]]:vr512 = VMOVUPSZrm [[COPY]], 1, _, 0, _ :: (load 64 from %ir.p1, align 32)
; AVX512F: %zmm0 = COPY [[VMOVUPSZrm]]
; AVX512F: RET 0, implicit %zmm0
%0(p0) = COPY %rdi
@@ -87,11 +81,8 @@ body: |
liveins: %rdi, %zmm0
; AVX512F-LABEL: name: test_store_v16i32_noalign
- ; AVX512F: registers:
- ; AVX512F-NEXT: id: 0, class: vr512
- ; AVX512F-NEXT: id: 1, class: gr64
- ; AVX512F: [[COPY:%[0-9]+]] = COPY %zmm0
- ; AVX512F: [[COPY1:%[0-9]+]] = COPY %rdi
+ ; AVX512F: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+ ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY %rdi
; AVX512F: VMOVUPSZmr [[COPY1]], 1, _, 0, _, [[COPY]] :: (store 64 into %ir.p1, align 1)
; AVX512F: RET 0
%0(<16 x s32>) = COPY %zmm0
@@ -113,11 +104,8 @@ body: |
liveins: %rdi, %zmm0
; AVX512F-LABEL: name: test_store_v16i32_align
- ; AVX512F: registers:
- ; AVX512F-NEXT: id: 0, class: vr512
- ; AVX512F-NEXT: id: 1, class: gr64
- ; AVX512F: [[COPY:%[0-9]+]] = COPY %zmm0
- ; AVX512F: [[COPY1:%[0-9]+]] = COPY %rdi
+ ; AVX512F: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+ ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY %rdi
; AVX512F: VMOVUPSZmr [[COPY1]], 1, _, 0, _, [[COPY]] :: (store 64 into %ir.p1, align 32)
; AVX512F: RET 0
%0(<16 x s32>) = COPY %zmm0
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir Tue Oct 24 11:04:54 2017
@@ -21,27 +21,17 @@ body: |
bb.1 (%ir-block.0):
; AVX-LABEL: name: test_merge
- ; AVX: registers:
- ; AVX-NEXT: id: 0, class: vr128
- ; AVX-NEXT: id: 1, class: vr256
- ; AVX-NEXT: id: 2, class: vr256
- ; AVX-NEXT: id: 3, class: vr256
- ; AVX: [[DEF:%[0-9]+]] = IMPLICIT_DEF
- ; AVX: undef %2.sub_xmm = COPY [[DEF]]
- ; AVX: [[VINSERTF128rr:%[0-9]+]] = VINSERTF128rr %2, [[DEF]], 1
- ; AVX: [[COPY:%[0-9]+]] = COPY [[VINSERTF128rr]]
+ ; AVX: [[DEF:%[0-9]+]]:vr128 = IMPLICIT_DEF
+ ; AVX: undef %2.sub_xmm:vr256 = COPY [[DEF]]
+ ; AVX: [[VINSERTF128rr:%[0-9]+]]:vr256 = VINSERTF128rr %2, [[DEF]], 1
+ ; AVX: [[COPY:%[0-9]+]]:vr256 = COPY [[VINSERTF128rr]]
; AVX: %ymm0 = COPY [[COPY]]
; AVX: RET 0, implicit %ymm0
; AVX512VL-LABEL: name: test_merge
- ; AVX512VL: registers:
- ; AVX512VL-NEXT: id: 0, class: vr128x
- ; AVX512VL-NEXT: id: 1, class: vr256x
- ; AVX512VL-NEXT: id: 2, class: vr256x
- ; AVX512VL-NEXT: id: 3, class: vr256x
- ; AVX512VL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
- ; AVX512VL: undef %2.sub_xmm = COPY [[DEF]]
- ; AVX512VL: [[VINSERTF32x4Z256rr:%[0-9]+]] = VINSERTF32x4Z256rr %2, [[DEF]], 1
- ; AVX512VL: [[COPY:%[0-9]+]] = COPY [[VINSERTF32x4Z256rr]]
+ ; AVX512VL: [[DEF:%[0-9]+]]:vr128x = IMPLICIT_DEF
+ ; AVX512VL: undef %2.sub_xmm:vr256x = COPY [[DEF]]
+ ; AVX512VL: [[VINSERTF32x4Z256rr:%[0-9]+]]:vr256x = VINSERTF32x4Z256rr %2, [[DEF]], 1
+ ; AVX512VL: [[COPY:%[0-9]+]]:vr256x = COPY [[VINSERTF32x4Z256rr]]
; AVX512VL: %ymm0 = COPY [[COPY]]
; AVX512VL: RET 0, implicit %ymm0
%0(<4 x s32>) = IMPLICIT_DEF
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir Tue Oct 24 11:04:54 2017
@@ -22,19 +22,12 @@ body: |
bb.1 (%ir-block.0):
; ALL-LABEL: name: test_merge_v128
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: vr128x
- ; ALL-NEXT: id: 1, class: vr512
- ; ALL-NEXT: id: 2, class: vr512
- ; ALL-NEXT: id: 3, class: vr512
- ; ALL-NEXT: id: 4, class: vr512
- ; ALL-NEXT: id: 5, class: vr512
- ; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
- ; ALL: undef %2.sub_xmm = COPY [[DEF]]
- ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]] = VINSERTF32x4Zrr %2, [[DEF]], 1
- ; ALL: [[VINSERTF32x4Zrr1:%[0-9]+]] = VINSERTF32x4Zrr [[VINSERTF32x4Zrr]], [[DEF]], 2
- ; ALL: [[VINSERTF32x4Zrr2:%[0-9]+]] = VINSERTF32x4Zrr [[VINSERTF32x4Zrr1]], [[DEF]], 3
- ; ALL: [[COPY:%[0-9]+]] = COPY [[VINSERTF32x4Zrr2]]
+ ; ALL: [[DEF:%[0-9]+]]:vr128x = IMPLICIT_DEF
+ ; ALL: undef %2.sub_xmm:vr512 = COPY [[DEF]]
+ ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]]:vr512 = VINSERTF32x4Zrr %2, [[DEF]], 1
+ ; ALL: [[VINSERTF32x4Zrr1:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[VINSERTF32x4Zrr]], [[DEF]], 2
+ ; ALL: [[VINSERTF32x4Zrr2:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[VINSERTF32x4Zrr1]], [[DEF]], 3
+ ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY [[VINSERTF32x4Zrr2]]
; ALL: %zmm0 = COPY [[COPY]]
; ALL: RET 0, implicit %zmm0
%0(<4 x s32>) = IMPLICIT_DEF
@@ -55,15 +48,10 @@ body: |
bb.1 (%ir-block.0):
; ALL-LABEL: name: test_merge_v256
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: vr256x
- ; ALL-NEXT: id: 1, class: vr512
- ; ALL-NEXT: id: 2, class: vr512
- ; ALL-NEXT: id: 3, class: vr512
- ; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
- ; ALL: undef %2.sub_ymm = COPY [[DEF]]
- ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]] = VINSERTF64x4Zrr %2, [[DEF]], 1
- ; ALL: [[COPY:%[0-9]+]] = COPY [[VINSERTF64x4Zrr]]
+ ; ALL: [[DEF:%[0-9]+]]:vr256x = IMPLICIT_DEF
+ ; ALL: undef %2.sub_ymm:vr512 = COPY [[DEF]]
+ ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]]:vr512 = VINSERTF64x4Zrr %2, [[DEF]], 1
+ ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY [[VINSERTF64x4Zrr]]
; ALL: %zmm0 = COPY [[COPY]]
; ALL: RET 0, implicit %zmm0
%0(<8 x s32>) = IMPLICIT_DEF
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir Tue Oct 24 11:04:54 2017
@@ -32,13 +32,9 @@ body: |
liveins: %edi, %esi
; ALL-LABEL: name: test_mul_i16
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr16
- ; ALL-NEXT: id: 1, class: gr16
- ; ALL-NEXT: id: 2, class: gr16
- ; ALL: [[COPY:%[0-9]+]] = COPY %di
- ; ALL: [[COPY1:%[0-9]+]] = COPY %si
- ; ALL: [[IMUL16rr:%[0-9]+]] = IMUL16rr [[COPY]], [[COPY1]], implicit-def %eflags
+ ; ALL: [[COPY:%[0-9]+]]:gr16 = COPY %di
+ ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY %si
+ ; ALL: [[IMUL16rr:%[0-9]+]]:gr16 = IMUL16rr [[COPY]], [[COPY1]], implicit-def %eflags
; ALL: %ax = COPY [[IMUL16rr]]
; ALL: RET 0, implicit %ax
%0(s16) = COPY %di
@@ -62,13 +58,9 @@ body: |
liveins: %edi, %esi
; ALL-LABEL: name: test_mul_i32
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr32
- ; ALL-NEXT: id: 1, class: gr32
- ; ALL-NEXT: id: 2, class: gr32
- ; ALL: [[COPY:%[0-9]+]] = COPY %edi
- ; ALL: [[COPY1:%[0-9]+]] = COPY %esi
- ; ALL: [[IMUL32rr:%[0-9]+]] = IMUL32rr [[COPY]], [[COPY1]], implicit-def %eflags
+ ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+ ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
+ ; ALL: [[IMUL32rr:%[0-9]+]]:gr32 = IMUL32rr [[COPY]], [[COPY1]], implicit-def %eflags
; ALL: %eax = COPY [[IMUL32rr]]
; ALL: RET 0, implicit %eax
%0(s32) = COPY %edi
@@ -92,13 +84,9 @@ body: |
liveins: %rdi, %rsi
; ALL-LABEL: name: test_mul_i64
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr64
- ; ALL-NEXT: id: 1, class: gr64
- ; ALL-NEXT: id: 2, class: gr64
- ; ALL: [[COPY:%[0-9]+]] = COPY %rdi
- ; ALL: [[COPY1:%[0-9]+]] = COPY %rsi
- ; ALL: [[IMUL64rr:%[0-9]+]] = IMUL64rr [[COPY]], [[COPY1]], implicit-def %eflags
+ ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+ ; ALL: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi
+ ; ALL: [[IMUL64rr:%[0-9]+]]:gr64 = IMUL64rr [[COPY]], [[COPY1]], implicit-def %eflags
; ALL: %rax = COPY [[IMUL64rr]]
; ALL: RET 0, implicit %rax
%0(s64) = COPY %rdi
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-mul-vec.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-mul-vec.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-mul-vec.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-mul-vec.mir Tue Oct 24 11:04:54 2017
@@ -103,13 +103,9 @@ body: |
liveins: %xmm0, %xmm1
; CHECK-LABEL: name: test_mul_v8i16
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: vr128
- ; CHECK-NEXT: id: 1, class: vr128
- ; CHECK-NEXT: id: 2, class: vr128
- ; CHECK: [[COPY:%[0-9]+]] = COPY %xmm0
- ; CHECK: [[COPY1:%[0-9]+]] = COPY %xmm1
- ; CHECK: [[PMULLWrr:%[0-9]+]] = PMULLWrr [[COPY]], [[COPY1]]
+ ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0
+ ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %xmm1
+ ; CHECK: [[PMULLWrr:%[0-9]+]]:vr128 = PMULLWrr [[COPY]], [[COPY1]]
; CHECK: %xmm0 = COPY [[PMULLWrr]]
; CHECK: RET 0, implicit %xmm0
%0(<8 x s16>) = COPY %xmm0
@@ -133,13 +129,9 @@ body: |
liveins: %xmm0, %xmm1
; CHECK-LABEL: name: test_mul_v8i16_avx
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: vr128
- ; CHECK-NEXT: id: 1, class: vr128
- ; CHECK-NEXT: id: 2, class: vr128
- ; CHECK: [[COPY:%[0-9]+]] = COPY %xmm0
- ; CHECK: [[COPY1:%[0-9]+]] = COPY %xmm1
- ; CHECK: [[VPMULLWrr:%[0-9]+]] = VPMULLWrr [[COPY]], [[COPY1]]
+ ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0
+ ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %xmm1
+ ; CHECK: [[VPMULLWrr:%[0-9]+]]:vr128 = VPMULLWrr [[COPY]], [[COPY1]]
; CHECK: %xmm0 = COPY [[VPMULLWrr]]
; CHECK: RET 0, implicit %xmm0
%0(<8 x s16>) = COPY %xmm0
@@ -163,13 +155,9 @@ body: |
liveins: %xmm0, %xmm1
; CHECK-LABEL: name: test_mul_v8i16_avx512bwvl
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: vr128x
- ; CHECK-NEXT: id: 1, class: vr128x
- ; CHECK-NEXT: id: 2, class: vr128x
- ; CHECK: [[COPY:%[0-9]+]] = COPY %xmm0
- ; CHECK: [[COPY1:%[0-9]+]] = COPY %xmm1
- ; CHECK: [[VPMULLWZ128rr:%[0-9]+]] = VPMULLWZ128rr [[COPY]], [[COPY1]]
+ ; CHECK: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0
+ ; CHECK: [[COPY1:%[0-9]+]]:vr128x = COPY %xmm1
+ ; CHECK: [[VPMULLWZ128rr:%[0-9]+]]:vr128x = VPMULLWZ128rr [[COPY]], [[COPY1]]
; CHECK: %xmm0 = COPY [[VPMULLWZ128rr]]
; CHECK: RET 0, implicit %xmm0
%0(<8 x s16>) = COPY %xmm0
@@ -193,13 +181,9 @@ body: |
liveins: %xmm0, %xmm1
; CHECK-LABEL: name: test_mul_v4i32
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: vr128
- ; CHECK-NEXT: id: 1, class: vr128
- ; CHECK-NEXT: id: 2, class: vr128
- ; CHECK: [[COPY:%[0-9]+]] = COPY %xmm0
- ; CHECK: [[COPY1:%[0-9]+]] = COPY %xmm1
- ; CHECK: [[PMULLDrr:%[0-9]+]] = PMULLDrr [[COPY]], [[COPY1]]
+ ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0
+ ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %xmm1
+ ; CHECK: [[PMULLDrr:%[0-9]+]]:vr128 = PMULLDrr [[COPY]], [[COPY1]]
; CHECK: %xmm0 = COPY [[PMULLDrr]]
; CHECK: RET 0, implicit %xmm0
%0(<4 x s32>) = COPY %xmm0
@@ -223,13 +207,9 @@ body: |
liveins: %xmm0, %xmm1
; CHECK-LABEL: name: test_mul_v4i32_avx
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: vr128
- ; CHECK-NEXT: id: 1, class: vr128
- ; CHECK-NEXT: id: 2, class: vr128
- ; CHECK: [[COPY:%[0-9]+]] = COPY %xmm0
- ; CHECK: [[COPY1:%[0-9]+]] = COPY %xmm1
- ; CHECK: [[VPMULLDrr:%[0-9]+]] = VPMULLDrr [[COPY]], [[COPY1]]
+ ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0
+ ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %xmm1
+ ; CHECK: [[VPMULLDrr:%[0-9]+]]:vr128 = VPMULLDrr [[COPY]], [[COPY1]]
; CHECK: %xmm0 = COPY [[VPMULLDrr]]
; CHECK: RET 0, implicit %xmm0
%0(<4 x s32>) = COPY %xmm0
@@ -253,13 +233,9 @@ body: |
liveins: %xmm0, %xmm1
; CHECK-LABEL: name: test_mul_v4i32_avx512vl
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: vr128x
- ; CHECK-NEXT: id: 1, class: vr128x
- ; CHECK-NEXT: id: 2, class: vr128x
- ; CHECK: [[COPY:%[0-9]+]] = COPY %xmm0
- ; CHECK: [[COPY1:%[0-9]+]] = COPY %xmm1
- ; CHECK: [[VPMULLDZ128rr:%[0-9]+]] = VPMULLDZ128rr [[COPY]], [[COPY1]]
+ ; CHECK: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0
+ ; CHECK: [[COPY1:%[0-9]+]]:vr128x = COPY %xmm1
+ ; CHECK: [[VPMULLDZ128rr:%[0-9]+]]:vr128x = VPMULLDZ128rr [[COPY]], [[COPY1]]
; CHECK: %xmm0 = COPY [[VPMULLDZ128rr]]
; CHECK: RET 0, implicit %xmm0
%0(<4 x s32>) = COPY %xmm0
@@ -283,13 +259,9 @@ body: |
liveins: %xmm0, %xmm1
; CHECK-LABEL: name: test_mul_v2i64
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: vr128x
- ; CHECK-NEXT: id: 1, class: vr128x
- ; CHECK-NEXT: id: 2, class: vr128x
- ; CHECK: [[COPY:%[0-9]+]] = COPY %xmm0
- ; CHECK: [[COPY1:%[0-9]+]] = COPY %xmm1
- ; CHECK: [[VPMULLQZ128rr:%[0-9]+]] = VPMULLQZ128rr [[COPY]], [[COPY1]]
+ ; CHECK: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0
+ ; CHECK: [[COPY1:%[0-9]+]]:vr128x = COPY %xmm1
+ ; CHECK: [[VPMULLQZ128rr:%[0-9]+]]:vr128x = VPMULLQZ128rr [[COPY]], [[COPY1]]
; CHECK: %xmm0 = COPY [[VPMULLQZ128rr]]
; CHECK: RET 0, implicit %xmm0
%0(<2 x s64>) = COPY %xmm0
@@ -313,13 +285,9 @@ body: |
liveins: %ymm0, %ymm1
; CHECK-LABEL: name: test_mul_v16i16
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: vr256
- ; CHECK-NEXT: id: 1, class: vr256
- ; CHECK-NEXT: id: 2, class: vr256
- ; CHECK: [[COPY:%[0-9]+]] = COPY %ymm0
- ; CHECK: [[COPY1:%[0-9]+]] = COPY %ymm1
- ; CHECK: [[VPMULLWYrr:%[0-9]+]] = VPMULLWYrr [[COPY]], [[COPY1]]
+ ; CHECK: [[COPY:%[0-9]+]]:vr256 = COPY %ymm0
+ ; CHECK: [[COPY1:%[0-9]+]]:vr256 = COPY %ymm1
+ ; CHECK: [[VPMULLWYrr:%[0-9]+]]:vr256 = VPMULLWYrr [[COPY]], [[COPY1]]
; CHECK: %ymm0 = COPY [[VPMULLWYrr]]
; CHECK: RET 0, implicit %ymm0
%0(<16 x s16>) = COPY %ymm0
@@ -343,13 +311,9 @@ body: |
liveins: %ymm0, %ymm1
; CHECK-LABEL: name: test_mul_v16i16_avx512bwvl
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: vr256x
- ; CHECK-NEXT: id: 1, class: vr256x
- ; CHECK-NEXT: id: 2, class: vr256x
- ; CHECK: [[COPY:%[0-9]+]] = COPY %ymm0
- ; CHECK: [[COPY1:%[0-9]+]] = COPY %ymm1
- ; CHECK: [[VPMULLWZ256rr:%[0-9]+]] = VPMULLWZ256rr [[COPY]], [[COPY1]]
+ ; CHECK: [[COPY:%[0-9]+]]:vr256x = COPY %ymm0
+ ; CHECK: [[COPY1:%[0-9]+]]:vr256x = COPY %ymm1
+ ; CHECK: [[VPMULLWZ256rr:%[0-9]+]]:vr256x = VPMULLWZ256rr [[COPY]], [[COPY1]]
; CHECK: %ymm0 = COPY [[VPMULLWZ256rr]]
; CHECK: RET 0, implicit %ymm0
%0(<16 x s16>) = COPY %ymm0
@@ -373,13 +337,9 @@ body: |
liveins: %ymm0, %ymm1
; CHECK-LABEL: name: test_mul_v8i32
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: vr256
- ; CHECK-NEXT: id: 1, class: vr256
- ; CHECK-NEXT: id: 2, class: vr256
- ; CHECK: [[COPY:%[0-9]+]] = COPY %ymm0
- ; CHECK: [[COPY1:%[0-9]+]] = COPY %ymm1
- ; CHECK: [[VPMULLDYrr:%[0-9]+]] = VPMULLDYrr [[COPY]], [[COPY1]]
+ ; CHECK: [[COPY:%[0-9]+]]:vr256 = COPY %ymm0
+ ; CHECK: [[COPY1:%[0-9]+]]:vr256 = COPY %ymm1
+ ; CHECK: [[VPMULLDYrr:%[0-9]+]]:vr256 = VPMULLDYrr [[COPY]], [[COPY1]]
; CHECK: %ymm0 = COPY [[VPMULLDYrr]]
; CHECK: RET 0, implicit %ymm0
%0(<8 x s32>) = COPY %ymm0
@@ -403,13 +363,9 @@ body: |
liveins: %ymm0, %ymm1
; CHECK-LABEL: name: test_mul_v8i32_avx512vl
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: vr256x
- ; CHECK-NEXT: id: 1, class: vr256x
- ; CHECK-NEXT: id: 2, class: vr256x
- ; CHECK: [[COPY:%[0-9]+]] = COPY %ymm0
- ; CHECK: [[COPY1:%[0-9]+]] = COPY %ymm1
- ; CHECK: [[VPMULLDZ256rr:%[0-9]+]] = VPMULLDZ256rr [[COPY]], [[COPY1]]
+ ; CHECK: [[COPY:%[0-9]+]]:vr256x = COPY %ymm0
+ ; CHECK: [[COPY1:%[0-9]+]]:vr256x = COPY %ymm1
+ ; CHECK: [[VPMULLDZ256rr:%[0-9]+]]:vr256x = VPMULLDZ256rr [[COPY]], [[COPY1]]
; CHECK: %ymm0 = COPY [[VPMULLDZ256rr]]
; CHECK: RET 0, implicit %ymm0
%0(<8 x s32>) = COPY %ymm0
@@ -433,13 +389,9 @@ body: |
liveins: %ymm0, %ymm1
; CHECK-LABEL: name: test_mul_v4i64
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: vr256x
- ; CHECK-NEXT: id: 1, class: vr256x
- ; CHECK-NEXT: id: 2, class: vr256x
- ; CHECK: [[COPY:%[0-9]+]] = COPY %ymm0
- ; CHECK: [[COPY1:%[0-9]+]] = COPY %ymm1
- ; CHECK: [[VPMULLQZ256rr:%[0-9]+]] = VPMULLQZ256rr [[COPY]], [[COPY1]]
+ ; CHECK: [[COPY:%[0-9]+]]:vr256x = COPY %ymm0
+ ; CHECK: [[COPY1:%[0-9]+]]:vr256x = COPY %ymm1
+ ; CHECK: [[VPMULLQZ256rr:%[0-9]+]]:vr256x = VPMULLQZ256rr [[COPY]], [[COPY1]]
; CHECK: %ymm0 = COPY [[VPMULLQZ256rr]]
; CHECK: RET 0, implicit %ymm0
%0(<4 x s64>) = COPY %ymm0
@@ -463,13 +415,9 @@ body: |
liveins: %zmm0, %zmm1
; CHECK-LABEL: name: test_mul_v32i16
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: vr512
- ; CHECK-NEXT: id: 1, class: vr512
- ; CHECK-NEXT: id: 2, class: vr512
- ; CHECK: [[COPY:%[0-9]+]] = COPY %zmm0
- ; CHECK: [[COPY1:%[0-9]+]] = COPY %zmm1
- ; CHECK: [[VPMULLWZrr:%[0-9]+]] = VPMULLWZrr [[COPY]], [[COPY1]]
+ ; CHECK: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+ ; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1
+ ; CHECK: [[VPMULLWZrr:%[0-9]+]]:vr512 = VPMULLWZrr [[COPY]], [[COPY1]]
; CHECK: %zmm0 = COPY [[VPMULLWZrr]]
; CHECK: RET 0, implicit %zmm0
%0(<32 x s16>) = COPY %zmm0
@@ -493,13 +441,9 @@ body: |
liveins: %zmm0, %zmm1
; CHECK-LABEL: name: test_mul_v16i32
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: vr512
- ; CHECK-NEXT: id: 1, class: vr512
- ; CHECK-NEXT: id: 2, class: vr512
- ; CHECK: [[COPY:%[0-9]+]] = COPY %zmm0
- ; CHECK: [[COPY1:%[0-9]+]] = COPY %zmm1
- ; CHECK: [[VPMULLDZrr:%[0-9]+]] = VPMULLDZrr [[COPY]], [[COPY1]]
+ ; CHECK: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+ ; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1
+ ; CHECK: [[VPMULLDZrr:%[0-9]+]]:vr512 = VPMULLDZrr [[COPY]], [[COPY1]]
; CHECK: %zmm0 = COPY [[VPMULLDZrr]]
; CHECK: RET 0, implicit %zmm0
%0(<16 x s32>) = COPY %zmm0
@@ -523,13 +467,9 @@ body: |
liveins: %zmm0, %zmm1
; CHECK-LABEL: name: test_mul_v8i64
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: vr512
- ; CHECK-NEXT: id: 1, class: vr512
- ; CHECK-NEXT: id: 2, class: vr512
- ; CHECK: [[COPY:%[0-9]+]] = COPY %zmm0
- ; CHECK: [[COPY1:%[0-9]+]] = COPY %zmm1
- ; CHECK: [[VPMULLQZrr:%[0-9]+]] = VPMULLQZrr [[COPY]], [[COPY1]]
+ ; CHECK: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+ ; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1
+ ; CHECK: [[VPMULLQZrr:%[0-9]+]]:vr512 = VPMULLQZrr [[COPY]], [[COPY1]]
; CHECK: %zmm0 = COPY [[VPMULLQZrr]]
; CHECK: RET 0, implicit %zmm0
%0(<8 x s64>) = COPY %zmm0
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-or-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-or-scalar.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-or-scalar.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-or-scalar.mir Tue Oct 24 11:04:54 2017
@@ -41,13 +41,9 @@ body: |
liveins: %edi, %esi
; ALL-LABEL: name: test_or_i8
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr8
- ; ALL-NEXT: id: 1, class: gr8
- ; ALL-NEXT: id: 2, class: gr8
- ; ALL: [[COPY:%[0-9]+]] = COPY %dil
- ; ALL: [[COPY1:%[0-9]+]] = COPY %sil
- ; ALL: [[OR8rr:%[0-9]+]] = OR8rr [[COPY]], [[COPY1]], implicit-def %eflags
+ ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY %dil
+ ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY %sil
+ ; ALL: [[OR8rr:%[0-9]+]]:gr8 = OR8rr [[COPY]], [[COPY1]], implicit-def %eflags
; ALL: %al = COPY [[OR8rr]]
; ALL: RET 0, implicit %al
%0(s8) = COPY %dil
@@ -75,13 +71,9 @@ body: |
liveins: %edi, %esi
; ALL-LABEL: name: test_or_i16
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr16
- ; ALL-NEXT: id: 1, class: gr16
- ; ALL-NEXT: id: 2, class: gr16
- ; ALL: [[COPY:%[0-9]+]] = COPY %di
- ; ALL: [[COPY1:%[0-9]+]] = COPY %si
- ; ALL: [[OR16rr:%[0-9]+]] = OR16rr [[COPY]], [[COPY1]], implicit-def %eflags
+ ; ALL: [[COPY:%[0-9]+]]:gr16 = COPY %di
+ ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY %si
+ ; ALL: [[OR16rr:%[0-9]+]]:gr16 = OR16rr [[COPY]], [[COPY1]], implicit-def %eflags
; ALL: %ax = COPY [[OR16rr]]
; ALL: RET 0, implicit %ax
%0(s16) = COPY %di
@@ -109,13 +101,9 @@ body: |
liveins: %edi, %esi
; ALL-LABEL: name: test_or_i32
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr32
- ; ALL-NEXT: id: 1, class: gr32
- ; ALL-NEXT: id: 2, class: gr32
- ; ALL: [[COPY:%[0-9]+]] = COPY %edi
- ; ALL: [[COPY1:%[0-9]+]] = COPY %esi
- ; ALL: [[OR32rr:%[0-9]+]] = OR32rr [[COPY]], [[COPY1]], implicit-def %eflags
+ ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+ ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
+ ; ALL: [[OR32rr:%[0-9]+]]:gr32 = OR32rr [[COPY]], [[COPY1]], implicit-def %eflags
; ALL: %eax = COPY [[OR32rr]]
; ALL: RET 0, implicit %eax
%0(s32) = COPY %edi
@@ -143,13 +131,9 @@ body: |
liveins: %rdi, %rsi
; ALL-LABEL: name: test_or_i64
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr64
- ; ALL-NEXT: id: 1, class: gr64
- ; ALL-NEXT: id: 2, class: gr64
- ; ALL: [[COPY:%[0-9]+]] = COPY %rdi
- ; ALL: [[COPY1:%[0-9]+]] = COPY %rsi
- ; ALL: [[OR64rr:%[0-9]+]] = OR64rr [[COPY]], [[COPY1]], implicit-def %eflags
+ ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+ ; ALL: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi
+ ; ALL: [[OR64rr:%[0-9]+]]:gr64 = OR64rr [[COPY]], [[COPY1]], implicit-def %eflags
; ALL: %rax = COPY [[OR64rr]]
; ALL: RET 0, implicit %rax
%0(s64) = COPY %rdi
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-phi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-phi.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-phi.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-phi.mir Tue Oct 24 11:04:54 2017
@@ -121,7 +121,7 @@ registers:
- { id: 4, class: gpr, preferred-register: '' }
- { id: 5, class: gpr, preferred-register: '' }
# ALL-LABEL: bb.3.cond.end:
-# ALL: %5 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
+# ALL: %5:gr8 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
# ALL-NEXT: %al = COPY %5
# ALL-NEXT: RET 0, implicit %al
body: |
@@ -174,7 +174,7 @@ registers:
- { id: 4, class: gpr, preferred-register: '' }
- { id: 5, class: gpr, preferred-register: '' }
# ALL-LABEL: bb.3.cond.end:
-# ALL: %5 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
+# ALL: %5:gr16 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
# ALL-NEXT: %ax = COPY %5
# ALL-NEXT: RET 0, implicit %ax
body: |
@@ -227,7 +227,7 @@ registers:
- { id: 4, class: gpr, preferred-register: '' }
- { id: 5, class: gpr, preferred-register: '' }
# ALL-LABEL: bb.3.cond.end:
-# ALL: %5 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
+# ALL: %5:gr32 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
# ALL-NEXT: %eax = COPY %5
# ALL-NEXT: RET 0, implicit %eax
body: |
@@ -280,7 +280,7 @@ registers:
- { id: 4, class: gpr, preferred-register: '' }
- { id: 5, class: gpr, preferred-register: '' }
# ALL-LABEL: bb.3.cond.end:
-# ALL: %5 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
+# ALL: %5:gr64 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
# ALL-NEXT: %rax = COPY %5
# ALL-NEXT: RET 0, implicit %rax
body: |
@@ -337,7 +337,7 @@ fixedStack:
stack:
constants:
# ALL-LABEL: bb.3.cond.end:
-# ALL: %5 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
+# ALL: %5:fr32 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
# ALL-NEXT: %xmm0 = COPY %5
# ALL-NEXT: RET 0, implicit %xmm0
body: |
@@ -390,7 +390,7 @@ registers:
- { id: 4, class: gpr, preferred-register: '' }
- { id: 5, class: vecr, preferred-register: '' }
# ALL-LABEL: bb.3.cond.end:
-# ALL: %5 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
+# ALL: %5:fr64 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
# ALL-NEXT: %xmm0 = COPY %5
# ALL-NEXT: RET 0, implicit %xmm0
body: |
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-sub-v128.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-sub-v128.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-sub-v128.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-sub-v128.mir Tue Oct 24 11:04:54 2017
@@ -31,31 +31,17 @@ name: test_sub_v16i8
alignment: 4
legalized: true
regBankSelected: true
-# NOVL: registers:
-# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
-# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
-# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
-#
-# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
-#
-# AVX512BWVL: registers:
-# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
-# SSE2: %2 = PSUBBrr %0, %1
+# SSE2: %2:vr128 = PSUBBrr %0, %1
#
-# AVX1: %2 = VPSUBBrr %0, %1
+# AVX1: %2:vr128 = VPSUBBrr %0, %1
#
-# AVX512VL: %2 = VPSUBBrr %0, %1
+# AVX512VL: %2:vr128 = VPSUBBrr %0, %1
#
-# AVX512BWVL: %2 = VPSUBBZ128rr %0, %1
+# AVX512BWVL: %2:vr128x = VPSUBBZ128rr %0, %1
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
@@ -73,31 +59,17 @@ name: test_sub_v8i16
alignment: 4
legalized: true
regBankSelected: true
-# NOVL: registers:
-# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
-# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
-# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
-#
-# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
-#
-# AVX512BWVL: registers:
-# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
-# SSE2: %2 = PSUBWrr %0, %1
+# SSE2: %2:vr128 = PSUBWrr %0, %1
#
-# AVX1: %2 = VPSUBWrr %0, %1
+# AVX1: %2:vr128 = VPSUBWrr %0, %1
#
-# AVX512VL: %2 = VPSUBWrr %0, %1
+# AVX512VL: %2:vr128 = VPSUBWrr %0, %1
#
-# AVX512BWVL: %2 = VPSUBWZ128rr %0, %1
+# AVX512BWVL: %2:vr128x = VPSUBWZ128rr %0, %1
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
@@ -115,31 +87,17 @@ name: test_sub_v4i32
alignment: 4
legalized: true
regBankSelected: true
-# NOVL: registers:
-# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
-# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
-# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
-#
-# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
-#
-# AVX512BWVL: registers:
-# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
-# SSE2: %2 = PSUBDrr %0, %1
+# SSE2: %2:vr128 = PSUBDrr %0, %1
#
-# AVX1: %2 = VPSUBDrr %0, %1
+# AVX1: %2:vr128 = VPSUBDrr %0, %1
#
-# AVX512VL: %2 = VPSUBDZ128rr %0, %1
+# AVX512VL: %2:vr128x = VPSUBDZ128rr %0, %1
#
-# AVX512BWVL: %2 = VPSUBDZ128rr %0, %1
+# AVX512BWVL: %2:vr128x = VPSUBDZ128rr %0, %1
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
@@ -157,31 +115,17 @@ name: test_sub_v2i64
alignment: 4
legalized: true
regBankSelected: true
-# NOVL: registers:
-# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
-# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
-# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
-#
-# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
-#
-# AVX512BWVL: registers:
-# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
-# SSE2: %2 = PSUBQrr %0, %1
+# SSE2: %2:vr128 = PSUBQrr %0, %1
#
-# AVX1: %2 = VPSUBQrr %0, %1
+# AVX1: %2:vr128 = VPSUBQrr %0, %1
#
-# AVX512VL: %2 = VPSUBQZ128rr %0, %1
+# AVX512VL: %2:vr128x = VPSUBQZ128rr %0, %1
#
-# AVX512BWVL: %2 = VPSUBQZ128rr %0, %1
+# AVX512BWVL: %2:vr128x = VPSUBQZ128rr %0, %1
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-sub-v256.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-sub-v256.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-sub-v256.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-sub-v256.mir Tue Oct 24 11:04:54 2017
@@ -29,29 +29,15 @@ name: test_sub_v32i8
alignment: 4
legalized: true
regBankSelected: true
-# AVX2: registers:
-# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
-# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
-# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
-#
-# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' }
-#
-# AVX512BWVL: registers:
-# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
-# AVX2: %2 = VPSUBBYrr %0, %1
+# AVX2: %2:vr256 = VPSUBBYrr %0, %1
#
-# AVX512VL: %2 = VPSUBBYrr %0, %1
+# AVX512VL: %2:vr256 = VPSUBBYrr %0, %1
#
-# AVX512BWVL: %2 = VPSUBBZ256rr %0, %1
+# AVX512BWVL: %2:vr256x = VPSUBBZ256rr %0, %1
body: |
bb.1 (%ir-block.0):
liveins: %ymm0, %ymm1
@@ -69,29 +55,15 @@ name: test_sub_v16i16
alignment: 4
legalized: true
regBankSelected: true
-# AVX2: registers:
-# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
-# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
-# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
-#
-# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' }
-#
-# AVX512BWVL: registers:
-# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
-# AVX2: %2 = VPSUBWYrr %0, %1
+# AVX2: %2:vr256 = VPSUBWYrr %0, %1
#
-# AVX512VL: %2 = VPSUBWYrr %0, %1
+# AVX512VL: %2:vr256 = VPSUBWYrr %0, %1
#
-# AVX512BWVL: %2 = VPSUBWZ256rr %0, %1
+# AVX512BWVL: %2:vr256x = VPSUBWZ256rr %0, %1
body: |
bb.1 (%ir-block.0):
liveins: %ymm0, %ymm1
@@ -109,29 +81,15 @@ name: test_sub_v8i32
alignment: 4
legalized: true
regBankSelected: true
-# AVX2: registers:
-# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
-# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
-# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
-#
-# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
-#
-# AVX512BWVL: registers:
-# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
-# AVX2: %2 = VPSUBDYrr %0, %1
+# AVX2: %2:vr256 = VPSUBDYrr %0, %1
#
-# AVX512VL: %2 = VPSUBDZ256rr %0, %1
+# AVX512VL: %2:vr256x = VPSUBDZ256rr %0, %1
#
-# AVX512BWVL: %2 = VPSUBDZ256rr %0, %1
+# AVX512BWVL: %2:vr256x = VPSUBDZ256rr %0, %1
body: |
bb.1 (%ir-block.0):
liveins: %ymm0, %ymm1
@@ -149,29 +107,15 @@ name: test_sub_v4i64
alignment: 4
legalized: true
regBankSelected: true
-# AVX2: registers:
-# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
-# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
-# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
-#
-# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
-#
-# AVX512BWVL: registers:
-# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
-# AVX2: %2 = VPSUBQYrr %0, %1
+# AVX2: %2:vr256 = VPSUBQYrr %0, %1
#
-# AVX512VL: %2 = VPSUBQZ256rr %0, %1
+# AVX512VL: %2:vr256x = VPSUBQZ256rr %0, %1
#
-# AVX512BWVL: %2 = VPSUBQZ256rr %0, %1
+# AVX512BWVL: %2:vr256x = VPSUBQZ256rr %0, %1
body: |
bb.1 (%ir-block.0):
liveins: %ymm0, %ymm1
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-sub-v512.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-sub-v512.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-sub-v512.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-sub-v512.mir Tue Oct 24 11:04:54 2017
@@ -39,13 +39,9 @@ body: |
liveins: %zmm0, %zmm1
; ALL-LABEL: name: test_sub_v64i8
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: vr512
- ; ALL-NEXT: id: 1, class: vr512
- ; ALL-NEXT: id: 2, class: vr512
- ; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
- ; ALL: [[COPY1:%[0-9]+]] = COPY %zmm1
- ; ALL: [[VPSUBBZrr:%[0-9]+]] = VPSUBBZrr [[COPY]], [[COPY1]]
+ ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+ ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1
+ ; ALL: [[VPSUBBZrr:%[0-9]+]]:vr512 = VPSUBBZrr [[COPY]], [[COPY1]]
; ALL: %zmm0 = COPY [[VPSUBBZrr]]
; ALL: RET 0, implicit %zmm0
%0(<64 x s8>) = COPY %zmm0
@@ -69,13 +65,9 @@ body: |
liveins: %zmm0, %zmm1
; ALL-LABEL: name: test_sub_v32i16
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: vr512
- ; ALL-NEXT: id: 1, class: vr512
- ; ALL-NEXT: id: 2, class: vr512
- ; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
- ; ALL: [[COPY1:%[0-9]+]] = COPY %zmm1
- ; ALL: [[VPSUBWZrr:%[0-9]+]] = VPSUBWZrr [[COPY]], [[COPY1]]
+ ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+ ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1
+ ; ALL: [[VPSUBWZrr:%[0-9]+]]:vr512 = VPSUBWZrr [[COPY]], [[COPY1]]
; ALL: %zmm0 = COPY [[VPSUBWZrr]]
; ALL: RET 0, implicit %zmm0
%0(<32 x s16>) = COPY %zmm0
@@ -99,13 +91,9 @@ body: |
liveins: %zmm0, %zmm1
; ALL-LABEL: name: test_sub_v16i32
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: vr512
- ; ALL-NEXT: id: 1, class: vr512
- ; ALL-NEXT: id: 2, class: vr512
- ; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
- ; ALL: [[COPY1:%[0-9]+]] = COPY %zmm1
- ; ALL: [[VPSUBDZrr:%[0-9]+]] = VPSUBDZrr [[COPY]], [[COPY1]]
+ ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+ ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1
+ ; ALL: [[VPSUBDZrr:%[0-9]+]]:vr512 = VPSUBDZrr [[COPY]], [[COPY1]]
; ALL: %zmm0 = COPY [[VPSUBDZrr]]
; ALL: RET 0, implicit %zmm0
%0(<16 x s32>) = COPY %zmm0
@@ -129,13 +117,9 @@ body: |
liveins: %zmm0, %zmm1
; ALL-LABEL: name: test_sub_v8i64
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: vr512
- ; ALL-NEXT: id: 1, class: vr512
- ; ALL-NEXT: id: 2, class: vr512
- ; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
- ; ALL: [[COPY1:%[0-9]+]] = COPY %zmm1
- ; ALL: [[VPSUBQZrr:%[0-9]+]] = VPSUBQZrr [[COPY]], [[COPY1]]
+ ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+ ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1
+ ; ALL: [[VPSUBQZrr:%[0-9]+]]:vr512 = VPSUBQZrr [[COPY]], [[COPY1]]
; ALL: %zmm0 = COPY [[VPSUBQZrr]]
; ALL: RET 0, implicit %zmm0
%0(<8 x s64>) = COPY %zmm0
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-sub.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-sub.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-sub.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-sub.mir Tue Oct 24 11:04:54 2017
@@ -29,17 +29,13 @@
name: test_sub_i64
legalized: true
regBankSelected: true
-# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
-# ALL: %0 = COPY %rdi
-# ALL-NEXT: %1 = COPY %rsi
-# ALL-NEXT: %2 = SUB64rr %0, %1
+# ALL: %0:gr64 = COPY %rdi
+# ALL-NEXT: %1:gr64 = COPY %rsi
+# ALL-NEXT: %2:gr64 = SUB64rr %0, %1
body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
@@ -55,17 +51,13 @@ body: |
name: test_sub_i32
legalized: true
regBankSelected: true
-# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
-# ALL: %0 = COPY %edi
-# ALL-NEXT: %1 = COPY %esi
-# ALL-NEXT: %2 = SUB32rr %0, %1
+# ALL: %0:gr32 = COPY %edi
+# ALL-NEXT: %1:gr32 = COPY %esi
+# ALL-NEXT: %2:gr32 = SUB32rr %0, %1
body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
@@ -83,23 +75,18 @@ legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
-# ALL: registers:
-# NO_AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
-# NO_AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
-# NO_AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
-# ALL: %0 = COPY %xmm0
-# ALL-NEXT: %1 = COPY %xmm1
-# SSE-NEXT: %2 = PSUBDrr %0, %1
-# AVX-NEXT: %2 = VPSUBDrr %0, %1
-# AVX512F-NEXT: %2 = VPSUBDrr %0, %1
-# AVX512VL-NEXT: %2 = VPSUBDZ128rr %0, %1
+# NO_AVX512VL: %0:vr128 = COPY %xmm0
+# AVX512VL: %0:vr128x = COPY %xmm0
+# NO_AVX512VL: %1:vr128 = COPY %xmm1
+# AVX512VL: %1:vr128x = COPY %xmm1
+# SSE-NEXT: %2:vr128 = PSUBDrr %0, %1
+# AVX-NEXT: %2:vr128 = VPSUBDrr %0, %1
+# AVX512F-NEXT: %2:vr128 = VPSUBDrr %0, %1
+# AVX512VL-NEXT: %2:vr128x = VPSUBDZ128rr %0, %1
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
@@ -118,23 +105,19 @@ legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
-# ALL: registers:
-# NO_AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
-# NO_AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
-# NO_AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
-# ALL: %0 = COPY %xmm0
-# ALL-NEXT: %1 = COPY %xmm1
-# SSE-NEXT: %2 = SUBPSrr %0, %1
-# AVX-NEXT: %2 = VSUBPSrr %0, %1
-# AVX512F-NEXT: %2 = VSUBPSrr %0, %1
-# AVX512VL-NEXT: %2 = VSUBPSZ128rr %0, %1
+# NO_AVX512VL: %0:vr128 = COPY %xmm0
+# NO_AVX512VL: %1:vr128 = COPY %xmm1
+# SSE-NEXT: %2:vr128 = SUBPSrr %0, %1
+# AVX-NEXT: %2:vr128 = VSUBPSrr %0, %1
+# AVX512F-NEXT: %2:vr128 = VSUBPSrr %0, %1
+#
+# AVX512VL: %0:vr128x = COPY %xmm0
+# AVX512VL: %1:vr128x = COPY %xmm1
+# AVX512VL-NEXT: %2:vr128x = VSUBPSZ128rr %0, %1
body: |
bb.1 (%ir-block.0):
liveins: %xmm0, %xmm1
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-trunc.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-trunc.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-trunc.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-trunc.mir Tue Oct 24 11:04:54 2017
@@ -45,11 +45,8 @@ body: |
liveins: %edi
; CHECK-LABEL: name: trunc_i32toi1
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: gr32
- ; CHECK-NEXT: id: 1, class: gr8
- ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
- ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_8bit
+ ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+ ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; CHECK: %al = COPY [[COPY1]]
; CHECK: RET 0, implicit %al
%0(s32) = COPY %edi
@@ -71,11 +68,8 @@ body: |
liveins: %edi
; CHECK-LABEL: name: trunc_i32toi8
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: gr32
- ; CHECK-NEXT: id: 1, class: gr8
- ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
- ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_8bit
+ ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+ ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; CHECK: %al = COPY [[COPY1]]
; CHECK: RET 0, implicit %al
%0(s32) = COPY %edi
@@ -97,11 +91,8 @@ body: |
liveins: %edi
; CHECK-LABEL: name: trunc_i32toi16
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: gr32
- ; CHECK-NEXT: id: 1, class: gr16
- ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
- ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_16bit
+ ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+ ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
; CHECK: %ax = COPY [[COPY1]]
; CHECK: RET 0, implicit %ax
%0(s32) = COPY %edi
@@ -123,11 +114,8 @@ body: |
liveins: %rdi
; CHECK-LABEL: name: trunc_i64toi8
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: gr64_with_sub_8bit
- ; CHECK-NEXT: id: 1, class: gr8
- ; CHECK: [[COPY:%[0-9]+]] = COPY %rdi
- ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_8bit
+ ; CHECK: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY %rdi
+ ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; CHECK: %al = COPY [[COPY1]]
; CHECK: RET 0, implicit %al
%0(s64) = COPY %rdi
@@ -149,11 +137,8 @@ body: |
liveins: %rdi
; CHECK-LABEL: name: trunc_i64toi16
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: gr64
- ; CHECK-NEXT: id: 1, class: gr16
- ; CHECK: [[COPY:%[0-9]+]] = COPY %rdi
- ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_16bit
+ ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+ ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
; CHECK: %ax = COPY [[COPY1]]
; CHECK: RET 0, implicit %ax
%0(s64) = COPY %rdi
@@ -175,11 +160,8 @@ body: |
liveins: %rdi
; CHECK-LABEL: name: trunc_i64toi32
- ; CHECK: registers:
- ; CHECK-NEXT: id: 0, class: gr64
- ; CHECK-NEXT: id: 1, class: gr32
- ; CHECK: [[COPY:%[0-9]+]] = COPY %rdi
- ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32bit
+ ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+ ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]].sub_32bit
; CHECK: %eax = COPY [[COPY1]]
; CHECK: RET 0, implicit %eax
%0(s64) = COPY %rdi
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-undef.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-undef.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-undef.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-undef.mir Tue Oct 24 11:04:54 2017
@@ -26,9 +26,7 @@ constants:
body: |
bb.1 (%ir-block.0):
; ALL-LABEL: name: test
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr8
- ; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
+ ; ALL: [[DEF:%[0-9]+]]:gr8 = IMPLICIT_DEF
; ALL: %al = COPY [[DEF]]
; ALL: RET 0, implicit %al
%0(s8) = G_IMPLICIT_DEF
@@ -54,13 +52,9 @@ body: |
liveins: %edi
; ALL-LABEL: name: test2
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr8
- ; ALL-NEXT: id: 1, class: gr8
- ; ALL-NEXT: id: 2, class: gr8
- ; ALL: [[COPY:%[0-9]+]] = COPY %dil
- ; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
- ; ALL: [[ADD8rr:%[0-9]+]] = ADD8rr [[COPY]], [[DEF]], implicit-def %eflags
+ ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY %dil
+ ; ALL: [[DEF:%[0-9]+]]:gr8 = IMPLICIT_DEF
+ ; ALL: [[ADD8rr:%[0-9]+]]:gr8 = ADD8rr [[COPY]], [[DEF]], implicit-def %eflags
; ALL: %al = COPY [[ADD8rr]]
; ALL: RET 0, implicit %al
%0(s8) = COPY %dil
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir Tue Oct 24 11:04:54 2017
@@ -23,24 +23,16 @@ body: |
bb.1 (%ir-block.0):
; AVX-LABEL: name: test_unmerge
- ; AVX: registers:
- ; AVX-NEXT: id: 0, class: vr256
- ; AVX-NEXT: id: 1, class: vr128
- ; AVX-NEXT: id: 2, class: vr128
- ; AVX: [[DEF:%[0-9]+]] = IMPLICIT_DEF
- ; AVX: [[COPY:%[0-9]+]] = COPY [[DEF]].sub_xmm
- ; AVX: [[VEXTRACTF128rr:%[0-9]+]] = VEXTRACTF128rr [[DEF]], 1
+ ; AVX: [[DEF:%[0-9]+]]:vr256 = IMPLICIT_DEF
+ ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY [[DEF]].sub_xmm
+ ; AVX: [[VEXTRACTF128rr:%[0-9]+]]:vr128 = VEXTRACTF128rr [[DEF]], 1
; AVX: %xmm0 = COPY [[COPY]]
; AVX: %xmm1 = COPY [[VEXTRACTF128rr]]
; AVX: RET 0, implicit %xmm0, implicit %xmm1
; AVX512VL-LABEL: name: test_unmerge
- ; AVX512VL: registers:
- ; AVX512VL-NEXT: id: 0, class: vr256x
- ; AVX512VL-NEXT: id: 1, class: vr128x
- ; AVX512VL-NEXT: id: 2, class: vr128x
- ; AVX512VL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
- ; AVX512VL: [[COPY:%[0-9]+]] = COPY [[DEF]].sub_xmm
- ; AVX512VL: [[VEXTRACTF32x4Z256rr:%[0-9]+]] = VEXTRACTF32x4Z256rr [[DEF]], 1
+ ; AVX512VL: [[DEF:%[0-9]+]]:vr256x = IMPLICIT_DEF
+ ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY [[DEF]].sub_xmm
+ ; AVX512VL: [[VEXTRACTF32x4Z256rr:%[0-9]+]]:vr128x = VEXTRACTF32x4Z256rr [[DEF]], 1
; AVX512VL: %xmm0 = COPY [[COPY]]
; AVX512VL: %xmm1 = COPY [[VEXTRACTF32x4Z256rr]]
; AVX512VL: RET 0, implicit %xmm0, implicit %xmm1
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir Tue Oct 24 11:04:54 2017
@@ -25,17 +25,11 @@ body: |
bb.1 (%ir-block.0):
; ALL-LABEL: name: test_unmerge_v128
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: vr512
- ; ALL-NEXT: id: 1, class: vr128x
- ; ALL-NEXT: id: 2, class: vr128x
- ; ALL-NEXT: id: 3, class: vr128x
- ; ALL-NEXT: id: 4, class: vr128x
- ; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
- ; ALL: [[COPY:%[0-9]+]] = COPY [[DEF]].sub_xmm
- ; ALL: [[VEXTRACTF32x4Zrr:%[0-9]+]] = VEXTRACTF32x4Zrr [[DEF]], 1
- ; ALL: [[VEXTRACTF32x4Zrr1:%[0-9]+]] = VEXTRACTF32x4Zrr [[DEF]], 2
- ; ALL: [[VEXTRACTF32x4Zrr2:%[0-9]+]] = VEXTRACTF32x4Zrr [[DEF]], 3
+ ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF
+ ; ALL: [[COPY:%[0-9]+]]:vr128x = COPY [[DEF]].sub_xmm
+ ; ALL: [[VEXTRACTF32x4Zrr:%[0-9]+]]:vr128x = VEXTRACTF32x4Zrr [[DEF]], 1
+ ; ALL: [[VEXTRACTF32x4Zrr1:%[0-9]+]]:vr128x = VEXTRACTF32x4Zrr [[DEF]], 2
+ ; ALL: [[VEXTRACTF32x4Zrr2:%[0-9]+]]:vr128x = VEXTRACTF32x4Zrr [[DEF]], 3
; ALL: %xmm0 = COPY [[COPY]]
; ALL: RET 0, implicit %xmm0
%0(<16 x s32>) = IMPLICIT_DEF
@@ -57,13 +51,9 @@ body: |
bb.1 (%ir-block.0):
; ALL-LABEL: name: test_unmerge_v256
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: vr512
- ; ALL-NEXT: id: 1, class: vr256x
- ; ALL-NEXT: id: 2, class: vr256x
- ; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
- ; ALL: [[COPY:%[0-9]+]] = COPY [[DEF]].sub_ymm
- ; ALL: [[VEXTRACTF64x4Zrr:%[0-9]+]] = VEXTRACTF64x4Zrr [[DEF]], 1
+ ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF
+ ; ALL: [[COPY:%[0-9]+]]:vr256x = COPY [[DEF]].sub_ymm
+ ; ALL: [[VEXTRACTF64x4Zrr:%[0-9]+]]:vr256x = VEXTRACTF64x4Zrr [[DEF]], 1
; ALL: %ymm0 = COPY [[COPY]]
; ALL: RET 0, implicit %ymm0
%0(<16 x s32>) = IMPLICIT_DEF
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-xor-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-xor-scalar.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-xor-scalar.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-xor-scalar.mir Tue Oct 24 11:04:54 2017
@@ -41,13 +41,9 @@ body: |
liveins: %edi, %esi
; ALL-LABEL: name: test_xor_i8
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr8
- ; ALL-NEXT: id: 1, class: gr8
- ; ALL-NEXT: id: 2, class: gr8
- ; ALL: [[COPY:%[0-9]+]] = COPY %dil
- ; ALL: [[COPY1:%[0-9]+]] = COPY %sil
- ; ALL: [[XOR8rr:%[0-9]+]] = XOR8rr [[COPY]], [[COPY1]], implicit-def %eflags
+ ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY %dil
+ ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY %sil
+ ; ALL: [[XOR8rr:%[0-9]+]]:gr8 = XOR8rr [[COPY]], [[COPY1]], implicit-def %eflags
; ALL: %al = COPY [[XOR8rr]]
; ALL: RET 0, implicit %al
%0(s8) = COPY %dil
@@ -75,13 +71,9 @@ body: |
liveins: %edi, %esi
; ALL-LABEL: name: test_xor_i16
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr16
- ; ALL-NEXT: id: 1, class: gr16
- ; ALL-NEXT: id: 2, class: gr16
- ; ALL: [[COPY:%[0-9]+]] = COPY %di
- ; ALL: [[COPY1:%[0-9]+]] = COPY %si
- ; ALL: [[XOR16rr:%[0-9]+]] = XOR16rr [[COPY]], [[COPY1]], implicit-def %eflags
+ ; ALL: [[COPY:%[0-9]+]]:gr16 = COPY %di
+ ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY %si
+ ; ALL: [[XOR16rr:%[0-9]+]]:gr16 = XOR16rr [[COPY]], [[COPY1]], implicit-def %eflags
; ALL: %ax = COPY [[XOR16rr]]
; ALL: RET 0, implicit %ax
%0(s16) = COPY %di
@@ -109,13 +101,9 @@ body: |
liveins: %edi, %esi
; ALL-LABEL: name: test_xor_i32
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr32
- ; ALL-NEXT: id: 1, class: gr32
- ; ALL-NEXT: id: 2, class: gr32
- ; ALL: [[COPY:%[0-9]+]] = COPY %edi
- ; ALL: [[COPY1:%[0-9]+]] = COPY %esi
- ; ALL: [[XOR32rr:%[0-9]+]] = XOR32rr [[COPY]], [[COPY1]], implicit-def %eflags
+ ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+ ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
+ ; ALL: [[XOR32rr:%[0-9]+]]:gr32 = XOR32rr [[COPY]], [[COPY1]], implicit-def %eflags
; ALL: %eax = COPY [[XOR32rr]]
; ALL: RET 0, implicit %eax
%0(s32) = COPY %edi
@@ -143,13 +131,9 @@ body: |
liveins: %rdi, %rsi
; ALL-LABEL: name: test_xor_i64
- ; ALL: registers:
- ; ALL-NEXT: id: 0, class: gr64
- ; ALL-NEXT: id: 1, class: gr64
- ; ALL-NEXT: id: 2, class: gr64
- ; ALL: [[COPY:%[0-9]+]] = COPY %rdi
- ; ALL: [[COPY1:%[0-9]+]] = COPY %rsi
- ; ALL: [[XOR64rr:%[0-9]+]] = XOR64rr [[COPY]], [[COPY1]], implicit-def %eflags
+ ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+ ; ALL: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi
+ ; ALL: [[XOR64rr:%[0-9]+]]:gr64 = XOR64rr [[COPY]], [[COPY1]], implicit-def %eflags
; ALL: %rax = COPY [[XOR64rr]]
; ALL: RET 0, implicit %rax
%0(s64) = COPY %rdi
Modified: llvm/trunk/test/CodeGen/X86/debugloc-no-line-0.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/debugloc-no-line-0.ll?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/debugloc-no-line-0.ll (original)
+++ llvm/trunk/test/CodeGen/X86/debugloc-no-line-0.ll Tue Oct 24 11:04:54 2017
@@ -7,9 +7,7 @@
; CHECK: JMP{{.*}}%bb.4.entry, debug-location ![[JUMPLOC:[0-9]+]]
; CHECK: bb.4.entry:
; CHECK: successors:
-; CHECK-NOT: :
; CHECK: JE{{.*}}debug-location ![[JUMPLOC]]
-; CHECK-NOT: :
; CHECK: JMP{{.*}}debug-location ![[JUMPLOC]]
define i32 @main() !dbg !12 {
Modified: llvm/trunk/test/CodeGen/X86/domain-reassignment.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/domain-reassignment.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/domain-reassignment.mir (original)
+++ llvm/trunk/test/CodeGen/X86/domain-reassignment.mir Tue Oct 24 11:04:54 2017
@@ -56,9 +56,6 @@ regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- # CHECK: - { id: 0, class: vk8, preferred-register: '' }
- # CHECK: - { id: 1, class: vk8, preferred-register: '' }
- # CHECK: - { id: 2, class: vk8, preferred-register: '' }
- { id: 0, class: gr8, preferred-register: '' }
- { id: 1, class: gr8, preferred-register: '' }
- { id: 2, class: gr8, preferred-register: '' }
@@ -72,12 +69,8 @@ registers:
- { id: 10, class: fr32x, preferred-register: '' }
- { id: 11, class: gr8, preferred-register: '' }
- { id: 12, class: vk1, preferred-register: '' }
- # CHECK: - { id: 13, class: vk32, preferred-register: '' }
- { id: 13, class: gr32, preferred-register: '' }
- { id: 14, class: vk1, preferred-register: '' }
- # CHECK: - { id: 15, class: vk32, preferred-register: '' }
- # CHECK: - { id: 16, class: vk32, preferred-register: '' }
- # CHECK: - { id: 17, class: vk32, preferred-register: '' }
- { id: 15, class: gr32, preferred-register: '' }
- { id: 16, class: gr32, preferred-register: '' }
- { id: 17, class: gr32, preferred-register: '' }
@@ -139,8 +132,8 @@ body: |
%14 = VCMPSSZrr %7, %8, 0
; check that cross domain copies are replaced with same domain copies.
- ; CHECK: %15 = COPY %14
- ; CHECK: %0 = COPY %15
+ ; CHECK: %15:vk32 = COPY %14
+ ; CHECK: %0:vk8 = COPY %15
%15 = COPY %14
%0 = COPY %15.sub_8bit
@@ -151,8 +144,8 @@ body: |
%12 = VCMPSSZrr %9, %10, 0
; check that cross domain copies are replaced with same domain copies.
- ; CHECK: %13 = COPY %12
- ; CHECK: %1 = COPY %13
+ ; CHECK: %13:vk32 = COPY %12
+ ; CHECK: %1:vk8 = COPY %13
%13 = COPY %12
%1 = COPY %13.sub_8bit
@@ -160,9 +153,9 @@ body: |
bb.3.exit:
; check PHI, IMPLICIT_DEF, and INSERT_SUBREG replacers.
- ; CHECK: %2 = PHI %1, %bb.2.else, %0, %bb.1.if
- ; CHECK: %16 = COPY %2
- ; CHECK: %18 = COPY %16
+ ; CHECK: %2:vk8 = PHI %1, %bb.2.else, %0, %bb.1.if
+ ; CHECK: %16:vk32 = COPY %2
+ ; CHECK: %18:vk1wm = COPY %16
%2 = PHI %1, %bb.2.else, %0, %bb.1.if
%17 = IMPLICIT_DEF
@@ -192,23 +185,12 @@ registers:
- { id: 3, class: vr512, preferred-register: '' }
- { id: 4, class: vr512, preferred-register: '' }
- { id: 5, class: vk8, preferred-register: '' }
- # CHECK: - { id: 6, class: vk32, preferred-register: '' }
- # CHECK: - { id: 7, class: vk8, preferred-register: '' }
- # CHECK: - { id: 8, class: vk32, preferred-register: '' }
- # CHECK: - { id: 9, class: vk32, preferred-register: '' }
- { id: 6, class: gr32, preferred-register: '' }
- { id: 7, class: gr8, preferred-register: '' }
- { id: 8, class: gr32, preferred-register: '' }
- { id: 9, class: gr32, preferred-register: '' }
- { id: 10, class: vk8wm, preferred-register: '' }
- { id: 11, class: vr512, preferred-register: '' }
- # CHECK: - { id: 12, class: vk8, preferred-register: '' }
- # CHECK: - { id: 13, class: vk8, preferred-register: '' }
- # CHECK: - { id: 14, class: vk8, preferred-register: '' }
- # CHECK: - { id: 15, class: vk8, preferred-register: '' }
- # CHECK: - { id: 16, class: vk8, preferred-register: '' }
- # CHECK: - { id: 17, class: vk8, preferred-register: '' }
- # CHECK: - { id: 18, class: vk8, preferred-register: '' }
- { id: 12, class: gr8, preferred-register: '' }
- { id: 13, class: gr8, preferred-register: '' }
- { id: 14, class: gr8, preferred-register: '' }
@@ -253,18 +235,18 @@ body: |
%4 = COPY %zmm3
%5 = VCMPPDZrri %3, %4, 0
- ; CHECK: %6 = COPY %5
- ; CHECK: %7 = COPY %6
+ ; CHECK: %6:vk32 = COPY %5
+ ; CHECK: %7:vk8 = COPY %6
%6 = COPY %5
%7 = COPY %6.sub_8bit
- ; CHECK: %12 = KSHIFTRBri %7, 2
- ; CHECK: %13 = KSHIFTLBri %12, 1
- ; CHECK: %14 = KNOTBrr %13
- ; CHECK: %15 = KORBrr %14, %12
- ; CHECK: %16 = KANDBrr %15, %13
- ; CHECK: %17 = KXORBrr %16, %12
- ; CHECK: %18 = KADDBrr %17, %14
+ ; CHECK: %12:vk8 = KSHIFTRBri %7, 2
+ ; CHECK: %13:vk8 = KSHIFTLBri %12, 1
+ ; CHECK: %14:vk8 = KNOTBrr %13
+ ; CHECK: %15:vk8 = KORBrr %14, %12
+ ; CHECK: %16:vk8 = KANDBrr %15, %13
+ ; CHECK: %17:vk8 = KXORBrr %16, %12
+ ; CHECK: %18:vk8 = KADDBrr %17, %14
%12 = SHR8ri %7, 2, implicit-def dead %eflags
%13 = SHL8ri %12, 1, implicit-def dead %eflags
%14 = NOT8r %13
@@ -273,8 +255,8 @@ body: |
%17 = XOR8rr %16, %12, implicit-def dead %eflags
%18 = ADD8rr %17, %14, implicit-def dead %eflags
- ; CHECK: %9 = COPY %18
- ; CHECK: %10 = COPY %9
+ ; CHECK: %9:vk32 = COPY %18
+ ; CHECK: %10:vk8wm = COPY %9
%8 = IMPLICIT_DEF
%9 = INSERT_SUBREG %8, %18, 1
%10 = COPY %9
@@ -308,22 +290,12 @@ registers:
- { id: 3, class: vr512, preferred-register: '' }
- { id: 4, class: vr512, preferred-register: '' }
- { id: 5, class: vk16, preferred-register: '' }
- # CHECK: - { id: 6, class: vk32, preferred-register: '' }
- # CHECK: - { id: 7, class: vk16, preferred-register: '' }
- # CHECK: - { id: 8, class: vk32, preferred-register: '' }
- # CHECK: - { id: 9, class: vk32, preferred-register: '' }
- { id: 6, class: gr32, preferred-register: '' }
- { id: 7, class: gr16, preferred-register: '' }
- { id: 8, class: gr32, preferred-register: '' }
- { id: 9, class: gr32, preferred-register: '' }
- { id: 10, class: vk16wm, preferred-register: '' }
- { id: 11, class: vr512, preferred-register: '' }
- # CHECK: - { id: 12, class: vk16, preferred-register: '' }
- # CHECK: - { id: 13, class: vk16, preferred-register: '' }
- # CHECK: - { id: 14, class: vk16, preferred-register: '' }
- # CHECK: - { id: 15, class: vk16, preferred-register: '' }
- # CHECK: - { id: 16, class: vk16, preferred-register: '' }
- # CHECK: - { id: 17, class: vk16, preferred-register: '' }
- { id: 12, class: gr16, preferred-register: '' }
- { id: 13, class: gr16, preferred-register: '' }
- { id: 14, class: gr16, preferred-register: '' }
@@ -367,17 +339,17 @@ body: |
%4 = COPY %zmm3
%5 = VCMPPSZrri %3, %4, 0
- ; CHECK: %6 = COPY %5
- ; CHECK: %7 = COPY %6
+ ; CHECK: %6:vk32 = COPY %5
+ ; CHECK: %7:vk16 = COPY %6
%6 = COPY %5
%7 = COPY %6.sub_16bit
- ; CHECK: %12 = KSHIFTRWri %7, 2
- ; CHECK: %13 = KSHIFTLWri %12, 1
- ; CHECK: %14 = KNOTWrr %13
- ; CHECK: %15 = KORWrr %14, %12
- ; CHECK: %16 = KANDWrr %15, %13
- ; CHECK: %17 = KXORWrr %16, %12
+ ; CHECK: %12:vk16 = KSHIFTRWri %7, 2
+ ; CHECK: %13:vk16 = KSHIFTLWri %12, 1
+ ; CHECK: %14:vk16 = KNOTWrr %13
+ ; CHECK: %15:vk16 = KORWrr %14, %12
+ ; CHECK: %16:vk16 = KANDWrr %15, %13
+ ; CHECK: %17:vk16 = KXORWrr %16, %12
%12 = SHR16ri %7, 2, implicit-def dead %eflags
%13 = SHL16ri %12, 1, implicit-def dead %eflags
%14 = NOT16r %13
@@ -385,8 +357,8 @@ body: |
%16 = AND16rr %15, %13, implicit-def dead %eflags
%17 = XOR16rr %16, %12, implicit-def dead %eflags
- ; CHECK: %9 = COPY %17
- ; CHECK: %10 = COPY %9
+ ; CHECK: %9:vk32 = COPY %17
+ ; CHECK: %10:vk16wm = COPY %9
%8 = IMPLICIT_DEF
%9 = INSERT_SUBREG %8, %17, 3
%10 = COPY %9
@@ -419,15 +391,6 @@ registers:
- { id: 2, class: vr512, preferred-register: '' }
- { id: 3, class: vk32wm, preferred-register: '' }
- { id: 4, class: vr512, preferred-register: '' }
- # CHECK: - { id: 5, class: vk32, preferred-register: '' }
- # CHECK: - { id: 6, class: vk32, preferred-register: '' }
- # CHECK: - { id: 7, class: vk32, preferred-register: '' }
- # CHECK: - { id: 8, class: vk32, preferred-register: '' }
- # CHECK: - { id: 9, class: vk32, preferred-register: '' }
- # CHECK: - { id: 10, class: vk32, preferred-register: '' }
- # CHECK: - { id: 11, class: vk32, preferred-register: '' }
- # CHECK: - { id: 12, class: vk32, preferred-register: '' }
- # CHECK: - { id: 13, class: vk32, preferred-register: '' }
- { id: 5, class: gr32, preferred-register: '' }
- { id: 6, class: gr32, preferred-register: '' }
- { id: 7, class: gr32, preferred-register: '' }
@@ -469,15 +432,15 @@ body: |
%1 = COPY %zmm0
%2 = COPY %zmm1
- ; CHECK: %5 = KMOVDkm %0, 1, _, 0, _
- ; CHECK: %6 = KSHIFTRDri %5, 2
- ; CHECK: %7 = KSHIFTLDri %6, 1
- ; CHECK: %8 = KNOTDrr %7
- ; CHECK: %9 = KORDrr %8, %6
- ; CHECK: %10 = KANDDrr %9, %7
- ; CHECK: %11 = KXORDrr %10, %6
- ; CHECK: %12 = KANDNDrr %11, %9
- ; CHECK: %13 = KADDDrr %12, %11
+ ; CHECK: %5:vk32 = KMOVDkm %0, 1, _, 0, _
+ ; CHECK: %6:vk32 = KSHIFTRDri %5, 2
+ ; CHECK: %7:vk32 = KSHIFTLDri %6, 1
+ ; CHECK: %8:vk32 = KNOTDrr %7
+ ; CHECK: %9:vk32 = KORDrr %8, %6
+ ; CHECK: %10:vk32 = KANDDrr %9, %7
+ ; CHECK: %11:vk32 = KXORDrr %10, %6
+ ; CHECK: %12:vk32 = KANDNDrr %11, %9
+ ; CHECK: %13:vk32 = KADDDrr %12, %11
%5 = MOV32rm %0, 1, _, 0, _
%6 = SHR32ri %5, 2, implicit-def dead %eflags
%7 = SHL32ri %6, 1, implicit-def dead %eflags
@@ -488,7 +451,7 @@ body: |
%12 = ANDN32rr %11, %9, implicit-def dead %eflags
%13 = ADD32rr %12, %11, implicit-def dead %eflags
- ; CHECK: %3 = COPY %13
+ ; CHECK: %3:vk32wm = COPY %13
%3 = COPY %13
%4 = VMOVDQU16Zrrk %2, killed %3, %1
VMOVDQA32Zmr %0, 1, _, 0, _, killed %4
@@ -519,15 +482,6 @@ registers:
- { id: 2, class: vr512, preferred-register: '' }
- { id: 3, class: vk64wm, preferred-register: '' }
- { id: 4, class: vr512, preferred-register: '' }
- # CHECK: - { id: 5, class: vk64, preferred-register: '' }
- # CHECK: - { id: 6, class: vk64, preferred-register: '' }
- # CHECK: - { id: 7, class: vk64, preferred-register: '' }
- # CHECK: - { id: 8, class: vk64, preferred-register: '' }
- # CHECK: - { id: 9, class: vk64, preferred-register: '' }
- # CHECK: - { id: 10, class: vk64, preferred-register: '' }
- # CHECK: - { id: 11, class: vk64, preferred-register: '' }
- # CHECK: - { id: 12, class: vk64, preferred-register: '' }
- # CHECK: - { id: 13, class: vk64, preferred-register: '' }
- { id: 5, class: gr64, preferred-register: '' }
- { id: 6, class: gr64, preferred-register: '' }
- { id: 7, class: gr64, preferred-register: '' }
@@ -569,15 +523,15 @@ body: |
%1 = COPY %zmm0
%2 = COPY %zmm1
- ; CHECK: %5 = KMOVQkm %0, 1, _, 0, _
- ; CHECK: %6 = KSHIFTRQri %5, 2
- ; CHECK: %7 = KSHIFTLQri %6, 1
- ; CHECK: %8 = KNOTQrr %7
- ; CHECK: %9 = KORQrr %8, %6
- ; CHECK: %10 = KANDQrr %9, %7
- ; CHECK: %11 = KXORQrr %10, %6
- ; CHECK: %12 = KANDNQrr %11, %9
- ; CHECK: %13 = KADDQrr %12, %11
+ ; CHECK: %5:vk64 = KMOVQkm %0, 1, _, 0, _
+ ; CHECK: %6:vk64 = KSHIFTRQri %5, 2
+ ; CHECK: %7:vk64 = KSHIFTLQri %6, 1
+ ; CHECK: %8:vk64 = KNOTQrr %7
+ ; CHECK: %9:vk64 = KORQrr %8, %6
+ ; CHECK: %10:vk64 = KANDQrr %9, %7
+ ; CHECK: %11:vk64 = KXORQrr %10, %6
+ ; CHECK: %12:vk64 = KANDNQrr %11, %9
+ ; CHECK: %13:vk64 = KADDQrr %12, %11
%5 = MOV64rm %0, 1, _, 0, _
%6 = SHR64ri %5, 2, implicit-def dead %eflags
%7 = SHL64ri %6, 1, implicit-def dead %eflags
@@ -588,7 +542,7 @@ body: |
%12 = ANDN64rr %11, %9, implicit-def dead %eflags
%13 = ADD64rr %12, %11, implicit-def dead %eflags
- ; CHECK: %3 = COPY %13
+ ; CHECK: %3:vk64wm = COPY %13
%3 = COPY %13
%4 = VMOVDQU8Zrrk %2, killed %3, %1
VMOVDQA32Zmr %0, 1, _, 0, _, killed %4
@@ -619,11 +573,8 @@ registers:
- { id: 2, class: vr512, preferred-register: '' }
- { id: 3, class: vk16wm, preferred-register: '' }
- { id: 4, class: vr512, preferred-register: '' }
- # CHECK: - { id: 5, class: vk16, preferred-register: '' }
- # CHECK: - { id: 6, class: vk16, preferred-register: '' }
- { id: 5, class: gr16, preferred-register: '' }
- { id: 6, class: gr16, preferred-register: '' }
- # CHECK: - { id: 7, class: vk8, preferred-register: '' }
liveins:
- { reg: '%rdi', virtual-reg: '%0' }
- { reg: '%zmm0', virtual-reg: '%1' }
@@ -656,13 +607,13 @@ body: |
%1 = COPY %zmm0
%2 = COPY %zmm1
- ; CHECK: %7 = KMOVBkm %0, 1, _, 0, _
- ; CHECK: %5 = COPY %7
- ; CHECK: %6 = KNOTWrr %5
+ ; CHECK: %7:vk8 = KMOVBkm %0, 1, _, 0, _
+ ; CHECK: %5:vk16 = COPY %7
+ ; CHECK: %6:vk16 = KNOTWrr %5
%5 = MOVZX16rm8 %0, 1, _, 0, _
%6 = NOT16r %5
- ; CHECK: %3 = COPY %6
+ ; CHECK: %3:vk16wm = COPY %6
%3 = COPY %6
%4 = VMOVAPSZrrk %2, killed %3, %1
VMOVAPSZmr %0, 1, _, 0, _, killed %4
@@ -684,14 +635,9 @@ registers:
- { id: 2, class: vr512, preferred-register: '' }
- { id: 3, class: vk64wm, preferred-register: '' }
- { id: 4, class: vr512, preferred-register: '' }
- # CHECK: - { id: 5, class: vk32, preferred-register: '' }
- # CHECK: - { id: 6, class: vk32, preferred-register: '' }
- # CHECK: - { id: 7, class: vk32, preferred-register: '' }
- { id: 5, class: gr32, preferred-register: '' }
- { id: 6, class: gr32, preferred-register: '' }
- { id: 7, class: gr32, preferred-register: '' }
- # CHECK: - { id: 8, class: vk8, preferred-register: '' }
- # CHECK: - { id: 9, class: vk16, preferred-register: '' }
liveins:
- { reg: '%rdi', virtual-reg: '%0' }
- { reg: '%zmm0', virtual-reg: '%1' }
@@ -724,16 +670,16 @@ body: |
%1 = COPY %zmm0
%2 = COPY %zmm1
- ; CHECK: %8 = KMOVBkm %0, 1, _, 0, _
- ; CHECK: %5 = COPY %8
- ; CHECK: %9 = KMOVWkm %0, 1, _, 0, _
- ; CHECK: %6 = COPY %9
- ; CHECK: %7 = KADDDrr %5, %6
+ ; CHECK: %8:vk8 = KMOVBkm %0, 1, _, 0, _
+ ; CHECK: %5:vk32 = COPY %8
+ ; CHECK: %9:vk16 = KMOVWkm %0, 1, _, 0, _
+ ; CHECK: %6:vk32 = COPY %9
+ ; CHECK: %7:vk32 = KADDDrr %5, %6
%5 = MOVZX32rm8 %0, 1, _, 0, _
%6 = MOVZX32rm16 %0, 1, _, 0, _
%7 = ADD32rr %5, %6, implicit-def dead %eflags
- ; CHECK: %3 = COPY %7
+ ; CHECK: %3:vk64wm = COPY %7
%3 = COPY %7
%4 = VMOVDQU16Zrrk %2, killed %3, %1
VMOVDQA32Zmr %0, 1, _, 0, _, killed %4
@@ -755,14 +701,9 @@ registers:
- { id: 2, class: vr512, preferred-register: '' }
- { id: 3, class: vk64wm, preferred-register: '' }
- { id: 4, class: vr512, preferred-register: '' }
- # CHECK: - { id: 5, class: vk64, preferred-register: '' }
- # CHECK: - { id: 6, class: vk64, preferred-register: '' }
- # CHECK: - { id: 7, class: vk64, preferred-register: '' }
- { id: 5, class: gr64, preferred-register: '' }
- { id: 6, class: gr64, preferred-register: '' }
- { id: 7, class: gr64, preferred-register: '' }
- # CHECK: - { id: 8, class: vk8, preferred-register: '' }
- # CHECK: - { id: 9, class: vk16, preferred-register: '' }
liveins:
- { reg: '%rdi', virtual-reg: '%0' }
- { reg: '%zmm0', virtual-reg: '%1' }
@@ -795,16 +736,16 @@ body: |
%1 = COPY %zmm0
%2 = COPY %zmm1
- ; CHECK: %8 = KMOVBkm %0, 1, _, 0, _
- ; CHECK: %5 = COPY %8
- ; CHECK: %9 = KMOVWkm %0, 1, _, 0, _
- ; CHECK: %6 = COPY %9
- ; CHECK: %7 = KADDQrr %5, %6
+ ; CHECK: %8:vk8 = KMOVBkm %0, 1, _, 0, _
+ ; CHECK: %5:vk64 = COPY %8
+ ; CHECK: %9:vk16 = KMOVWkm %0, 1, _, 0, _
+ ; CHECK: %6:vk64 = COPY %9
+ ; CHECK: %7:vk64 = KADDQrr %5, %6
%5 = MOVZX64rm8 %0, 1, _, 0, _
%6 = MOVZX64rm16 %0, 1, _, 0, _
%7 = ADD64rr %5, %6, implicit-def dead %eflags
- ; CHECK: %3 = COPY %7
+ ; CHECK: %3:vk64wm = COPY %7
%3 = COPY %7
%4 = VMOVDQU8Zrrk %2, killed %3, %1
VMOVDQA32Zmr %0, 1, _, 0, _, killed %4
Modified: llvm/trunk/test/CodeGen/X86/implicit-use-spill.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/implicit-use-spill.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/implicit-use-spill.mir (original)
+++ llvm/trunk/test/CodeGen/X86/implicit-use-spill.mir Tue Oct 24 11:04:54 2017
@@ -14,7 +14,7 @@ body: |
; CHECK-NEXT: MOV64mr [[SLOT:%stack.[0-9]+]], 1, _, 0, _, [[VAL]]
; CHECK-NEXT: NOOP csr_noregs
; We need to reload before the (implicit) use.
- ; CHECK-NEXT: [[RELOADED_VAL:%[0-9]+]] = MOV64rm [[SLOT]], 1, _, 0, _
+ ; CHECK-NEXT: [[RELOADED_VAL:%[0-9]+]]:gr64 = MOV64rm [[SLOT]], 1, _, 0, _
; CHECK-NEXT: NOOP implicit [[RELOADED_VAL]]
NOOP implicit-def %0
NOOP csr_noregs
Modified: llvm/trunk/test/CodeGen/X86/lea-opt-with-debug.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lea-opt-with-debug.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/lea-opt-with-debug.mir (original)
+++ llvm/trunk/test/CodeGen/X86/lea-opt-with-debug.mir Tue Oct 24 11:04:54 2017
@@ -95,9 +95,9 @@ body: |
bb.0 (%ir-block.0):
successors: %bb.1(0x80000000)
- ; CHECK: %3 = LEA64r %2, 2, %2, 0, _, debug-location !13
- ; CHECK-NEXT: %4 = LEA64r %1, 4, %3, 0, _, debug-location !13
- ; CHECK-NOT: %0 = LEA64r %1, 4, %3, 8, _, debug-location !14
+ ; CHECK: %3:gr64_nosp = LEA64r %2, 2, %2, 0, _, debug-location !13
+ ; CHECK-NEXT: %4:gr64 = LEA64r %1, 4, %3, 0, _, debug-location !13
+ ; CHECK-NOT: %0:gr64 = LEA64r %1, 4, %3, 8, _, debug-location !14
; CHECK: DBG_VALUE debug-use %4, debug-use _, !11, !DIExpression(DW_OP_plus_uconst, 8, DW_OP_stack_value), debug-location !15
%1 = MOV64rm %rip, 1, _, @c, _, debug-location !13 :: (dereferenceable load 8 from @c)
@@ -110,7 +110,7 @@ body: |
DBG_VALUE debug-use %0, debug-use _, !11, !DIExpression(), debug-location !15
; CHECK-LABEL: bb.1 (%ir-block.8):
- ; CHECK: %6 = MOV32rm %4, 1, _, 8, _, debug-location !17 :: (load 4 from %ir.7)
+ ; CHECK: %6:gr32 = MOV32rm %4, 1, _, 8, _, debug-location !17 :: (load 4 from %ir.7)
bb.1 (%ir-block.8):
successors: %bb.1(0x80000000)
Modified: llvm/trunk/test/CodeGen/X86/movtopush.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/movtopush.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/movtopush.mir (original)
+++ llvm/trunk/test/CodeGen/X86/movtopush.mir Tue Oct 24 11:04:54 2017
@@ -41,10 +41,10 @@
# CHECK-NEXT: CALLpcrel32 @good, csr_32, implicit %esp, implicit-def %esp
# CHECK-NEXT: ADJCALLSTACKUP32 16, 0, implicit-def dead %esp, implicit-def dead %eflags, implicit %esp
# CHECK-NEXT: ADJCALLSTACKDOWN32 20, 0, 20, implicit-def dead %esp, implicit-def dead %eflags, implicit %esp
-# CHECK-NEXT: %1 = MOV32rm %stack.2.s, 1, _, 0, _ :: (load 4 from %stack.2.s, align 8)
-# CHECK-NEXT: %2 = MOV32rm %stack.2.s, 1, _, 4, _ :: (load 4 from %stack.2.s + 4)
-# CHECK-NEXT: %4 = LEA32r %stack.0.p, 1, _, 0, _
-# CHECK-NEXT: %5 = LEA32r %stack.1.q, 1, _, 0, _
+# CHECK-NEXT: %1:gr32 = MOV32rm %stack.2.s, 1, _, 0, _ :: (load 4 from %stack.2.s, align 8)
+# CHECK-NEXT: %2:gr32 = MOV32rm %stack.2.s, 1, _, 4, _ :: (load 4 from %stack.2.s + 4)
+# CHECK-NEXT: %4:gr32 = LEA32r %stack.0.p, 1, _, 0, _
+# CHECK-NEXT: %5:gr32 = LEA32r %stack.1.q, 1, _, 0, _
# CHECK-NEXT: PUSH32r %4, implicit-def %esp, implicit %esp
# CHECK-NEXT: PUSH32r %5, implicit-def %esp, implicit %esp
# CHECK-NEXT: PUSH32i8 6, implicit-def %esp, implicit %esp
Modified: llvm/trunk/test/CodeGen/X86/peephole-recurrence.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/peephole-recurrence.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/peephole-recurrence.mir (original)
+++ llvm/trunk/test/CodeGen/X86/peephole-recurrence.mir Tue Oct 24 11:04:54 2017
@@ -4,54 +4,54 @@
define i32 @foo(i32 %a) {
bb0:
br label %bb1
-
+
bb1: ; preds = %bb7, %bb0
%vreg0 = phi i32 [ 0, %bb0 ], [ %vreg3, %bb7 ]
%cond0 = icmp eq i32 %a, 0
br i1 %cond0, label %bb4, label %bb3
-
+
bb3: ; preds = %bb1
br label %bb4
-
+
bb4: ; preds = %bb1, %bb3
%vreg5 = phi i32 [ 2, %bb3 ], [ 1, %bb1 ]
%cond1 = icmp eq i32 %vreg5, 0
br i1 %cond1, label %bb7, label %bb6
-
+
bb6: ; preds = %bb4
br label %bb7
-
+
bb7: ; preds = %bb4, %bb6
%vreg1 = phi i32 [ 2, %bb6 ], [ 1, %bb4 ]
%vreg2 = add i32 %vreg5, %vreg0
%vreg3 = add i32 %vreg1, %vreg2
%cond2 = icmp slt i32 %vreg3, 10
br i1 %cond2, label %bb1, label %bb8
-
+
bb8: ; preds = %bb7
ret i32 0
}
-
+
define i32 @bar(i32 %a, i32* %p) {
bb0:
br label %bb1
-
+
bb1: ; preds = %bb7, %bb0
%vreg0 = phi i32 [ 0, %bb0 ], [ %vreg3, %bb7 ]
%cond0 = icmp eq i32 %a, 0
br i1 %cond0, label %bb4, label %bb3
-
+
bb3: ; preds = %bb1
br label %bb4
-
+
bb4: ; preds = %bb1, %bb3
%vreg5 = phi i32 [ 2, %bb3 ], [ 1, %bb1 ]
%cond1 = icmp eq i32 %vreg5, 0
br i1 %cond1, label %bb7, label %bb6
-
+
bb6: ; preds = %bb4
br label %bb7
-
+
bb7: ; preds = %bb4, %bb6
%vreg1 = phi i32 [ 2, %bb6 ], [ 1, %bb4 ]
%vreg2 = add i32 %vreg5, %vreg0
@@ -59,7 +59,7 @@
%vreg3 = add i32 %vreg1, %vreg2
%cond2 = icmp slt i32 %vreg3, 10
br i1 %cond2, label %bb1, label %bb8
-
+
bb8: ; preds = %bb7
ret i32 0
}
@@ -71,7 +71,7 @@
# the recurrence are tied. This will remove redundant copy instruction.
name: foo
tracksRegLiveness: true
-registers:
+registers:
- { id: 0, class: gr32, preferred-register: '' }
- { id: 1, class: gr32, preferred-register: '' }
- { id: 2, class: gr32, preferred-register: '' }
@@ -85,60 +85,60 @@ registers:
- { id: 10, class: gr32, preferred-register: '' }
- { id: 11, class: gr32, preferred-register: '' }
- { id: 12, class: gr32, preferred-register: '' }
-liveins:
+liveins:
- { reg: '%edi', virtual-reg: '%4' }
body: |
bb.0.bb0:
successors: %bb.1.bb1(0x80000000)
liveins: %edi
-
+
%4 = COPY %edi
%5 = MOV32r0 implicit-def dead %eflags
-
+
bb.1.bb1:
successors: %bb.3.bb4(0x30000000), %bb.2.bb3(0x50000000)
-
- ; CHECK: %0 = PHI %5, %bb.0.bb0, %3, %bb.5.bb7
+
+ ; CHECK: %0:gr32 = PHI %5, %bb.0.bb0, %3, %bb.5.bb7
%0 = PHI %5, %bb.0.bb0, %3, %bb.5.bb7
%6 = MOV32ri 1
TEST32rr %4, %4, implicit-def %eflags
JE_1 %bb.3.bb4, implicit %eflags
JMP_1 %bb.2.bb3
-
+
bb.2.bb3:
successors: %bb.3.bb4(0x80000000)
-
+
%7 = MOV32ri 2
-
+
bb.3.bb4:
successors: %bb.5.bb7(0x30000000), %bb.4.bb6(0x50000000)
-
+
%1 = PHI %6, %bb.1.bb1, %7, %bb.2.bb3
TEST32rr %1, %1, implicit-def %eflags
JE_1 %bb.5.bb7, implicit %eflags
JMP_1 %bb.4.bb6
-
+
bb.4.bb6:
successors: %bb.5.bb7(0x80000000)
-
+
%9 = MOV32ri 2
-
+
bb.5.bb7:
successors: %bb.1.bb1(0x7c000000), %bb.6.bb8(0x04000000)
-
+
%2 = PHI %6, %bb.3.bb4, %9, %bb.4.bb6
%10 = ADD32rr %1, %0, implicit-def dead %eflags
- ; CHECK: %10 = ADD32rr
+ ; CHECK: %10:gr32 = ADD32rr
; CHECK-SAME: %0,
; CHECK-SAME: %1,
%3 = ADD32rr %2, killed %10, implicit-def dead %eflags
- ; CHECK: %3 = ADD32rr
+ ; CHECK: %3:gr32 = ADD32rr
; CHECK-SAME: %10,
; CHECK-SAME: %2,
%11 = SUB32ri8 %3, 10, implicit-def %eflags
JL_1 %bb.1.bb1, implicit %eflags
JMP_1 %bb.6.bb8
-
+
bb.6.bb8:
%12 = MOV32r0 implicit-def dead %eflags
%eax = COPY %12
@@ -149,10 +149,10 @@ body: |
# Here a recurrence is formulated around %0, %11, and %3, but operands should
# not be commuted because %0 has a use outside of recurrence. This is to
# prevent the case of commuting operands ties the values with overlapping live
-# ranges.
+# ranges.
name: bar
tracksRegLiveness: true
-registers:
+registers:
- { id: 0, class: gr32, preferred-register: '' }
- { id: 1, class: gr32, preferred-register: '' }
- { id: 2, class: gr32, preferred-register: '' }
@@ -167,63 +167,63 @@ registers:
- { id: 11, class: gr32, preferred-register: '' }
- { id: 12, class: gr32, preferred-register: '' }
- { id: 13, class: gr32, preferred-register: '' }
-liveins:
+liveins:
- { reg: '%edi', virtual-reg: '%4' }
- { reg: '%rsi', virtual-reg: '%5' }
body: |
bb.0.bb0:
successors: %bb.1.bb1(0x80000000)
liveins: %edi, %rsi
-
+
%5 = COPY %rsi
%4 = COPY %edi
%6 = MOV32r0 implicit-def dead %eflags
-
+
bb.1.bb1:
successors: %bb.3.bb4(0x30000000), %bb.2.bb3(0x50000000)
-
+
%0 = PHI %6, %bb.0.bb0, %3, %bb.5.bb7
- ; CHECK: %0 = PHI %6, %bb.0.bb0, %3, %bb.5.bb7
+ ; CHECK: %0:gr32 = PHI %6, %bb.0.bb0, %3, %bb.5.bb7
%7 = MOV32ri 1
TEST32rr %4, %4, implicit-def %eflags
JE_1 %bb.3.bb4, implicit %eflags
JMP_1 %bb.2.bb3
-
+
bb.2.bb3:
successors: %bb.3.bb4(0x80000000)
-
+
%8 = MOV32ri 2
-
+
bb.3.bb4:
successors: %bb.5.bb7(0x30000000), %bb.4.bb6(0x50000000)
-
+
%1 = PHI %7, %bb.1.bb1, %8, %bb.2.bb3
TEST32rr %1, %1, implicit-def %eflags
JE_1 %bb.5.bb7, implicit %eflags
JMP_1 %bb.4.bb6
-
+
bb.4.bb6:
successors: %bb.5.bb7(0x80000000)
-
+
%10 = MOV32ri 2
-
+
bb.5.bb7:
successors: %bb.1.bb1(0x7c000000), %bb.6.bb8(0x04000000)
-
+
%2 = PHI %7, %bb.3.bb4, %10, %bb.4.bb6
%11 = ADD32rr %1, %0, implicit-def dead %eflags
- ; CHECK: %11 = ADD32rr
+ ; CHECK: %11:gr32 = ADD32rr
; CHECK-SAME: %1,
; CHECK-SAME: %0,
MOV32mr %5, 1, _, 0, _, %0 :: (store 4 into %ir.p)
%3 = ADD32rr %2, killed %11, implicit-def dead %eflags
- ; CHECK: %3 = ADD32rr
+ ; CHECK: %3:gr32 = ADD32rr
; CHECK-SAME: %2,
; CHECK-SAME: %11,
%12 = SUB32ri8 %3, 10, implicit-def %eflags
JL_1 %bb.1.bb1, implicit %eflags
JMP_1 %bb.6.bb8
-
+
bb.6.bb8:
%13 = MOV32r0 implicit-def dead %eflags
%eax = COPY %13
Modified: llvm/trunk/test/CodeGen/X86/peephole.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/peephole.mir?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/peephole.mir (original)
+++ llvm/trunk/test/CodeGen/X86/peephole.mir Tue Oct 24 11:04:54 2017
@@ -19,18 +19,18 @@ registers:
body: |
bb.0:
- ; CHECK: %1 = VMOVDI2SSrr %0
- ; CHECK: %7 = COPY %0
+ ; CHECK: %1:fr32 = VMOVDI2SSrr %0
+ ; CHECK: %7:gr32 = COPY %0
; CHECK: NOOP implicit %7
%0 = MOV32ri 42
%1 = VMOVDI2SSrr %0
%2 = MOVSS2DIrr %1
NOOP implicit %2
- ; CHECK: %4 = VMOVDI2SSrr %3
+ ; CHECK: %4:fr32 = VMOVDI2SSrr %3
; CHECK-NOT: COPY
- ; CHECK: %5 = MOVSS2DIrr %4
- ; CHECK: %6 = SUBREG_TO_REG %5, 0
+ ; CHECK: %5:gr32 = MOVSS2DIrr %4
+ ; CHECK: %6:gr64 = SUBREG_TO_REG %5, 0
; CHECK: NOOP implicit %6
%3 = MOV32ri 42
%4 = VMOVDI2SSrr %3
Modified: llvm/trunk/test/CodeGen/X86/sqrt-fastmath-mir.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sqrt-fastmath-mir.ll?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sqrt-fastmath-mir.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sqrt-fastmath-mir.ll Tue Oct 24 11:04:54 2017
@@ -5,21 +5,21 @@ declare float @llvm.sqrt.f32(float) #0
define float @foo(float %f) #0 {
; CHECK: {{name: *foo}}
; CHECK: body:
-; CHECK: %0 = COPY %xmm0
-; CHECK: %1 = VRSQRTSSr killed %2, %0
-; CHECK: %3 = VMULSSrr %0, %1
-; CHECK: %4 = VMOVSSrm
-; CHECK: %5 = VFMADD213SSr %1, killed %3, %4
-; CHECK: %6 = VMOVSSrm
-; CHECK: %7 = VMULSSrr %1, %6
-; CHECK: %8 = VMULSSrr killed %7, killed %5
-; CHECK: %9 = VMULSSrr %0, %8
-; CHECK: %10 = VFMADD213SSr %8, %9, %4
-; CHECK: %11 = VMULSSrr %9, %6
-; CHECK: %12 = VMULSSrr killed %11, killed %10
-; CHECK: %14 = FsFLD0SS
-; CHECK: %15 = VCMPSSrr %0, killed %14, 0
-; CHECK: %17 = VANDNPSrr killed %16, killed %13
+; CHECK: %0:fr32 = COPY %xmm0
+; CHECK: %1:fr32 = VRSQRTSSr killed %2, %0
+; CHECK: %3:fr32 = VMULSSrr %0, %1
+; CHECK: %4:fr32 = VMOVSSrm
+; CHECK: %5:fr32 = VFMADD213SSr %1, killed %3, %4
+; CHECK: %6:fr32 = VMOVSSrm
+; CHECK: %7:fr32 = VMULSSrr %1, %6
+; CHECK: %8:fr32 = VMULSSrr killed %7, killed %5
+; CHECK: %9:fr32 = VMULSSrr %0, %8
+; CHECK: %10:fr32 = VFMADD213SSr %8, %9, %4
+; CHECK: %11:fr32 = VMULSSrr %9, %6
+; CHECK: %12:fr32 = VMULSSrr killed %11, killed %10
+; CHECK: %14:fr32 = FsFLD0SS
+; CHECK: %15:fr32 = VCMPSSrr %0, killed %14, 0
+; CHECK: %17:vr128 = VANDNPSrr killed %16, killed %13
; CHECK: %xmm0 = COPY %18
; CHECK: RET 0, %xmm0
%call = tail call float @llvm.sqrt.f32(float %f) #1
@@ -29,18 +29,18 @@ define float @foo(float %f) #0 {
define float @rfoo(float %f) #0 {
; CHECK: {{name: *rfoo}}
; CHECK: body: |
-; CHECK: %0 = COPY %xmm0
-; CHECK: %1 = VRSQRTSSr killed %2, %0
-; CHECK: %3 = VMULSSrr %0, %1
-; CHECK: %4 = VMOVSSrm
-; CHECK: %5 = VFMADD213SSr %1, killed %3, %4
-; CHECK: %6 = VMOVSSrm
-; CHECK: %7 = VMULSSrr %1, %6
-; CHECK: %8 = VMULSSrr killed %7, killed %5
-; CHECK: %9 = VMULSSrr %0, %8
-; CHECK: %10 = VFMADD213SSr %8, killed %9, %4
-; CHECK: %11 = VMULSSrr %8, %6
-; CHECK: %12 = VMULSSrr killed %11, killed %10
+; CHECK: %0:fr32 = COPY %xmm0
+; CHECK: %1:fr32 = VRSQRTSSr killed %2, %0
+; CHECK: %3:fr32 = VMULSSrr %0, %1
+; CHECK: %4:fr32 = VMOVSSrm
+; CHECK: %5:fr32 = VFMADD213SSr %1, killed %3, %4
+; CHECK: %6:fr32 = VMOVSSrm
+; CHECK: %7:fr32 = VMULSSrr %1, %6
+; CHECK: %8:fr32 = VMULSSrr killed %7, killed %5
+; CHECK: %9:fr32 = VMULSSrr %0, %8
+; CHECK: %10:fr32 = VFMADD213SSr %8, killed %9, %4
+; CHECK: %11:fr32 = VMULSSrr %8, %6
+; CHECK: %12:fr32 = VMULSSrr killed %11, killed %10
; CHECK: %xmm0 = COPY %12
; CHECK: RET 0, %xmm0
%sqrt = tail call float @llvm.sqrt.f32(float %f)
Modified: llvm/trunk/test/CodeGen/X86/tail-dup-debugloc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tail-dup-debugloc.ll?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tail-dup-debugloc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tail-dup-debugloc.ll Tue Oct 24 11:04:54 2017
@@ -1,10 +1,10 @@
; RUN: llc -stop-after=tailduplication < %s | FileCheck %s
;
-; Check that DebugLoc attached to the branch instruction of
+; Check that DebugLoc attached to the branch instruction of
; 'while.cond1.preheader.lr.ph' survives after tailduplication pass.
;
; CHECK: [[DLOC:![0-9]+]] = !DILocation(line: 9, column: 5, scope: !{{[0-9]+}})
-; CHECK: [[VREG:%[^ ]+]] = COPY %rdi
+; CHECK: [[VREG:%[^ ]+]]:gr64 = COPY %rdi
; CHECK: TEST64rr [[VREG]], [[VREG]]
; CHECK-NEXT: JE_1 {{.+}}, debug-location [[DLOC]]
; CHECK-NEXT: JMP_1 {{.+}}, debug-location [[DLOC]]
Modified: llvm/trunk/test/CodeGen/X86/update-terminator-debugloc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/update-terminator-debugloc.ll?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/update-terminator-debugloc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/update-terminator-debugloc.ll Tue Oct 24 11:04:54 2017
@@ -15,18 +15,18 @@
; 12 }
; 13 return ret;
; 14 }
-;
-; With the test code, LLVM-IR below shows that loop-control branches have a
+;
+; With the test code, LLVM-IR below shows that loop-control branches have a
; debug location of line 6 (branches in entry and for.body block). Make sure that
; these debug locations are propaged correctly to lowered instructions.
;
; CHECK: [[DLOC:![0-9]+]] = !DILocation(line: 6
-; CHECK-DAG: [[VREG1:%[^ ]+]] = COPY %rsi
-; CHECK-DAG: [[VREG2:%[^ ]+]] = COPY %rdi
+; CHECK-DAG: [[VREG1:%[^ ]+]]:gr64 = COPY %rsi
+; CHECK-DAG: [[VREG2:%[^ ]+]]:gr64 = COPY %rdi
; CHECK: SUB64rr [[VREG2]], [[VREG1]]
; CHECK-NEXT: JNE_1 {{.*}}, debug-location [[DLOC]]{{$}}
-; CHECK: [[VREG3:%[^ ]+]] = PHI [[VREG2]]
-; CHECK: [[VREG4:%[^ ]+]] = ADD64ri8 [[VREG3]], 4
+; CHECK: [[VREG3:%[^ ]+]]:gr64 = PHI [[VREG2]]
+; CHECK: [[VREG4:%[^ ]+]]:gr64 = ADD64ri8 [[VREG3]], 4
; CHECK: SUB64rr [[VREG1]], [[VREG4]]
; CHECK-NEXT: JNE_1 {{.*}}, debug-location [[DLOC]]{{$}}
; CHECK-NEXT: JMP_1 {{.*}}, debug-location [[DLOC]]{{$}}
Modified: llvm/trunk/test/CodeGen/X86/xor-combine-debugloc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/xor-combine-debugloc.ll?rev=316479&r1=316478&r2=316479&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/xor-combine-debugloc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/xor-combine-debugloc.ll Tue Oct 24 11:04:54 2017
@@ -4,11 +4,11 @@
; that implictly defines %eflags has a same debug location with the icmp
; instruction, and the branch instructions have a same debug location with the
; br instruction.
-;
+;
; CHECK: [[DLOC1:![0-9]+]] = !DILocation(line: 5, column: 9, scope: !{{[0-9]+}})
; CHECK: [[DLOC2:![0-9]+]] = !DILocation(line: 5, column: 7, scope: !{{[0-9]+}})
-; CHECK-DAG: [[VREG1:%[^ ]+]] = COPY %esi
-; CHECK-DAG: [[VREG2:%[^ ]+]] = COPY %edi
+; CHECK-DAG: [[VREG1:%[^ ]+]]:gr32 = COPY %esi
+; CHECK-DAG: [[VREG2:%[^ ]+]]:gr32 = COPY %edi
; CHECK: SUB32rr [[VREG2]], [[VREG1]], implicit-def %eflags, debug-location [[DLOC1]]
; CHECK-NEXT: JE_1{{.*}} implicit %eflags, debug-location [[DLOC2]]
; CHECK-NEXT: JMP_1{{.*}} debug-location [[DLOC2]]
@@ -36,8 +36,8 @@ return:
ret i32 %retval.0, !dbg !21
}
-declare i32 @bar(...)
-declare i32 @baz(...)
+declare i32 @bar(...)
+declare i32 @baz(...)
; Function Attrs: nounwind readnone
declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
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