[PATCH] D36104: [AArch64] Coalesce Copy Zero during instruction selection

[Geoff Berry via Phabricator via llvm-commits]

gberry added a comment.

This looks pretty good to me (with one minor comment), but someone else should probably approve it.



================
Comment at: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:2809
+    SDValue New;
+    if (Node->getValueType(Node->getNumValues() - 1) == MVT::Glue)
+      New =
----------------
I think you can get rid of this if/else by re-writing as:

```
SDValue New = CurDAG->getNode(ISD::CopyToReg, SDLoc(Node), Node->getVTList(), makeArrayRef(Ops, NumOperands));
```


Repository:
  rL LLVM

https://reviews.llvm.org/D36104