[PATCH] D39051: [X86][F16C] Update instruction scheduling on btver2

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon accepted this revision.
RKSimon added a comment.
This revision is now accepted and ready to land.

In https://reviews.llvm.org/D39051#904742, @avt77 wrote:

> I'm not shure about WriteCVT3St lattency: is it really 3?


Stores are tricky as we can't easily model the time until the value is written out to memory - best we can do is just the cycles for the conversion, and it then disappears into the memory queue. It means that spill/reload round trips can't be easily modelled but then we don't handle STLF timings either.

LGTM with one minor.



================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:438
+def WriteCVT3Ld: SchedWriteRes<[JFPU1, JLAGU]> {
+  let Latency = 3;
+  let ResourceCycles = [1, 1];
----------------
This should be Latency = 8


https://reviews.llvm.org/D39051