[llvm] r316363 - [Hexagon] Add extra pattern for S4_addaddi

Krzysztof Parzyszek via llvm-commits llvm-commits at lists.llvm.org
Mon Oct 23 12:07:50 PDT 2017


Author: kparzysz
Date: Mon Oct 23 12:07:50 2017
New Revision: 316363

URL: http://llvm.org/viewvc/llvm-project?rev=316363&view=rev
Log:
[Hexagon] Add extra pattern for S4_addaddi

One combination was missing: add(add(x,y),c).

Added:
    llvm/trunk/test/CodeGen/Hexagon/addaddi.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td

Modified: llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td?rev=316363&r1=316362&r2=316363&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td Mon Oct 23 12:07:50 2017
@@ -1310,6 +1310,8 @@ def: AccRRR_pat<M4_xor_andn,  Xor, Su<No
 let AddedComplexity = 30 in {
   def: Pat<(add I32:$Rs, (Su<Add> I32:$Ru, anyimm:$s6)),
            (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>;
+  def: Pat<(add anyimm:$s6, (Su<Add> I32:$Rs, I32:$Ru)),
+           (S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>;
   def: Pat<(add I32:$Rs, (Su<Sub> anyimm:$s6, I32:$Ru)),
            (S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>;
   def: Pat<(sub (Su<Add> I32:$Rs, anyimm:$s6), I32:$Ru),

Added: llvm/trunk/test/CodeGen/Hexagon/addaddi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/addaddi.ll?rev=316363&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/addaddi.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/addaddi.ll Mon Oct 23 12:07:50 2017
@@ -0,0 +1,13 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; Check for S4_addaddi:
+; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}},add(r{{[0-9]+}},#2))
+
+define i32 @fred(i32 %a0, i32 %a1, i32* nocapture %a2) #0 {
+b3:
+  %v4 = add nsw i32 %a0, 2
+  %v5 = add nsw i32 %v4, %a1
+  store i32 %v5, i32* %a2, align 4
+  ret i32 undef
+}
+
+attributes #0 = { nounwind }




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