[PATCH] D38949: AMDGPU: Merge S_BUFFER_LOAD_DWORD_IMM into x2, x4

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle accepted this revision.
nhaehnle added a comment.
This revision is now accepted and ready to land.

One comment inline, apart from that LGTM. I imagine some of those additional spills could be improved with better register allocation, and that's a bullet someone has to bite eventually, but not now.



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Comment at: lib/Target/AMDGPU/AMDGPUSubtarget.h:326-328
+    // Only use the "x1" variants on GFX9 or don't use the buffer variants.
+    // TODO: There is one future GFX9 chip that doesn't have this bug.
+    return getGeneration() != GFX9;
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Could you add an explanation of what the bug is in the comment? (I think it may be the page-crossing bug that I vaguely remember but don't find the reference to right now, in which case we could still consider merging stores that are properly aligned in a future patch.)


https://reviews.llvm.org/D38949