[PATCH] D38915: AMDGPU: Fold immediate offset into BUFFER_LOAD_DWORD lowered from SMEM

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle added a comment.

Some small comments inline. More generally, I think stuff like this belongs in a MIR-level InstCombine pass. We just don't have the infrastructure for that yet, and this patch is a nice improvement in the meantime.



================
Comment at: lib/Target/AMDGPU/SIInstrInfo.cpp:3727-3732
+        if (Src) {
+          if (Src->isReg()) {
+            auto Mov = MRI.getUniqueVRegDef(Src->getReg());
+            if (Mov && Mov->getOpcode() == AMDGPU::S_MOV_B32)
+              Src = &Mov->getOperand(1);
+          }
----------------
Could you please reduce the nesting here a bit by wrapping this first part in `if (Src && Src->isReg())`?


================
Comment at: lib/Target/AMDGPU/SIInstrInfo.cpp:3742
+
+        if (Offset && isLegalMUBUFImmOffset(Offset))
+          VAddr = getNamedOperand(*Add, AMDGPU::OpName::src1);
----------------
Not a huge deal, but it seems a bit silly not to handle the case of an immediate `Offset == 0`. Such stuff should mostly be caught earlier, but who knows what kind of nonsense intermediate passes generate again.


https://reviews.llvm.org/D38915