[llvm] r316326 - [X86][AVX2] Regenerate AVX2 intrinsics tests on 32 + 64-bit targets
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 23 07:19:46 PDT 2017
Author: rksimon
Date: Mon Oct 23 07:19:46 2017
New Revision: 316326
URL: http://llvm.org/viewvc/llvm-project?rev=316326&view=rev
Log:
[X86][AVX2] Regenerate AVX2 intrinsics tests on 32 + 64-bit targets
Modified:
llvm/trunk/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll
llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll
llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll
Modified: llvm/trunk/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll?rev=316326&r1=316325&r2=316326&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll Mon Oct 23 07:19:46 2017
@@ -1,19 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=X32
-; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=X64
+; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=X86
+; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=X64
; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/avx2-builtins.c
define <4 x i64> @test_mm256_abs_epi8(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_abs_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpabsb %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_abs_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpabsb %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_abs_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpabsb %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg = bitcast <4 x i64> %a0 to <32 x i8>
%sub = sub <32 x i8> zeroinitializer, %arg
%cmp = icmp sgt <32 x i8> %arg, zeroinitializer
@@ -24,15 +19,10 @@ define <4 x i64> @test_mm256_abs_epi8(<4
declare <32 x i8> @llvm.x86.avx2.pabs.b(<32 x i8>) nounwind readnone
define <4 x i64> @test_mm256_abs_epi16(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_abs_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpabsw %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_abs_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpabsw %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_abs_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpabsw %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg = bitcast <4 x i64> %a0 to <16 x i16>
%sub = sub <16 x i16> zeroinitializer, %arg
%cmp = icmp sgt <16 x i16> %arg, zeroinitializer
@@ -43,15 +33,10 @@ define <4 x i64> @test_mm256_abs_epi16(<
declare <16 x i16> @llvm.x86.avx2.pabs.w(<16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_abs_epi32(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_abs_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpabsd %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_abs_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpabsd %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_abs_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpabsd %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg = bitcast <4 x i64> %a0 to <8 x i32>
%sub = sub <8 x i32> zeroinitializer, %arg
%cmp = icmp sgt <8 x i32> %arg, zeroinitializer
@@ -62,15 +47,10 @@ define <4 x i64> @test_mm256_abs_epi32(<
declare <8 x i32> @llvm.x86.avx2.pabs.d(<8 x i32>) nounwind readnone
define <4 x i64> @test_mm256_add_epi8(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_add_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpaddb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_add_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpaddb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_add_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpaddb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%res = add <32 x i8> %arg0, %arg1
@@ -79,15 +59,10 @@ define <4 x i64> @test_mm256_add_epi8(<4
}
define <4 x i64> @test_mm256_add_epi16(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_add_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpaddw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_add_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpaddw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_add_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpaddw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = add <16 x i16> %arg0, %arg1
@@ -96,15 +71,10 @@ define <4 x i64> @test_mm256_add_epi16(<
}
define <4 x i64> @test_mm256_add_epi32(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_add_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpaddd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_add_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpaddd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_add_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpaddd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = add <8 x i32> %arg0, %arg1
@@ -113,29 +83,19 @@ define <4 x i64> @test_mm256_add_epi32(<
}
define <4 x i64> @test_mm256_add_epi64(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_add_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpaddq %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_add_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpaddq %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_add_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpaddq %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = add <4 x i64> %a0, %a1
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_adds_epi8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_adds_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpaddsb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_adds_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpaddsb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_adds_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpaddsb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%res = call <32 x i8> @llvm.x86.avx2.padds.b(<32 x i8> %arg0, <32 x i8> %arg1)
@@ -145,15 +105,10 @@ define <4 x i64> @test_mm256_adds_epi8(<
declare <32 x i8> @llvm.x86.avx2.padds.b(<32 x i8>, <32 x i8>) nounwind readnone
define <4 x i64> @test_mm256_adds_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_adds_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpaddsw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_adds_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpaddsw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_adds_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpaddsw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.padds.w(<16 x i16> %arg0, <16 x i16> %arg1)
@@ -163,15 +118,10 @@ define <4 x i64> @test_mm256_adds_epi16(
declare <16 x i16> @llvm.x86.avx2.padds.w(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_adds_epu8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_adds_epu8:
-; X32: # BB#0:
-; X32-NEXT: vpaddusb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_adds_epu8:
-; X64: # BB#0:
-; X64-NEXT: vpaddusb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_adds_epu8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpaddusb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%res = call <32 x i8> @llvm.x86.avx2.paddus.b(<32 x i8> %arg0, <32 x i8> %arg1)
@@ -181,15 +131,10 @@ define <4 x i64> @test_mm256_adds_epu8(<
declare <32 x i8> @llvm.x86.avx2.paddus.b(<32 x i8>, <32 x i8>) nounwind readnone
define <4 x i64> @test_mm256_adds_epu16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_adds_epu16:
-; X32: # BB#0:
-; X32-NEXT: vpaddusw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_adds_epu16:
-; X64: # BB#0:
-; X64-NEXT: vpaddusw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_adds_epu16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpaddusw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.paddus.w(<16 x i16> %arg0, <16 x i16> %arg1)
@@ -199,15 +144,10 @@ define <4 x i64> @test_mm256_adds_epu16(
declare <16 x i16> @llvm.x86.avx2.paddus.w(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_alignr_epi8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_alignr_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm1[0,1],ymm0[18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm1[16,17]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_alignr_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm1[0,1],ymm0[18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm1[16,17]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_alignr_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm1[0,1],ymm0[18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm1[16,17]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%shuf = shufflevector <32 x i8> %arg0, <32 x i8> %arg1, <32 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49>
@@ -216,15 +156,10 @@ define <4 x i64> @test_mm256_alignr_epi8
}
define <4 x i64> @test2_mm256_alignr_epi8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test2_mm256_alignr_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm1[0],ymm0[17,18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm1[16]
-; X32-NEXT: retl
-;
-; X64-LABEL: test2_mm256_alignr_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm1[0],ymm0[17,18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm1[16]
-; X64-NEXT: retq
+; CHECK-LABEL: test2_mm256_alignr_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpalignr {{.*#+}} ymm0 = ymm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm1[0],ymm0[17,18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm1[16]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%shuf = shufflevector <32 x i8> %arg0, <32 x i8> %arg1, <32 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48>
@@ -233,48 +168,31 @@ define <4 x i64> @test2_mm256_alignr_epi
}
define <4 x i64> @test_mm256_and_si256(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_and_si256:
-; X32: # BB#0:
-; X32-NEXT: vandps %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_and_si256:
-; X64: # BB#0:
-; X64-NEXT: vandps %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_and_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: vandps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = and <4 x i64> %a0, %a1
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_andnot_si256(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_andnot_si256:
-; X32: # BB#0:
-; X32-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
-; X32-NEXT: vpxor %ymm2, %ymm0, %ymm0
-; X32-NEXT: vpand %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_andnot_si256:
-; X64: # BB#0:
-; X64-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
-; X64-NEXT: vpxor %ymm2, %ymm0, %ymm0
-; X64-NEXT: vpand %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_andnot_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; CHECK-NEXT: vpxor %ymm2, %ymm0, %ymm0
+; CHECK-NEXT: vpand %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%not = xor <4 x i64> %a0, <i64 -1, i64 -1, i64 -1, i64 -1>
%res = and <4 x i64> %not, %a1
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_avg_epu8(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_avg_epu8:
-; X32: # BB#0:
-; X32-NEXT: vpavgb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_avg_epu8:
-; X64: # BB#0:
-; X64-NEXT: vpavgb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_avg_epu8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpavgb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%zext0 = zext <32 x i8> %arg0 to <32 x i16>
@@ -288,15 +206,10 @@ define <4 x i64> @test_mm256_avg_epu8(<4
}
define <4 x i64> @test_mm256_avg_epu16(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_avg_epu16:
-; X32: # BB#0:
-; X32-NEXT: vpavgw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_avg_epu16:
-; X64: # BB#0:
-; X64-NEXT: vpavgw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_avg_epu16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpavgw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%zext0 = zext <16 x i16> %arg0 to <16 x i32>
@@ -310,15 +223,10 @@ define <4 x i64> @test_mm256_avg_epu16(<
}
define <4 x i64> @test_mm256_blend_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_blend_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7,8],ymm1[9],ymm0[10,11,12,13,14,15]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_blend_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7,8],ymm1[9],ymm0[10,11,12,13,14,15]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_blend_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7,8],ymm1[9],ymm0[10,11,12,13,14,15]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%shuf = shufflevector <16 x i16> %arg0, <16 x i16> %arg1, <16 x i32> <i32 0, i32 17, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 25, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -327,15 +235,10 @@ define <4 x i64> @test_mm256_blend_epi16
}
define <2 x i64> @test_mm_blend_epi32(<2 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_blend_epi32:
-; X32: # BB#0:
-; X32-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_blend_epi32:
-; X64: # BB#0:
-; X64-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_blend_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <4 x i32>
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%shuf = shufflevector <4 x i32> %arg0, <4 x i32> %arg1, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
@@ -344,15 +247,10 @@ define <2 x i64> @test_mm_blend_epi32(<2
}
define <4 x i64> @test_mm256_blend_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_blend_epi32:
-; X32: # BB#0:
-; X32-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4,5],ymm0[6,7]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_blend_epi32:
-; X64: # BB#0:
-; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4,5],ymm0[6,7]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_blend_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4,5],ymm0[6,7]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%shuf = shufflevector <8 x i32> %arg0, <8 x i32> %arg1, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 13, i32 6, i32 7>
@@ -361,15 +259,10 @@ define <4 x i64> @test_mm256_blend_epi32
}
define <4 x i64> @test_mm256_blendv_epi8(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2) {
-; X32-LABEL: test_mm256_blendv_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_blendv_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_blendv_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%arg2 = bitcast <4 x i64> %a2 to <32 x i8>
@@ -380,15 +273,10 @@ define <4 x i64> @test_mm256_blendv_epi8
declare <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8>, <32 x i8>, <32 x i8>) nounwind readnone
define <2 x i64> @test_mm_broadcastb_epi8(<2 x i64> %a0) {
-; X32-LABEL: test_mm_broadcastb_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpbroadcastb %xmm0, %xmm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_broadcastb_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpbroadcastb %xmm0, %xmm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_broadcastb_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpbroadcastb %xmm0, %xmm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%shuf = shufflevector <16 x i8> %arg0, <16 x i8> undef, <16 x i32> zeroinitializer
%res = bitcast <16 x i8> %shuf to <2 x i64>
@@ -396,15 +284,10 @@ define <2 x i64> @test_mm_broadcastb_epi
}
define <4 x i64> @test_mm256_broadcastb_epi8(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_broadcastb_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpbroadcastb %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_broadcastb_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpbroadcastb %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_broadcastb_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpbroadcastb %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%shuf = shufflevector <32 x i8> %arg0, <32 x i8> undef, <32 x i32> zeroinitializer
%res = bitcast <32 x i8> %shuf to <4 x i64>
@@ -412,15 +295,10 @@ define <4 x i64> @test_mm256_broadcastb_
}
define <2 x i64> @test_mm_broadcastd_epi32(<2 x i64> %a0) {
-; X32-LABEL: test_mm_broadcastd_epi32:
-; X32: # BB#0:
-; X32-NEXT: vbroadcastss %xmm0, %xmm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_broadcastd_epi32:
-; X64: # BB#0:
-; X64-NEXT: vbroadcastss %xmm0, %xmm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_broadcastd_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vbroadcastss %xmm0, %xmm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <4 x i32>
%shuf = shufflevector <4 x i32> %arg0, <4 x i32> undef, <4 x i32> zeroinitializer
%res = bitcast <4 x i32> %shuf to <2 x i64>
@@ -428,15 +306,10 @@ define <2 x i64> @test_mm_broadcastd_epi
}
define <4 x i64> @test_mm256_broadcastd_epi32(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_broadcastd_epi32:
-; X32: # BB#0:
-; X32-NEXT: vbroadcastss %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_broadcastd_epi32:
-; X64: # BB#0:
-; X64-NEXT: vbroadcastss %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_broadcastd_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vbroadcastss %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%shuf = shufflevector <8 x i32> %arg0, <8 x i32> undef, <8 x i32> zeroinitializer
%res = bitcast <8 x i32> %shuf to <4 x i64>
@@ -444,131 +317,90 @@ define <4 x i64> @test_mm256_broadcastd_
}
define <2 x i64> @test_mm_broadcastq_epi64(<2 x i64> %a0) {
-; X32-LABEL: test_mm_broadcastq_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpbroadcastq %xmm0, %xmm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_broadcastq_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpbroadcastq %xmm0, %xmm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_broadcastq_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpbroadcastq %xmm0, %xmm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <2 x i64> %a0, <2 x i64> undef, <2 x i32> zeroinitializer
ret <2 x i64> %res
}
define <4 x i64> @test_mm256_broadcastq_epi64(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_broadcastq_epi64:
-; X32: # BB#0:
-; X32-NEXT: vbroadcastsd %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_broadcastq_epi64:
-; X64: # BB#0:
-; X64-NEXT: vbroadcastsd %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_broadcastq_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> zeroinitializer
ret <4 x i64> %res
}
define <2 x double> @test_mm_broadcastsd_pd(<2 x double> %a0) {
-; X32-LABEL: test_mm_broadcastsd_pd:
-; X32: # BB#0:
-; X32-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_broadcastsd_pd:
-; X64: # BB#0:
-; X64-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_broadcastsd_pd:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <2 x double> %a0, <2 x double> undef, <2 x i32> zeroinitializer
ret <2 x double> %res
}
define <4 x double> @test_mm256_broadcastsd_pd(<4 x double> %a0) {
-; X32-LABEL: test_mm256_broadcastsd_pd:
-; X32: # BB#0:
-; X32-NEXT: vbroadcastsd %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_broadcastsd_pd:
-; X64: # BB#0:
-; X64-NEXT: vbroadcastsd %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_broadcastsd_pd:
+; CHECK: # BB#0:
+; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <4 x double> %a0, <4 x double> undef, <4 x i32> zeroinitializer
ret <4 x double> %res
}
define <4 x i64> @test_mm256_broadcastsi128_si256(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_broadcastsi128_si256:
-; X32: # BB#0:
-; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
-; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_broadcastsi128_si256:
-; X64: # BB#0:
-; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
-; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_broadcastsi128_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
+; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <2 x i64> %a0, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_broadcastsi128_si256_mem(<2 x i64>* %p0) {
-; X32-LABEL: test_mm256_broadcastsi128_si256_mem:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_broadcastsi128_si256_mem:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_broadcastsi128_si256_mem:
; X64: # BB#0:
; X64-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%a0 = load <2 x i64>, <2 x i64>* %p0
%res = shufflevector <2 x i64> %a0, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
ret <4 x i64> %res
}
define <4 x float> @test_mm_broadcastss_ps(<4 x float> %a0) {
-; X32-LABEL: test_mm_broadcastss_ps:
-; X32: # BB#0:
-; X32-NEXT: vbroadcastss %xmm0, %xmm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_broadcastss_ps:
-; X64: # BB#0:
-; X64-NEXT: vbroadcastss %xmm0, %xmm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_broadcastss_ps:
+; CHECK: # BB#0:
+; CHECK-NEXT: vbroadcastss %xmm0, %xmm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <4 x float> %a0, <4 x float> undef, <4 x i32> zeroinitializer
ret <4 x float> %res
}
define <8 x float> @test_mm256_broadcastss_ps(<8 x float> %a0) {
-; X32-LABEL: test_mm256_broadcastss_ps:
-; X32: # BB#0:
-; X32-NEXT: vbroadcastss %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_broadcastss_ps:
-; X64: # BB#0:
-; X64-NEXT: vbroadcastss %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_broadcastss_ps:
+; CHECK: # BB#0:
+; CHECK-NEXT: vbroadcastss %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <8 x float> %a0, <8 x float> undef, <8 x i32> zeroinitializer
ret <8 x float> %res
}
define <2 x i64> @test_mm_broadcastw_epi16(<2 x i64> %a0) {
-; X32-LABEL: test_mm_broadcastw_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpbroadcastw %xmm0, %xmm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_broadcastw_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpbroadcastw %xmm0, %xmm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_broadcastw_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpbroadcastw %xmm0, %xmm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <8 x i16>
%shuf = shufflevector <8 x i16> %arg0, <8 x i16> undef, <8 x i32> zeroinitializer
%res = bitcast <8 x i16> %shuf to <2 x i64>
@@ -576,15 +408,10 @@ define <2 x i64> @test_mm_broadcastw_epi
}
define <4 x i64> @test_mm256_broadcastw_epi16(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_broadcastw_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpbroadcastw %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_broadcastw_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpbroadcastw %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_broadcastw_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpbroadcastw %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%shuf = shufflevector <16 x i16> %arg0, <16 x i16> undef, <16 x i32> zeroinitializer
%res = bitcast <16 x i16> %shuf to <4 x i64>
@@ -592,15 +419,10 @@ define <4 x i64> @test_mm256_broadcastw_
}
define <4 x i64> @test_mm256_bslli_epi128(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_bslli_epi128:
-; X32: # BB#0:
-; X32-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12],zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_bslli_epi128:
-; X64: # BB#0:
-; X64-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12],zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_bslli_epi128:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12],zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%shuf = shufflevector <32 x i8> zeroinitializer, <32 x i8> %arg0, <32 x i32> <i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60>
%res = bitcast <32 x i8> %shuf to <4 x i64>
@@ -608,15 +430,10 @@ define <4 x i64> @test_mm256_bslli_epi12
}
define <4 x i64> @test_mm256_bsrli_epi128(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_bsrli_epi128:
-; X32: # BB#0:
-; X32-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[3,4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,ymm0[19,20,21,22,23,24,25,26,27,28,29,30,31],zero,zero,zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_bsrli_epi128:
-; X64: # BB#0:
-; X64-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[3,4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,ymm0[19,20,21,22,23,24,25,26,27,28,29,30,31],zero,zero,zero
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_bsrli_epi128:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[3,4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,ymm0[19,20,21,22,23,24,25,26,27,28,29,30,31],zero,zero,zero
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%shuf = shufflevector <32 x i8> %arg0, <32 x i8> zeroinitializer, <32 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50>
%res = bitcast <32 x i8> %shuf to <4 x i64>
@@ -624,15 +441,10 @@ define <4 x i64> @test_mm256_bsrli_epi12
}
define <4 x i64> @test_mm256_cmpeq_epi8(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_cmpeq_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cmpeq_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cmpeq_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%cmp = icmp eq <32 x i8> %arg0, %arg1
@@ -642,15 +454,10 @@ define <4 x i64> @test_mm256_cmpeq_epi8(
}
define <4 x i64> @test_mm256_cmpeq_epi16(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_cmpeq_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cmpeq_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cmpeq_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%cmp = icmp eq <16 x i16> %arg0, %arg1
@@ -660,15 +467,10 @@ define <4 x i64> @test_mm256_cmpeq_epi16
}
define <4 x i64> @test_mm256_cmpeq_epi32(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_cmpeq_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpcmpeqd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cmpeq_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpcmpeqd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cmpeq_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpcmpeqd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%cmp = icmp eq <8 x i32> %arg0, %arg1
@@ -678,30 +480,20 @@ define <4 x i64> @test_mm256_cmpeq_epi32
}
define <4 x i64> @test_mm256_cmpeq_epi64(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_cmpeq_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cmpeq_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cmpeq_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%cmp = icmp eq <4 x i64> %a0, %a1
%res = sext <4 x i1> %cmp to <4 x i64>
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_cmpgt_epi8(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_cmpgt_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cmpgt_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cmpgt_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%cmp = icmp sgt <32 x i8> %arg0, %arg1
@@ -711,15 +503,10 @@ define <4 x i64> @test_mm256_cmpgt_epi8(
}
define <4 x i64> @test_mm256_cmpgt_epi16(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_cmpgt_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cmpgt_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cmpgt_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%cmp = icmp sgt <16 x i16> %arg0, %arg1
@@ -729,15 +516,10 @@ define <4 x i64> @test_mm256_cmpgt_epi16
}
define <4 x i64> @test_mm256_cmpgt_epi32(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_cmpgt_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cmpgt_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cmpgt_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%cmp = icmp sgt <8 x i32> %arg0, %arg1
@@ -747,30 +529,20 @@ define <4 x i64> @test_mm256_cmpgt_epi32
}
define <4 x i64> @test_mm256_cmpgt_epi64(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_cmpgt_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cmpgt_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cmpgt_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%cmp = icmp sgt <4 x i64> %a0, %a1
%res = sext <4 x i1> %cmp to <4 x i64>
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_cvtepi8_epi16(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepi8_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpmovsxbw %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepi8_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpmovsxbw %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepi8_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovsxbw %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%ext = sext <16 x i8> %arg0 to <16 x i16>
%res = bitcast <16 x i16> %ext to <4 x i64>
@@ -778,15 +550,10 @@ define <4 x i64> @test_mm256_cvtepi8_epi
}
define <4 x i64> @test_mm256_cvtepi8_epi32(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepi8_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpmovsxbd %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepi8_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpmovsxbd %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepi8_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovsxbd %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%shuf = shufflevector <16 x i8> %arg0, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%ext = sext <8 x i8> %shuf to <8 x i32>
@@ -795,15 +562,10 @@ define <4 x i64> @test_mm256_cvtepi8_epi
}
define <4 x i64> @test_mm256_cvtepi8_epi64(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepi8_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpmovsxbq %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepi8_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpmovsxbq %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepi8_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovsxbq %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%shuf = shufflevector <16 x i8> %arg0, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%ext = sext <4 x i8> %shuf to <4 x i64>
@@ -811,15 +573,10 @@ define <4 x i64> @test_mm256_cvtepi8_epi
}
define <4 x i64> @test_mm256_cvtepi16_epi32(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepi16_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpmovsxwd %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepi16_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpmovsxwd %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepi16_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovsxwd %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <8 x i16>
%ext = sext <8 x i16> %arg0 to <8 x i32>
%res = bitcast <8 x i32> %ext to <4 x i64>
@@ -827,15 +584,10 @@ define <4 x i64> @test_mm256_cvtepi16_ep
}
define <4 x i64> @test_mm256_cvtepi16_epi64(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepi16_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpmovsxwq %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepi16_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpmovsxwq %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepi16_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovsxwq %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <8 x i16>
%shuf = shufflevector <8 x i16> %arg0, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%ext = sext <4 x i16> %shuf to <4 x i64>
@@ -843,30 +595,20 @@ define <4 x i64> @test_mm256_cvtepi16_ep
}
define <4 x i64> @test_mm256_cvtepi32_epi64(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepi32_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpmovsxdq %xmm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepi32_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpmovsxdq %xmm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepi32_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovsxdq %xmm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <4 x i32>
%ext = sext <4 x i32> %arg0 to <4 x i64>
ret <4 x i64> %ext
}
define <4 x i64> @test_mm256_cvtepu8_epi16(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepu8_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepu8_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepu8_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%ext = zext <16 x i8> %arg0 to <16 x i16>
%res = bitcast <16 x i16> %ext to <4 x i64>
@@ -874,15 +616,10 @@ define <4 x i64> @test_mm256_cvtepu8_epi
}
define <4 x i64> @test_mm256_cvtepu8_epi32(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepu8_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepu8_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepu8_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%shuf = shufflevector <16 x i8> %arg0, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%ext = zext <8 x i8> %shuf to <8 x i32>
@@ -891,15 +628,10 @@ define <4 x i64> @test_mm256_cvtepu8_epi
}
define <4 x i64> @test_mm256_cvtepu8_epi64(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepu8_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpmovzxbq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepu8_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpmovzxbq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepu8_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovzxbq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <16 x i8>
%shuf = shufflevector <16 x i8> %arg0, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%ext = zext <4 x i8> %shuf to <4 x i64>
@@ -907,15 +639,10 @@ define <4 x i64> @test_mm256_cvtepu8_epi
}
define <4 x i64> @test_mm256_cvtepu16_epi32(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepu16_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepu16_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepu16_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <8 x i16>
%ext = zext <8 x i16> %arg0 to <8 x i32>
%res = bitcast <8 x i32> %ext to <4 x i64>
@@ -923,15 +650,10 @@ define <4 x i64> @test_mm256_cvtepu16_ep
}
define <4 x i64> @test_mm256_cvtepu16_epi64(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepu16_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpmovzxwq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepu16_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpmovzxwq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepu16_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovzxwq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <8 x i16>
%shuf = shufflevector <8 x i16> %arg0, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%ext = zext <4 x i16> %shuf to <4 x i64>
@@ -939,46 +661,30 @@ define <4 x i64> @test_mm256_cvtepu16_ep
}
define <4 x i64> @test_mm256_cvtepu32_epi64(<2 x i64> %a0) {
-; X32-LABEL: test_mm256_cvtepu32_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_cvtepu32_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_cvtepu32_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <4 x i32>
%ext = zext <4 x i32> %arg0 to <4 x i64>
ret <4 x i64> %ext
}
define <2 x i64> @test_mm256_extracti128_si256(<4 x i64> %a0) nounwind {
-; X32-LABEL: test_mm256_extracti128_si256:
-; X32: # BB#0:
-; X32-NEXT: vextractf128 $1, %ymm0, %xmm0
-; X32-NEXT: vzeroupper
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_extracti128_si256:
-; X64: # BB#0:
-; X64-NEXT: vextractf128 $1, %ymm0, %xmm0
-; X64-NEXT: vzeroupper
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_extracti128_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <4 x i64> %a0, <4 x i64> %a0, <2 x i32> <i32 2, i32 3>
ret <2 x i64> %res
}
define <4 x i64> @test_mm256_hadd_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_hadd_epi16:
-; X32: # BB#0:
-; X32-NEXT: vphaddw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_hadd_epi16:
-; X64: # BB#0:
-; X64-NEXT: vphaddw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_hadd_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vphaddw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16> %arg0, <16 x i16> %arg1)
@@ -988,15 +694,10 @@ define <4 x i64> @test_mm256_hadd_epi16(
declare <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_hadd_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_hadd_epi32:
-; X32: # BB#0:
-; X32-NEXT: vphaddd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_hadd_epi32:
-; X64: # BB#0:
-; X64-NEXT: vphaddd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_hadd_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vphaddd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = call <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32> %arg0, <8 x i32> %arg1)
@@ -1006,15 +707,10 @@ define <4 x i64> @test_mm256_hadd_epi32(
declare <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32>, <8 x i32>) nounwind readnone
define <4 x i64> @test_mm256_hadds_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_hadds_epi16:
-; X32: # BB#0:
-; X32-NEXT: vphaddsw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_hadds_epi16:
-; X64: # BB#0:
-; X64-NEXT: vphaddsw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_hadds_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vphaddsw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.phadd.sw(<16 x i16> %arg0, <16 x i16> %arg1)
@@ -1024,15 +720,10 @@ define <4 x i64> @test_mm256_hadds_epi16
declare <16 x i16> @llvm.x86.avx2.phadd.sw(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_hsub_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_hsub_epi16:
-; X32: # BB#0:
-; X32-NEXT: vphsubw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_hsub_epi16:
-; X64: # BB#0:
-; X64-NEXT: vphsubw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_hsub_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vphsubw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.phsub.w(<16 x i16> %arg0, <16 x i16> %arg1)
@@ -1042,15 +733,10 @@ define <4 x i64> @test_mm256_hsub_epi16(
declare <16 x i16> @llvm.x86.avx2.phsub.w(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_hsub_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_hsub_epi32:
-; X32: # BB#0:
-; X32-NEXT: vphsubd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_hsub_epi32:
-; X64: # BB#0:
-; X64-NEXT: vphsubd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_hsub_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vphsubd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = call <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32> %arg0, <8 x i32> %arg1)
@@ -1060,15 +746,10 @@ define <4 x i64> @test_mm256_hsub_epi32(
declare <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32>, <8 x i32>) nounwind readnone
define <4 x i64> @test_mm256_hsubs_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_hsubs_epi16:
-; X32: # BB#0:
-; X32-NEXT: vphsubsw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_hsubs_epi16:
-; X64: # BB#0:
-; X64-NEXT: vphsubsw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_hsubs_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vphsubsw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.phsub.sw(<16 x i16> %arg0, <16 x i16> %arg1)
@@ -1078,14 +759,14 @@ define <4 x i64> @test_mm256_hsubs_epi16
declare <16 x i16> @llvm.x86.avx2.phsub.sw(<16 x i16>, <16 x i16>) nounwind readnone
define <2 x i64> @test_mm_i32gather_epi32(i32 *%a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_i32gather_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; X32-NEXT: vpgatherdd %xmm2, (%eax,%xmm0,2), %xmm1
-; X32-NEXT: vmovdqa %xmm1, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_i32gather_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; X86-NEXT: vpgatherdd %xmm2, (%eax,%xmm0,2), %xmm1
+; X86-NEXT: vmovdqa %xmm1, %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_i32gather_epi32:
; X64: # BB#0:
@@ -1093,7 +774,7 @@ define <2 x i64> @test_mm_i32gather_epi3
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpgatherdd %xmm2, (%rdi,%xmm0,2), %xmm1
; X64-NEXT: vmovdqa %xmm1, %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i32 *%a0 to i8*
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%mask = bitcast <2 x i64> <i64 -1, i64 -1> to <4 x i32>
@@ -1104,16 +785,16 @@ define <2 x i64> @test_mm_i32gather_epi3
declare <4 x i32> @llvm.x86.avx2.gather.d.d(<4 x i32>, i8*, <4 x i32>, <4 x i32>, i8) nounwind readonly
define <2 x i64> @test_mm_mask_i32gather_epi32(<2 x i64> %a0, i32 *%a1, <2 x i64> %a2, <2 x i64> %a3) {
-; X32-LABEL: test_mm_mask_i32gather_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpgatherdd %xmm2, (%eax,%xmm1,2), %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_mask_i32gather_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpgatherdd %xmm2, (%eax,%xmm1,2), %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_mask_i32gather_epi32:
; X64: # BB#0:
; X64-NEXT: vpgatherdd %xmm2, (%rdi,%xmm1,2), %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <4 x i32>
%arg1 = bitcast i32 *%a1 to i8*
%arg2 = bitcast <2 x i64> %a2 to <4 x i32>
@@ -1124,14 +805,14 @@ define <2 x i64> @test_mm_mask_i32gather
}
define <4 x i64> @test_mm256_i32gather_epi32(i32 *%a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_i32gather_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
-; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; X32-NEXT: vpgatherdd %ymm2, (%eax,%ymm0,2), %ymm1
-; X32-NEXT: vmovdqa %ymm1, %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_i32gather_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; X86-NEXT: vpgatherdd %ymm2, (%eax,%ymm0,2), %ymm1
+; X86-NEXT: vmovdqa %ymm1, %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_i32gather_epi32:
; X64: # BB#0:
@@ -1139,7 +820,7 @@ define <4 x i64> @test_mm256_i32gather_e
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpgatherdd %ymm2, (%rdi,%ymm0,2), %ymm1
; X64-NEXT: vmovdqa %ymm1, %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i32 *%a0 to i8*
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%mask = bitcast <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1> to <8 x i32>
@@ -1150,16 +831,16 @@ define <4 x i64> @test_mm256_i32gather_e
declare <8 x i32> @llvm.x86.avx2.gather.d.d.256(<8 x i32>, i8*, <8 x i32>, <8 x i32>, i8) nounwind readonly
define <4 x i64> @test_mm256_mask_i32gather_epi32(<4 x i64> %a0, i32 *%a1, <4 x i64> %a2, <4 x i64> %a3) {
-; X32-LABEL: test_mm256_mask_i32gather_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpgatherdd %ymm2, (%eax,%ymm1,2), %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_mask_i32gather_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpgatherdd %ymm2, (%eax,%ymm1,2), %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_mask_i32gather_epi32:
; X64: # BB#0:
; X64-NEXT: vpgatherdd %ymm2, (%rdi,%ymm1,2), %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast i32 *%a1 to i8*
%arg2 = bitcast <4 x i64> %a2 to <8 x i32>
@@ -1170,14 +851,14 @@ define <4 x i64> @test_mm256_mask_i32gat
}
define <2 x i64> @test_mm_i32gather_epi64(i64 *%a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_i32gather_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; X32-NEXT: vpgatherdq %xmm2, (%eax,%xmm0,2), %xmm1
-; X32-NEXT: vmovdqa %xmm1, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_i32gather_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; X86-NEXT: vpgatherdq %xmm2, (%eax,%xmm0,2), %xmm1
+; X86-NEXT: vmovdqa %xmm1, %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_i32gather_epi64:
; X64: # BB#0:
@@ -1185,7 +866,7 @@ define <2 x i64> @test_mm_i32gather_epi6
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpgatherdq %xmm2, (%rdi,%xmm0,2), %xmm1
; X64-NEXT: vmovdqa %xmm1, %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i64 *%a0 to i8*
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%res = call <2 x i64> @llvm.x86.avx2.gather.d.q(<2 x i64> undef, i8* %arg0, <4 x i32> %arg1, <2 x i64> <i64 -1, i64 -1>, i8 2)
@@ -1194,16 +875,16 @@ define <2 x i64> @test_mm_i32gather_epi6
declare <2 x i64> @llvm.x86.avx2.gather.d.q(<2 x i64>, i8*, <4 x i32>, <2 x i64>, i8) nounwind readonly
define <2 x i64> @test_mm_mask_i32gather_epi64(<2 x i64> %a0, i64 *%a1, <2 x i64> %a2, <2 x i64> %a3) {
-; X32-LABEL: test_mm_mask_i32gather_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpgatherdq %xmm2, (%eax,%xmm1,2), %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_mask_i32gather_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpgatherdq %xmm2, (%eax,%xmm1,2), %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_mask_i32gather_epi64:
; X64: # BB#0:
; X64-NEXT: vpgatherdq %xmm2, (%rdi,%xmm1,2), %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast i64 *%a1 to i8*
%arg2 = bitcast <2 x i64> %a2 to <4 x i32>
%res = call <2 x i64> @llvm.x86.avx2.gather.d.q(<2 x i64> %a0, i8* %arg1, <4 x i32> %arg2, <2 x i64> %a3, i8 2)
@@ -1211,14 +892,14 @@ define <2 x i64> @test_mm_mask_i32gather
}
define <4 x i64> @test_mm256_i32gather_epi64(i64 *%a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm256_i32gather_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
-; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; X32-NEXT: vpgatherdq %ymm2, (%eax,%xmm0,2), %ymm1
-; X32-NEXT: vmovdqa %ymm1, %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_i32gather_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; X86-NEXT: vpgatherdq %ymm2, (%eax,%xmm0,2), %ymm1
+; X86-NEXT: vmovdqa %ymm1, %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_i32gather_epi64:
; X64: # BB#0:
@@ -1226,7 +907,7 @@ define <4 x i64> @test_mm256_i32gather_e
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpgatherdq %ymm2, (%rdi,%xmm0,2), %ymm1
; X64-NEXT: vmovdqa %ymm1, %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i64 *%a0 to i8*
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%res = call <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64> undef, i8* %arg0, <4 x i32> %arg1, <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, i8 2)
@@ -1235,16 +916,16 @@ define <4 x i64> @test_mm256_i32gather_e
declare <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64>, i8*, <4 x i32>, <4 x i64>, i8) nounwind readonly
define <4 x i64> @test_mm256_mask_i32gather_epi64(<4 x i64> %a0, i64 *%a1, <2 x i64> %a2, <4 x i64> %a3) {
-; X32-LABEL: test_mm256_mask_i32gather_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpgatherdq %ymm2, (%eax,%xmm1,2), %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_mask_i32gather_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpgatherdq %ymm2, (%eax,%xmm1,2), %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_mask_i32gather_epi64:
; X64: # BB#0:
; X64-NEXT: vpgatherdq %ymm2, (%rdi,%xmm1,2), %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast i64 *%a1 to i8*
%arg2 = bitcast <2 x i64> %a2 to <4 x i32>
%res = call <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64> %a0, i8* %arg1, <4 x i32> %arg2, <4 x i64> %a3, i8 2)
@@ -1252,14 +933,14 @@ define <4 x i64> @test_mm256_mask_i32gat
}
define <2 x double> @test_mm_i32gather_pd(double *%a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_i32gather_pd:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; X32-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; X32-NEXT: vgatherdpd %xmm2, (%eax,%xmm0,2), %xmm1
-; X32-NEXT: vmovapd %xmm1, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_i32gather_pd:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; X86-NEXT: vgatherdpd %xmm2, (%eax,%xmm0,2), %xmm1
+; X86-NEXT: vmovapd %xmm1, %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_i32gather_pd:
; X64: # BB#0:
@@ -1267,7 +948,7 @@ define <2 x double> @test_mm_i32gather_p
; X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X64-NEXT: vgatherdpd %xmm2, (%rdi,%xmm0,2), %xmm1
; X64-NEXT: vmovapd %xmm1, %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast double *%a0 to i8*
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%cmp = fcmp oeq <2 x double> zeroinitializer, zeroinitializer
@@ -1279,16 +960,16 @@ define <2 x double> @test_mm_i32gather_p
declare <2 x double> @llvm.x86.avx2.gather.d.pd(<2 x double>, i8*, <4 x i32>, <2 x double>, i8) nounwind readonly
define <2 x double> @test_mm_mask_i32gather_pd(<2 x double> %a0, double *%a1, <2 x i64> %a2, <2 x double> %a3) {
-; X32-LABEL: test_mm_mask_i32gather_pd:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vgatherdpd %xmm2, (%eax,%xmm1,2), %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_mask_i32gather_pd:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vgatherdpd %xmm2, (%eax,%xmm1,2), %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_mask_i32gather_pd:
; X64: # BB#0:
; X64-NEXT: vgatherdpd %xmm2, (%rdi,%xmm1,2), %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast double *%a1 to i8*
%arg2 = bitcast <2 x i64> %a2 to <4 x i32>
%res = call <2 x double> @llvm.x86.avx2.gather.d.pd(<2 x double> %a0, i8* %arg1, <4 x i32> %arg2, <2 x double> %a3, i8 2)
@@ -1296,14 +977,14 @@ define <2 x double> @test_mm_mask_i32gat
}
define <4 x double> @test_mm256_i32gather_pd(double *%a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm256_i32gather_pd:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; X32-NEXT: vcmpeqpd %ymm1, %ymm1, %ymm2
-; X32-NEXT: vgatherdpd %ymm2, (%eax,%xmm0,2), %ymm1
-; X32-NEXT: vmovapd %ymm1, %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_i32gather_pd:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; X86-NEXT: vcmpeqpd %ymm1, %ymm1, %ymm2
+; X86-NEXT: vgatherdpd %ymm2, (%eax,%xmm0,2), %ymm1
+; X86-NEXT: vmovapd %ymm1, %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_i32gather_pd:
; X64: # BB#0:
@@ -1311,7 +992,7 @@ define <4 x double> @test_mm256_i32gathe
; X64-NEXT: vcmpeqpd %ymm1, %ymm1, %ymm2
; X64-NEXT: vgatherdpd %ymm2, (%rdi,%xmm0,2), %ymm1
; X64-NEXT: vmovapd %ymm1, %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast double *%a0 to i8*
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%mask = call <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double> zeroinitializer, <4 x double> zeroinitializer, i8 0)
@@ -1321,16 +1002,16 @@ define <4 x double> @test_mm256_i32gathe
declare <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double>, i8*, <4 x i32>, <4 x double>, i8) nounwind readonly
define <4 x double> @test_mm256_mask_i32gather_pd(<4 x double> %a0, double *%a1, <2 x i64> %a2, <4 x double> %a3) {
-; X32-LABEL: test_mm256_mask_i32gather_pd:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vgatherdpd %ymm2, (%eax,%xmm1,2), %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_mask_i32gather_pd:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vgatherdpd %ymm2, (%eax,%xmm1,2), %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_mask_i32gather_pd:
; X64: # BB#0:
; X64-NEXT: vgatherdpd %ymm2, (%rdi,%xmm1,2), %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast double *%a1 to i8*
%arg2 = bitcast <2 x i64> %a2 to <4 x i32>
%res = call <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double> %a0, i8* %arg1, <4 x i32> %arg2, <4 x double> %a3, i8 2)
@@ -1338,14 +1019,14 @@ define <4 x double> @test_mm256_mask_i32
}
define <4 x float> @test_mm_i32gather_ps(float *%a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_i32gather_ps:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; X32-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; X32-NEXT: vgatherdps %xmm2, (%eax,%xmm0,2), %xmm1
-; X32-NEXT: vmovaps %xmm1, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_i32gather_ps:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; X86-NEXT: vgatherdps %xmm2, (%eax,%xmm0,2), %xmm1
+; X86-NEXT: vmovaps %xmm1, %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_i32gather_ps:
; X64: # BB#0:
@@ -1353,7 +1034,7 @@ define <4 x float> @test_mm_i32gather_ps
; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-NEXT: vgatherdps %xmm2, (%rdi,%xmm0,2), %xmm1
; X64-NEXT: vmovaps %xmm1, %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast float *%a0 to i8*
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%cmp = fcmp oeq <4 x float> zeroinitializer, zeroinitializer
@@ -1365,16 +1046,16 @@ define <4 x float> @test_mm_i32gather_ps
declare <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float>, i8*, <4 x i32>, <4 x float>, i8) nounwind readonly
define <4 x float> @test_mm_mask_i32gather_ps(<4 x float> %a0, float *%a1, <2 x i64> %a2, <4 x float> %a3) {
-; X32-LABEL: test_mm_mask_i32gather_ps:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vgatherdps %xmm2, (%eax,%xmm1,2), %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_mask_i32gather_ps:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vgatherdps %xmm2, (%eax,%xmm1,2), %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_mask_i32gather_ps:
; X64: # BB#0:
; X64-NEXT: vgatherdps %xmm2, (%rdi,%xmm1,2), %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast float *%a1 to i8*
%arg2 = bitcast <2 x i64> %a2 to <4 x i32>
%call = call <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float> %a0, i8* %arg1, <4 x i32> %arg2, <4 x float> %a3, i8 2)
@@ -1382,14 +1063,14 @@ define <4 x float> @test_mm_mask_i32gath
}
define <8 x float> @test_mm256_i32gather_ps(float *%a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_i32gather_ps:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; X32-NEXT: vcmpeqps %ymm1, %ymm1, %ymm2
-; X32-NEXT: vgatherdps %ymm2, (%eax,%ymm0,2), %ymm1
-; X32-NEXT: vmovaps %ymm1, %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_i32gather_ps:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; X86-NEXT: vcmpeqps %ymm1, %ymm1, %ymm2
+; X86-NEXT: vgatherdps %ymm2, (%eax,%ymm0,2), %ymm1
+; X86-NEXT: vmovaps %ymm1, %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_i32gather_ps:
; X64: # BB#0:
@@ -1397,7 +1078,7 @@ define <8 x float> @test_mm256_i32gather
; X64-NEXT: vcmpeqps %ymm1, %ymm1, %ymm2
; X64-NEXT: vgatherdps %ymm2, (%rdi,%ymm0,2), %ymm1
; X64-NEXT: vmovaps %ymm1, %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast float *%a0 to i8*
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%mask = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> zeroinitializer, <8 x float> zeroinitializer, i8 0)
@@ -1407,16 +1088,16 @@ define <8 x float> @test_mm256_i32gather
declare <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float>, i8*, <8 x i32>, <8 x float>, i8) nounwind readonly
define <8 x float> @test_mm256_mask_i32gather_ps(<8 x float> %a0, float *%a1, <4 x i64> %a2, <8 x float> %a3) {
-; X32-LABEL: test_mm256_mask_i32gather_ps:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vgatherdps %ymm2, (%eax,%ymm1,2), %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_mask_i32gather_ps:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vgatherdps %ymm2, (%eax,%ymm1,2), %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_mask_i32gather_ps:
; X64: # BB#0:
; X64-NEXT: vgatherdps %ymm2, (%rdi,%ymm1,2), %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast float *%a1 to i8*
%arg2 = bitcast <4 x i64> %a2 to <8 x i32>
%call = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> %a0, i8* %arg1, <8 x i32> %arg2, <8 x float> %a3, i8 2)
@@ -1424,14 +1105,14 @@ define <8 x float> @test_mm256_mask_i32g
}
define <2 x i64> @test_mm_i64gather_epi32(i32 *%a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_i64gather_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; X32-NEXT: vpgatherqd %xmm2, (%eax,%xmm0,2), %xmm1
-; X32-NEXT: vmovdqa %xmm1, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_i64gather_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; X86-NEXT: vpgatherqd %xmm2, (%eax,%xmm0,2), %xmm1
+; X86-NEXT: vmovdqa %xmm1, %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_i64gather_epi32:
; X64: # BB#0:
@@ -1439,7 +1120,7 @@ define <2 x i64> @test_mm_i64gather_epi3
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpgatherqd %xmm2, (%rdi,%xmm0,2), %xmm1
; X64-NEXT: vmovdqa %xmm1, %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i32 *%a0 to i8*
%mask = bitcast <2 x i64> <i64 -1, i64 -1> to <4 x i32>
%call = call <4 x i32> @llvm.x86.avx2.gather.q.d(<4 x i32> undef, i8* %arg0, <2 x i64> %a1, <4 x i32> %mask, i8 2)
@@ -1449,16 +1130,16 @@ define <2 x i64> @test_mm_i64gather_epi3
declare <4 x i32> @llvm.x86.avx2.gather.q.d(<4 x i32>, i8*, <2 x i64>, <4 x i32>, i8) nounwind readonly
define <2 x i64> @test_mm_mask_i64gather_epi32(<2 x i64> %a0, i32 *%a1, <2 x i64> %a2, <2 x i64> %a3) {
-; X32-LABEL: test_mm_mask_i64gather_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpgatherqd %xmm2, (%eax,%xmm1,2), %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_mask_i64gather_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpgatherqd %xmm2, (%eax,%xmm1,2), %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_mask_i64gather_epi32:
; X64: # BB#0:
; X64-NEXT: vpgatherqd %xmm2, (%rdi,%xmm1,2), %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <4 x i32>
%arg1 = bitcast i32 *%a1 to i8*
%arg3 = bitcast <2 x i64> %a3 to <4 x i32>
@@ -1468,15 +1149,15 @@ define <2 x i64> @test_mm_mask_i64gather
}
define <2 x i64> @test_mm256_i64gather_epi32(i32 *%a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_i64gather_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; X32-NEXT: vpgatherqd %xmm2, (%eax,%ymm0,2), %xmm1
-; X32-NEXT: vmovdqa %xmm1, %xmm0
-; X32-NEXT: vzeroupper
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_i64gather_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; X86-NEXT: vpgatherqd %xmm2, (%eax,%ymm0,2), %xmm1
+; X86-NEXT: vmovdqa %xmm1, %xmm0
+; X86-NEXT: vzeroupper
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_i64gather_epi32:
; X64: # BB#0:
@@ -1485,7 +1166,7 @@ define <2 x i64> @test_mm256_i64gather_e
; X64-NEXT: vpgatherqd %xmm2, (%rdi,%ymm0,2), %xmm1
; X64-NEXT: vmovdqa %xmm1, %xmm0
; X64-NEXT: vzeroupper
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i32 *%a0 to i8*
%mask = bitcast <2 x i64> <i64 -1, i64 -1> to <4 x i32>
%call = call <4 x i32> @llvm.x86.avx2.gather.q.d.256(<4 x i32> undef, i8* %arg0, <4 x i64> %a1, <4 x i32> %mask, i8 2)
@@ -1495,18 +1176,18 @@ define <2 x i64> @test_mm256_i64gather_e
declare <4 x i32> @llvm.x86.avx2.gather.q.d.256(<4 x i32>, i8*, <4 x i64>, <4 x i32>, i8) nounwind readonly
define <2 x i64> @test_mm256_mask_i64gather_epi32(<2 x i64> %a0, i32 *%a1, <4 x i64> %a2, <2 x i64> %a3) {
-; X32-LABEL: test_mm256_mask_i64gather_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpgatherqd %xmm2, (%eax,%ymm1,2), %xmm0
-; X32-NEXT: vzeroupper
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_mask_i64gather_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpgatherqd %xmm2, (%eax,%ymm1,2), %xmm0
+; X86-NEXT: vzeroupper
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_mask_i64gather_epi32:
; X64: # BB#0:
; X64-NEXT: vpgatherqd %xmm2, (%rdi,%ymm1,2), %xmm0
; X64-NEXT: vzeroupper
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <4 x i32>
%arg1 = bitcast i32 *%a1 to i8*
%arg3 = bitcast <2 x i64> %a3 to <4 x i32>
@@ -1516,14 +1197,14 @@ define <2 x i64> @test_mm256_mask_i64gat
}
define <2 x i64> @test_mm_i64gather_epi64(i64 *%a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_i64gather_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; X32-NEXT: vpgatherqq %xmm2, (%eax,%xmm0,2), %xmm1
-; X32-NEXT: vmovdqa %xmm1, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_i64gather_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; X86-NEXT: vpgatherqq %xmm2, (%eax,%xmm0,2), %xmm1
+; X86-NEXT: vmovdqa %xmm1, %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_i64gather_epi64:
; X64: # BB#0:
@@ -1531,7 +1212,7 @@ define <2 x i64> @test_mm_i64gather_epi6
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpgatherqq %xmm2, (%rdi,%xmm0,2), %xmm1
; X64-NEXT: vmovdqa %xmm1, %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i64 *%a0 to i8*
%call = call <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64> undef, i8* %arg0, <2 x i64> %a1, <2 x i64> <i64 -1, i64 -1>, i8 2)
ret <2 x i64> %call
@@ -1539,30 +1220,30 @@ define <2 x i64> @test_mm_i64gather_epi6
declare <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64>, i8*, <2 x i64>, <2 x i64>, i8) nounwind readonly
define <2 x i64> @test_mm_mask_i64gather_epi64(<2 x i64> %a0, i64 *%a1, <2 x i64> %a2, <2 x i64> %a3) {
-; X32-LABEL: test_mm_mask_i64gather_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpgatherqq %xmm2, (%eax,%xmm1,2), %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_mask_i64gather_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpgatherqq %xmm2, (%eax,%xmm1,2), %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_mask_i64gather_epi64:
; X64: # BB#0:
; X64-NEXT: vpgatherqq %xmm2, (%rdi,%xmm1,2), %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast i64 *%a1 to i8*
%call = call <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64> %a0, i8* %arg1, <2 x i64> %a2, <2 x i64> %a3, i8 2)
ret <2 x i64> %call
}
define <4 x i64> @test_mm256_i64gather_epi64(i64 *%a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_i64gather_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
-; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; X32-NEXT: vpgatherqq %ymm2, (%eax,%ymm0,2), %ymm1
-; X32-NEXT: vmovdqa %ymm1, %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_i64gather_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
+; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; X86-NEXT: vpgatherqq %ymm2, (%eax,%ymm0,2), %ymm1
+; X86-NEXT: vmovdqa %ymm1, %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_i64gather_epi64:
; X64: # BB#0:
@@ -1570,7 +1251,7 @@ define <4 x i64> @test_mm256_i64gather_e
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpgatherqq %ymm2, (%rdi,%ymm0,2), %ymm1
; X64-NEXT: vmovdqa %ymm1, %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i64 *%a0 to i8*
%call = call <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64> undef, i8* %arg0, <4 x i64> %a1, <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, i8 2)
ret <4 x i64> %call
@@ -1578,30 +1259,30 @@ define <4 x i64> @test_mm256_i64gather_e
declare <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64>, i8*, <4 x i64>, <4 x i64>, i8) nounwind readonly
define <4 x i64> @test_mm256_mask_i64gather_epi64(<4 x i64> %a0, i64 *%a1, <4 x i64> %a2, <4 x i64> %a3) {
-; X32-LABEL: test_mm256_mask_i64gather_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpgatherqq %ymm2, (%eax,%ymm1,2), %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_mask_i64gather_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpgatherqq %ymm2, (%eax,%ymm1,2), %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_mask_i64gather_epi64:
; X64: # BB#0:
; X64-NEXT: vpgatherqq %ymm2, (%rdi,%ymm1,2), %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast i64 *%a1 to i8*
%call = call <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64> %a0, i8* %arg1, <4 x i64> %a2, <4 x i64> %a3, i8 2)
ret <4 x i64> %call
}
define <2 x double> @test_mm_i64gather_pd(double *%a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_i64gather_pd:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; X32-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; X32-NEXT: vgatherqpd %xmm2, (%eax,%xmm0,2), %xmm1
-; X32-NEXT: vmovapd %xmm1, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_i64gather_pd:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; X86-NEXT: vgatherqpd %xmm2, (%eax,%xmm0,2), %xmm1
+; X86-NEXT: vmovapd %xmm1, %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_i64gather_pd:
; X64: # BB#0:
@@ -1609,7 +1290,7 @@ define <2 x double> @test_mm_i64gather_p
; X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; X64-NEXT: vgatherqpd %xmm2, (%rdi,%xmm0,2), %xmm1
; X64-NEXT: vmovapd %xmm1, %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast double *%a0 to i8*
%cmp = fcmp oeq <2 x double> zeroinitializer, zeroinitializer
%sext = sext <2 x i1> %cmp to <2 x i64>
@@ -1620,30 +1301,30 @@ define <2 x double> @test_mm_i64gather_p
declare <2 x double> @llvm.x86.avx2.gather.q.pd(<2 x double>, i8*, <2 x i64>, <2 x double>, i8) nounwind readonly
define <2 x double> @test_mm_mask_i64gather_pd(<2 x double> %a0, double *%a1, <2 x i64> %a2, <2 x double> %a3) {
-; X32-LABEL: test_mm_mask_i64gather_pd:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vgatherqpd %xmm2, (%eax,%xmm1,2), %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_mask_i64gather_pd:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vgatherqpd %xmm2, (%eax,%xmm1,2), %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_mask_i64gather_pd:
; X64: # BB#0:
; X64-NEXT: vgatherqpd %xmm2, (%rdi,%xmm1,2), %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast double *%a1 to i8*
%call = call <2 x double> @llvm.x86.avx2.gather.q.pd(<2 x double> %a0, i8* %arg1, <2 x i64> %a2, <2 x double> %a3, i8 2)
ret <2 x double> %call
}
define <4 x double> @test_mm256_i64gather_pd(double *%a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_i64gather_pd:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; X32-NEXT: vcmpeqpd %ymm1, %ymm1, %ymm2
-; X32-NEXT: vgatherqpd %ymm2, (%eax,%ymm0,2), %ymm1
-; X32-NEXT: vmovapd %ymm1, %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_i64gather_pd:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; X86-NEXT: vcmpeqpd %ymm1, %ymm1, %ymm2
+; X86-NEXT: vgatherqpd %ymm2, (%eax,%ymm0,2), %ymm1
+; X86-NEXT: vmovapd %ymm1, %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_i64gather_pd:
; X64: # BB#0:
@@ -1651,7 +1332,7 @@ define <4 x double> @test_mm256_i64gathe
; X64-NEXT: vcmpeqpd %ymm1, %ymm1, %ymm2
; X64-NEXT: vgatherqpd %ymm2, (%rdi,%ymm0,2), %ymm1
; X64-NEXT: vmovapd %ymm1, %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast double *%a0 to i8*
%mask = call <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double> zeroinitializer, <4 x double> zeroinitializer, i8 0)
%call = call <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double> undef, i8* %arg0, <4 x i64> %a1, <4 x double> %mask, i8 2)
@@ -1660,30 +1341,30 @@ define <4 x double> @test_mm256_i64gathe
declare <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double>, i8*, <4 x i64>, <4 x double>, i8) nounwind readonly
define <4 x double> @test_mm256_mask_i64gather_pd(<4 x double> %a0, i64 *%a1, <4 x i64> %a2, <4 x double> %a3) {
-; X32-LABEL: test_mm256_mask_i64gather_pd:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vgatherqpd %ymm2, (%eax,%ymm1,2), %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_mask_i64gather_pd:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vgatherqpd %ymm2, (%eax,%ymm1,2), %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_mask_i64gather_pd:
; X64: # BB#0:
; X64-NEXT: vgatherqpd %ymm2, (%rdi,%ymm1,2), %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast i64 *%a1 to i8*
%call = call <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double> %a0, i8* %arg1, <4 x i64> %a2, <4 x double> %a3, i8 2)
ret <4 x double> %call
}
define <4 x float> @test_mm_i64gather_ps(float *%a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_i64gather_ps:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; X32-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; X32-NEXT: vgatherqps %xmm2, (%eax,%xmm0,2), %xmm1
-; X32-NEXT: vmovaps %xmm1, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_i64gather_ps:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; X86-NEXT: vgatherqps %xmm2, (%eax,%xmm0,2), %xmm1
+; X86-NEXT: vmovaps %xmm1, %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_i64gather_ps:
; X64: # BB#0:
@@ -1691,7 +1372,7 @@ define <4 x float> @test_mm_i64gather_ps
; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-NEXT: vgatherqps %xmm2, (%rdi,%xmm0,2), %xmm1
; X64-NEXT: vmovaps %xmm1, %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast float *%a0 to i8*
%cmp = fcmp oeq <4 x float> zeroinitializer, zeroinitializer
%sext = sext <4 x i1> %cmp to <4 x i32>
@@ -1702,31 +1383,31 @@ define <4 x float> @test_mm_i64gather_ps
declare <4 x float> @llvm.x86.avx2.gather.q.ps(<4 x float>, i8*, <2 x i64>, <4 x float>, i8) nounwind readonly
define <4 x float> @test_mm_mask_i64gather_ps(<4 x float> %a0, float *%a1, <2 x i64> %a2, <4 x float> %a3) {
-; X32-LABEL: test_mm_mask_i64gather_ps:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vgatherqps %xmm2, (%eax,%xmm1,2), %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_mask_i64gather_ps:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vgatherqps %xmm2, (%eax,%xmm1,2), %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_mask_i64gather_ps:
; X64: # BB#0:
; X64-NEXT: vgatherqps %xmm2, (%rdi,%xmm1,2), %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast float *%a1 to i8*
%call = call <4 x float> @llvm.x86.avx2.gather.q.ps(<4 x float> %a0, i8* %arg1, <2 x i64> %a2, <4 x float> %a3, i8 2)
ret <4 x float> %call
}
define <4 x float> @test_mm256_i64gather_ps(float *%a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_i64gather_ps:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; X32-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; X32-NEXT: vgatherqps %xmm2, (%eax,%ymm0,2), %xmm1
-; X32-NEXT: vmovaps %xmm1, %xmm0
-; X32-NEXT: vzeroupper
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_i64gather_ps:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; X86-NEXT: vgatherqps %xmm2, (%eax,%ymm0,2), %xmm1
+; X86-NEXT: vmovaps %xmm1, %xmm0
+; X86-NEXT: vzeroupper
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_i64gather_ps:
; X64: # BB#0:
@@ -1735,7 +1416,7 @@ define <4 x float> @test_mm256_i64gather
; X64-NEXT: vgatherqps %xmm2, (%rdi,%ymm0,2), %xmm1
; X64-NEXT: vmovaps %xmm1, %xmm0
; X64-NEXT: vzeroupper
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast float *%a0 to i8*
%cmp = fcmp oeq <4 x float> zeroinitializer, zeroinitializer
%sext = sext <4 x i1> %cmp to <4 x i32>
@@ -1746,65 +1427,49 @@ define <4 x float> @test_mm256_i64gather
declare <4 x float> @llvm.x86.avx2.gather.q.ps.256(<4 x float>, i8*, <4 x i64>, <4 x float>, i8) nounwind readonly
define <4 x float> @test_mm256_mask_i64gather_ps(<4 x float> %a0, float *%a1, <4 x i64> %a2, <4 x float> %a3) {
-; X32-LABEL: test_mm256_mask_i64gather_ps:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vgatherqps %xmm2, (%eax,%ymm1,2), %xmm0
-; X32-NEXT: vzeroupper
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_mask_i64gather_ps:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vgatherqps %xmm2, (%eax,%ymm1,2), %xmm0
+; X86-NEXT: vzeroupper
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_mask_i64gather_ps:
; X64: # BB#0:
; X64-NEXT: vgatherqps %xmm2, (%rdi,%ymm1,2), %xmm0
; X64-NEXT: vzeroupper
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg1 = bitcast float *%a1 to i8*
%call = call <4 x float> @llvm.x86.avx2.gather.q.ps.256(<4 x float> %a0, i8* %arg1, <4 x i64> %a2, <4 x float> %a3, i8 2)
ret <4 x float> %call
}
define <4 x i64> @test0_mm256_inserti128_si256(<4 x i64> %a0, <2 x i64> %a1) nounwind {
-; X32-LABEL: test0_mm256_inserti128_si256:
-; X32: # BB#0:
-; X32-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
-; X32-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
-; X32-NEXT: retl
-;
-; X64-LABEL: test0_mm256_inserti128_si256:
-; X64: # BB#0:
-; X64-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
-; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
-; X64-NEXT: retq
+; CHECK-LABEL: test0_mm256_inserti128_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def>
+; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
+; CHECK-NEXT: ret{{[l|q]}}
%ext = shufflevector <2 x i64> %a1, <2 x i64> %a1, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%res = shufflevector <4 x i64> %a0, <4 x i64> %ext, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
ret <4 x i64> %res
}
define <4 x i64> @test1_mm256_inserti128_si256(<4 x i64> %a0, <2 x i64> %a1) nounwind {
-; X32-LABEL: test1_mm256_inserti128_si256:
-; X32: # BB#0:
-; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test1_mm256_inserti128_si256:
-; X64: # BB#0:
-; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test1_mm256_inserti128_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%ext = shufflevector <2 x i64> %a1, <2 x i64> %a1, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%res = shufflevector <4 x i64> %a0, <4 x i64> %ext, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_madd_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_madd_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_madd_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_madd_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %arg0, <16 x i16> %arg1)
@@ -1814,15 +1479,10 @@ define <4 x i64> @test_mm256_madd_epi16(
declare <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_maddubs_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_maddubs_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_maddubs_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_maddubs_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%res = call <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8> %arg0, <32 x i8> %arg1)
@@ -1832,16 +1492,16 @@ define <4 x i64> @test_mm256_maddubs_epi
declare <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8>, <32 x i8>) nounwind readnone
define <2 x i64> @test_mm_maskload_epi32(i32* %a0, <2 x i64> %a1) nounwind {
-; X32-LABEL: test_mm_maskload_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmaskmovd (%eax), %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_maskload_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpmaskmovd (%eax), %xmm0, %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_maskload_epi32:
; X64: # BB#0:
; X64-NEXT: vpmaskmovd (%rdi), %xmm0, %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i32* %a0 to i8*
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%call = call <4 x i32> @llvm.x86.avx2.maskload.d(i8* %arg0, <4 x i32> %arg1)
@@ -1851,16 +1511,16 @@ define <2 x i64> @test_mm_maskload_epi32
declare <4 x i32> @llvm.x86.avx2.maskload.d(i8*, <4 x i32>) nounwind readonly
define <4 x i64> @test_mm256_maskload_epi32(i32* %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_maskload_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmaskmovd (%eax), %ymm0, %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_maskload_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpmaskmovd (%eax), %ymm0, %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_maskload_epi32:
; X64: # BB#0:
; X64-NEXT: vpmaskmovd (%rdi), %ymm0, %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i32* %a0 to i8*
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%call = call <8 x i32> @llvm.x86.avx2.maskload.d.256(i8* %arg0, <8 x i32> %arg1)
@@ -1870,16 +1530,16 @@ define <4 x i64> @test_mm256_maskload_ep
declare <8 x i32> @llvm.x86.avx2.maskload.d.256(i8*, <8 x i32>) nounwind readonly
define <2 x i64> @test_mm_maskload_epi64(i64* %a0, <2 x i64> %a1) nounwind {
-; X32-LABEL: test_mm_maskload_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmaskmovq (%eax), %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm_maskload_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpmaskmovq (%eax), %xmm0, %xmm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_maskload_epi64:
; X64: # BB#0:
; X64-NEXT: vpmaskmovq (%rdi), %xmm0, %xmm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i64* %a0 to i8*
%res = call <2 x i64> @llvm.x86.avx2.maskload.q(i8* %arg0, <2 x i64> %a1)
ret <2 x i64> %res
@@ -1887,16 +1547,16 @@ define <2 x i64> @test_mm_maskload_epi64
declare <2 x i64> @llvm.x86.avx2.maskload.q(i8*, <2 x i64>) nounwind readonly
define <4 x i64> @test_mm256_maskload_epi64(i64* %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_maskload_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmaskmovq (%eax), %ymm0, %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_maskload_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpmaskmovq (%eax), %ymm0, %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_maskload_epi64:
; X64: # BB#0:
; X64-NEXT: vpmaskmovq (%rdi), %ymm0, %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i64* %a0 to i8*
%res = call <4 x i64> @llvm.x86.avx2.maskload.q.256(i8* %arg0, <4 x i64> %a1)
ret <4 x i64> %res
@@ -1904,16 +1564,16 @@ define <4 x i64> @test_mm256_maskload_ep
declare <4 x i64> @llvm.x86.avx2.maskload.q.256(i8*, <4 x i64>) nounwind readonly
define void @test_mm_maskstore_epi32(float* %a0, <2 x i64> %a1, <2 x i64> %a2) nounwind {
-; X32-LABEL: test_mm_maskstore_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmaskmovd %xmm1, %xmm0, (%eax)
-; X32-NEXT: retl
+; X86-LABEL: test_mm_maskstore_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpmaskmovd %xmm1, %xmm0, (%eax)
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_maskstore_epi32:
; X64: # BB#0:
; X64-NEXT: vpmaskmovd %xmm1, %xmm0, (%rdi)
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast float* %a0 to i8*
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%arg2 = bitcast <2 x i64> %a2 to <4 x i32>
@@ -1923,18 +1583,18 @@ define void @test_mm_maskstore_epi32(flo
declare void @llvm.x86.avx2.maskstore.d(i8*, <4 x i32>, <4 x i32>) nounwind readnone
define void @test_mm256_maskstore_epi32(float* %a0, <4 x i64> %a1, <4 x i64> %a2) nounwind {
-; X32-LABEL: test_mm256_maskstore_epi32:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmaskmovd %ymm1, %ymm0, (%eax)
-; X32-NEXT: vzeroupper
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_maskstore_epi32:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpmaskmovd %ymm1, %ymm0, (%eax)
+; X86-NEXT: vzeroupper
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_maskstore_epi32:
; X64: # BB#0:
; X64-NEXT: vpmaskmovd %ymm1, %ymm0, (%rdi)
; X64-NEXT: vzeroupper
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast float* %a0 to i8*
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%arg2 = bitcast <4 x i64> %a2 to <8 x i32>
@@ -1944,16 +1604,16 @@ define void @test_mm256_maskstore_epi32(
declare void @llvm.x86.avx2.maskstore.d.256(i8*, <8 x i32>, <8 x i32>) nounwind readnone
define void @test_mm_maskstore_epi64(i64* %a0, <2 x i64> %a1, <2 x i64> %a2) nounwind {
-; X32-LABEL: test_mm_maskstore_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmaskmovq %xmm1, %xmm0, (%eax)
-; X32-NEXT: retl
+; X86-LABEL: test_mm_maskstore_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpmaskmovq %xmm1, %xmm0, (%eax)
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm_maskstore_epi64:
; X64: # BB#0:
; X64-NEXT: vpmaskmovq %xmm1, %xmm0, (%rdi)
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i64* %a0 to i8*
call void @llvm.x86.avx2.maskstore.q(i8* %arg0, <2 x i64> %a1, <2 x i64> %a2)
ret void
@@ -1961,18 +1621,18 @@ define void @test_mm_maskstore_epi64(i64
declare void @llvm.x86.avx2.maskstore.q(i8*, <2 x i64>, <2 x i64>) nounwind readnone
define void @test_mm256_maskstore_epi64(i64* %a0, <4 x i64> %a1, <4 x i64> %a2) nounwind {
-; X32-LABEL: test_mm256_maskstore_epi64:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmaskmovq %ymm1, %ymm0, (%eax)
-; X32-NEXT: vzeroupper
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_maskstore_epi64:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpmaskmovq %ymm1, %ymm0, (%eax)
+; X86-NEXT: vzeroupper
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_maskstore_epi64:
; X64: # BB#0:
; X64-NEXT: vpmaskmovq %ymm1, %ymm0, (%rdi)
; X64-NEXT: vzeroupper
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast i64* %a0 to i8*
call void @llvm.x86.avx2.maskstore.q.256(i8* %arg0, <4 x i64> %a1, <4 x i64> %a2)
ret void
@@ -1980,15 +1640,10 @@ define void @test_mm256_maskstore_epi64(
declare void @llvm.x86.avx2.maskstore.q.256(i8*, <4 x i64>, <4 x i64>) nounwind readnone
define <4 x i64> @test_mm256_max_epi8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_max_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_max_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_max_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%cmp = icmp sgt <32 x i8> %arg0, %arg1
@@ -1998,15 +1653,10 @@ define <4 x i64> @test_mm256_max_epi8(<4
}
define <4 x i64> @test_mm256_max_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_max_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_max_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_max_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%cmp = icmp sgt <16 x i16> %arg0, %arg1
@@ -2016,15 +1666,10 @@ define <4 x i64> @test_mm256_max_epi16(<
}
define <4 x i64> @test_mm256_max_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_max_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_max_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_max_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%cmp = icmp sgt <8 x i32> %arg0, %arg1
@@ -2034,15 +1679,10 @@ define <4 x i64> @test_mm256_max_epi32(<
}
define <4 x i64> @test_mm256_max_epu8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_max_epu8:
-; X32: # BB#0:
-; X32-NEXT: vpmaxub %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_max_epu8:
-; X64: # BB#0:
-; X64-NEXT: vpmaxub %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_max_epu8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmaxub %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%cmp = icmp ugt <32 x i8> %arg0, %arg1
@@ -2052,15 +1692,10 @@ define <4 x i64> @test_mm256_max_epu8(<4
}
define <4 x i64> @test_mm256_max_epu16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_max_epu16:
-; X32: # BB#0:
-; X32-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_max_epu16:
-; X64: # BB#0:
-; X64-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_max_epu16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%cmp = icmp ugt <16 x i16> %arg0, %arg1
@@ -2070,15 +1705,10 @@ define <4 x i64> @test_mm256_max_epu16(<
}
define <4 x i64> @test_mm256_max_epu32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_max_epu32:
-; X32: # BB#0:
-; X32-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_max_epu32:
-; X64: # BB#0:
-; X64-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_max_epu32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%cmp = icmp ugt <8 x i32> %arg0, %arg1
@@ -2088,15 +1718,10 @@ define <4 x i64> @test_mm256_max_epu32(<
}
define <4 x i64> @test_mm256_min_epi8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_min_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpminsb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_min_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpminsb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_min_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpminsb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%cmp = icmp slt <32 x i8> %arg0, %arg1
@@ -2106,15 +1731,10 @@ define <4 x i64> @test_mm256_min_epi8(<4
}
define <4 x i64> @test_mm256_min_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_min_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpminsw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_min_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpminsw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_min_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpminsw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%cmp = icmp slt <16 x i16> %arg0, %arg1
@@ -2124,15 +1744,10 @@ define <4 x i64> @test_mm256_min_epi16(<
}
define <4 x i64> @test_mm256_min_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_min_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpminsd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_min_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpminsd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_min_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpminsd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%cmp = icmp slt <8 x i32> %arg0, %arg1
@@ -2142,15 +1757,10 @@ define <4 x i64> @test_mm256_min_epi32(<
}
define <4 x i64> @test_mm256_min_epu8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_min_epu8:
-; X32: # BB#0:
-; X32-NEXT: vpminub %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_min_epu8:
-; X64: # BB#0:
-; X64-NEXT: vpminub %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_min_epu8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpminub %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%cmp = icmp ult <32 x i8> %arg0, %arg1
@@ -2160,15 +1770,10 @@ define <4 x i64> @test_mm256_min_epu8(<4
}
define <4 x i64> @test_mm256_min_epu16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_min_epu16:
-; X32: # BB#0:
-; X32-NEXT: vpminuw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_min_epu16:
-; X64: # BB#0:
-; X64-NEXT: vpminuw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_min_epu16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpminuw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%cmp = icmp ult <16 x i16> %arg0, %arg1
@@ -2178,15 +1783,10 @@ define <4 x i64> @test_mm256_min_epu16(<
}
define <4 x i64> @test_mm256_min_epu32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_min_epu32:
-; X32: # BB#0:
-; X32-NEXT: vpminud %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_min_epu32:
-; X64: # BB#0:
-; X64-NEXT: vpminud %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_min_epu32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpminud %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%cmp = icmp ult <8 x i32> %arg0, %arg1
@@ -2196,17 +1796,11 @@ define <4 x i64> @test_mm256_min_epu32(<
}
define i32 @test_mm256_movemask_epi8(<4 x i64> %a0) nounwind {
-; X32-LABEL: test_mm256_movemask_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpmovmskb %ymm0, %eax
-; X32-NEXT: vzeroupper
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_movemask_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpmovmskb %ymm0, %eax
-; X64-NEXT: vzeroupper
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_movemask_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmovmskb %ymm0, %eax
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%res = call i32 @llvm.x86.avx2.pmovmskb(<32 x i8> %arg0)
ret i32 %res
@@ -2214,15 +1808,10 @@ define i32 @test_mm256_movemask_epi8(<4
declare i32 @llvm.x86.avx2.pmovmskb(<32 x i8>) nounwind readnone
define <4 x i64> @test_mm256_mpsadbw_epu8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_mpsadbw_epu8:
-; X32: # BB#0:
-; X32-NEXT: vmpsadbw $3, %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_mpsadbw_epu8:
-; X64: # BB#0:
-; X64-NEXT: vmpsadbw $3, %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_mpsadbw_epu8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmpsadbw $3, %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%call = call <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8> %arg0, <32 x i8> %arg1, i8 3)
@@ -2232,15 +1821,10 @@ define <4 x i64> @test_mm256_mpsadbw_epu
declare <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8>, <32 x i8>, i8) nounwind readnone
define <4 x i64> @test_mm256_mul_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_mul_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpmuldq %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_mul_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpmuldq %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_mul_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmuldq %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = call <4 x i64> @llvm.x86.avx2.pmul.dq(<8 x i32> %arg0, <8 x i32> %arg1)
@@ -2249,15 +1833,10 @@ define <4 x i64> @test_mm256_mul_epi32(<
declare <4 x i64> @llvm.x86.avx2.pmul.dq(<8 x i32>, <8 x i32>) nounwind readnone
define <4 x i64> @test_mm256_mul_epu32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_mul_epu32:
-; X32: # BB#0:
-; X32-NEXT: vpmuludq %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_mul_epu32:
-; X64: # BB#0:
-; X64-NEXT: vpmuludq %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_mul_epu32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmuludq %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = call <4 x i64> @llvm.x86.avx2.pmulu.dq(<8 x i32> %arg0, <8 x i32> %arg1)
@@ -2266,15 +1845,10 @@ define <4 x i64> @test_mm256_mul_epu32(<
declare <4 x i64> @llvm.x86.avx2.pmulu.dq(<8 x i32>, <8 x i32>) nounwind readnone
define <4 x i64> @test_mm256_mulhi_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_mulhi_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpmulhw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_mulhi_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpmulhw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_mulhi_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmulhw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> %arg0, <16 x i16> %arg1)
@@ -2284,15 +1858,10 @@ define <4 x i64> @test_mm256_mulhi_epi16
declare <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_mulhi_epu16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_mulhi_epu16:
-; X32: # BB#0:
-; X32-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_mulhi_epu16:
-; X64: # BB#0:
-; X64-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_mulhi_epu16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> %arg0, <16 x i16> %arg1)
@@ -2302,15 +1871,10 @@ define <4 x i64> @test_mm256_mulhi_epu16
declare <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_mulhrs_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_mulhrs_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpmulhrsw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_mulhrs_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpmulhrsw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_mulhrs_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmulhrsw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.pmul.hr.sw(<16 x i16> %arg0, <16 x i16> %arg1)
@@ -2320,15 +1884,10 @@ define <4 x i64> @test_mm256_mulhrs_epi1
declare <16 x i16> @llvm.x86.avx2.pmul.hr.sw(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_mullo_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_mullo_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpmullw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_mullo_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpmullw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_mullo_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmullw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = mul <16 x i16> %arg0, %arg1
@@ -2337,15 +1896,10 @@ define <4 x i64> @test_mm256_mullo_epi16
}
define <4 x i64> @test_mm256_mullo_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_mullo_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpmulld %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_mullo_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpmulld %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_mullo_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmulld %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = mul <8 x i32> %arg0, %arg1
@@ -2354,29 +1908,19 @@ define <4 x i64> @test_mm256_mullo_epi32
}
define <4 x i64> @test_mm256_or_si256(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_or_si256:
-; X32: # BB#0:
-; X32-NEXT: vorps %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_or_si256:
-; X64: # BB#0:
-; X64-NEXT: vorps %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_or_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: vorps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = or <4 x i64> %a0, %a1
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_packs_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_packs_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpacksswb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_packs_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpacksswb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_packs_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpacksswb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%call = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> %arg0, <16 x i16> %arg1)
@@ -2386,15 +1930,10 @@ define <4 x i64> @test_mm256_packs_epi16
declare <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_packs_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_packs_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpackssdw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_packs_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpackssdw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_packs_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpackssdw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%call = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> %arg0, <8 x i32> %arg1)
@@ -2404,15 +1943,10 @@ define <4 x i64> @test_mm256_packs_epi32
declare <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32>, <8 x i32>) nounwind readnone
define <4 x i64> @test_mm256_packus_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_packus_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpackuswb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_packus_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpackuswb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_packus_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpackuswb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%call = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> %arg0, <16 x i16> %arg1)
@@ -2422,15 +1956,10 @@ define <4 x i64> @test_mm256_packus_epi1
declare <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_packus_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_packus_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpackusdw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_packus_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpackusdw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_packus_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpackusdw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%call = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> %arg0, <8 x i32> %arg1)
@@ -2440,58 +1969,38 @@ define <4 x i64> @test_mm256_packus_epi3
declare <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32>, <8 x i32>) nounwind readnone
define <4 x i64> @test_mm256_permute2x128_si256(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_permute2x128_si256:
-; X32: # BB#0:
-; X32-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_permute2x128_si256:
-; X64: # BB#0:
-; X64-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_permute2x128_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <4 x i64> %a0, <4 x i64> %a1, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
ret <4 x i64> %res
}
declare <4 x i64> @llvm.x86.avx2.vperm2i128(<4 x i64>, <4 x i64>, i8) nounwind readonly
define <4 x i64> @test_mm256_permute4x64_epi64(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_permute4x64_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[3,0,2,0]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_permute4x64_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[3,0,2,0]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_permute4x64_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[3,0,2,0]
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 3, i32 0, i32 2, i32 0>
ret <4 x i64> %res
}
define <4 x double> @test_mm256_permute4x64_pd(<4 x double> %a0) {
-; X32-LABEL: test_mm256_permute4x64_pd:
-; X32: # BB#0:
-; X32-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[1,2,1,0]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_permute4x64_pd:
-; X64: # BB#0:
-; X64-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[1,2,1,0]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_permute4x64_pd:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[1,2,1,0]
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <4 x double> %a0, <4 x double> undef, <4 x i32> <i32 1, i32 2, i32 1, i32 0>
ret <4 x double> %res
}
define <4 x i64> @test_mm256_permutevar8x32_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_permutevar8x32_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_permutevar8x32_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_permutevar8x32_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%call = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %arg0, <8 x i32> %arg1)
@@ -2501,15 +2010,10 @@ define <4 x i64> @test_mm256_permutevar8
declare <8 x i32> @llvm.x86.avx2.permd(<8 x i32>, <8 x i32>) nounwind readonly
define <8 x float> @test_mm256_permutevar8x32_ps(<8 x float> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_permutevar8x32_ps:
-; X32: # BB#0:
-; X32-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_permutevar8x32_ps:
-; X64: # BB#0:
-; X64-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_permutevar8x32_ps:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> %arg1)
ret <8 x float> %res
@@ -2517,15 +2021,10 @@ define <8 x float> @test_mm256_permuteva
declare <8 x float> @llvm.x86.avx2.permps(<8 x float>, <8 x i32>) nounwind readonly
define <4 x i64> @test_mm256_sad_epu8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_sad_epu8:
-; X32: # BB#0:
-; X32-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sad_epu8:
-; X64: # BB#0:
-; X64-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sad_epu8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsadbw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%res = call <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8> %arg0, <32 x i8> %arg1)
@@ -2534,15 +2033,10 @@ define <4 x i64> @test_mm256_sad_epu8(<4
declare <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8>, <32 x i8>) nounwind readnone
define <4 x i64> @test_mm256_shuffle_epi32(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_shuffle_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,3,0,0,7,7,4,4]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_shuffle_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,3,0,0,7,7,4,4]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_shuffle_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,3,0,0,7,7,4,4]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%shuf = shufflevector <8 x i32> %arg0, <8 x i32> undef, <8 x i32> <i32 3, i32 3, i32 0, i32 0, i32 7, i32 7, i32 4, i32 4>
%res = bitcast <8 x i32> %shuf to <4 x i64>
@@ -2550,15 +2044,10 @@ define <4 x i64> @test_mm256_shuffle_epi
}
define <4 x i64> @test_mm256_shuffle_epi8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_shuffle_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpshufb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_shuffle_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpshufb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_shuffle_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpshufb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%shuf = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %arg0, <32 x i8> %arg1)
@@ -2568,15 +2057,10 @@ define <4 x i64> @test_mm256_shuffle_epi
declare <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8>, <32 x i8>) nounwind readnone
define <4 x i64> @test_mm256_shufflehi_epi16(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_shufflehi_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,7,6,6,5,8,9,10,11,15,14,14,13]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_shufflehi_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,7,6,6,5,8,9,10,11,15,14,14,13]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_shufflehi_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,7,6,6,5,8,9,10,11,15,14,14,13]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%shuf = shufflevector <16 x i16> %arg0, <16 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 6, i32 6, i32 5, i32 8, i32 9, i32 10, i32 11, i32 15, i32 14, i32 14, i32 13>
%res = bitcast <16 x i16> %shuf to <4 x i64>
@@ -2584,15 +2068,10 @@ define <4 x i64> @test_mm256_shufflehi_e
}
define <4 x i64> @test_mm256_shufflelo_epi16(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_shufflelo_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpshuflw {{.*#+}} ymm0 = ymm0[3,0,1,1,4,5,6,7,11,8,9,9,12,13,14,15]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_shufflelo_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpshuflw {{.*#+}} ymm0 = ymm0[3,0,1,1,4,5,6,7,11,8,9,9,12,13,14,15]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_shufflelo_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpshuflw {{.*#+}} ymm0 = ymm0[3,0,1,1,4,5,6,7,11,8,9,9,12,13,14,15]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%shuf = shufflevector <16 x i16> %arg0, <16 x i16> undef, <16 x i32> <i32 3, i32 0, i32 1, i32 1, i32 4, i32 5, i32 6, i32 7, i32 11, i32 8, i32 9, i32 9, i32 12, i32 13, i32 14, i32 15>
%res = bitcast <16 x i16> %shuf to <4 x i64>
@@ -2600,15 +2079,10 @@ define <4 x i64> @test_mm256_shufflelo_e
}
define <4 x i64> @test_mm256_sign_epi8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_sign_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpsignb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sign_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpsignb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sign_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsignb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%call = call <32 x i8> @llvm.x86.avx2.psign.b(<32 x i8> %arg0, <32 x i8> %arg1)
@@ -2618,15 +2092,10 @@ define <4 x i64> @test_mm256_sign_epi8(<
declare <32 x i8> @llvm.x86.avx2.psign.b(<32 x i8>, <32 x i8>) nounwind readnone
define <4 x i64> @test_mm256_sign_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_sign_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpsignw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sign_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpsignw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sign_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsignw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%call = call <16 x i16> @llvm.x86.avx2.psign.w(<16 x i16> %arg0, <16 x i16> %arg1)
@@ -2636,15 +2105,10 @@ define <4 x i64> @test_mm256_sign_epi16(
declare <16 x i16> @llvm.x86.avx2.psign.w(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_sign_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_sign_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsignd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sign_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsignd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sign_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsignd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%call = call <8 x i32> @llvm.x86.avx2.psign.d(<8 x i32> %arg0, <8 x i32> %arg1)
@@ -2654,15 +2118,10 @@ define <4 x i64> @test_mm256_sign_epi32(
declare <8 x i32> @llvm.x86.avx2.psign.d(<8 x i32>, <8 x i32>) nounwind readnone
define <4 x i64> @test_mm256_sll_epi16(<4 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm256_sll_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpsllw %xmm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sll_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpsllw %xmm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sll_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsllw %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <2 x i64> %a1 to <8 x i16>
%res = call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %arg0, <8 x i16> %arg1)
@@ -2672,15 +2131,10 @@ define <4 x i64> @test_mm256_sll_epi16(<
declare <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16>, <8 x i16>) nounwind readnone
define <4 x i64> @test_mm256_sll_epi32(<4 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm256_sll_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpslld %xmm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sll_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpslld %xmm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sll_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpslld %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%res = call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %arg0, <4 x i32> %arg1)
@@ -2690,30 +2144,20 @@ define <4 x i64> @test_mm256_sll_epi32(<
declare <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32>, <4 x i32>) nounwind readnone
define <4 x i64> @test_mm256_sll_epi64(<4 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm256_sll_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpsllq %xmm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sll_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpsllq %xmm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sll_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsllq %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %a0, <2 x i64> %a1)
ret <4 x i64> %res
}
declare <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64>, <2 x i64>) nounwind readnone
define <4 x i64> @test_mm256_slli_epi16(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_slli_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpsllw $3, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_slli_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpsllw $3, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_slli_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsllw $3, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %arg0, i32 3)
%bc = bitcast <16 x i16> %res to <4 x i64>
@@ -2722,15 +2166,10 @@ define <4 x i64> @test_mm256_slli_epi16(
declare <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16>, i32) nounwind readnone
define <4 x i64> @test_mm256_slli_epi32(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_slli_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpslld $3, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_slli_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpslld $3, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_slli_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpslld $3, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%res = call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %arg0, i32 3)
%bc = bitcast <8 x i32> %res to <4 x i64>
@@ -2739,30 +2178,20 @@ define <4 x i64> @test_mm256_slli_epi32(
declare <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32>, i32) nounwind readnone
define <4 x i64> @test_mm256_slli_epi64(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_slli_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpsllq $3, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_slli_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpsllq $3, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_slli_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsllq $3, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %a0, i32 3)
ret <4 x i64> %res
}
declare <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64>, i32) nounwind readnone
define <4 x i64> @test_mm256_slli_si256(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_slli_si256:
-; X32: # BB#0:
-; X32-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12],zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_slli_si256:
-; X64: # BB#0:
-; X64-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12],zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_slli_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12],zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%shuf = shufflevector <32 x i8> zeroinitializer, <32 x i8> %arg0, <32 x i32> <i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60>
%res = bitcast <32 x i8> %shuf to <4 x i64>
@@ -2770,15 +2199,10 @@ define <4 x i64> @test_mm256_slli_si256(
}
define <2 x i64> @test_mm_sllv_epi32(<2 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_sllv_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_sllv_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_sllv_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <4 x i32>
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%res = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %arg0, <4 x i32> %arg1)
@@ -2788,15 +2212,10 @@ define <2 x i64> @test_mm_sllv_epi32(<2
declare <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x i64> @test_mm256_sllv_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_sllv_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sllv_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sllv_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %arg0, <8 x i32> %arg1)
@@ -2806,45 +2225,30 @@ define <4 x i64> @test_mm256_sllv_epi32(
declare <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32>, <8 x i32>) nounwind readnone
define <2 x i64> @test_mm_sllv_epi64(<2 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_sllv_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_sllv_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_sllv_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %a0, <2 x i64> %a1)
ret <2 x i64> %res
}
declare <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64>, <2 x i64>) nounwind readnone
define <4 x i64> @test_mm256_sllv_epi64(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_sllv_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpsllvq %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sllv_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpsllvq %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sllv_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsllvq %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %a0, <4 x i64> %a1)
ret <4 x i64> %res
}
declare <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64>, <4 x i64>) nounwind readnone
define <4 x i64> @test_mm256_sra_epi16(<4 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm256_sra_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpsraw %xmm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sra_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpsraw %xmm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sra_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsraw %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <2 x i64> %a1 to <8 x i16>
%res = call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %arg0, <8 x i16> %arg1)
@@ -2854,15 +2258,10 @@ define <4 x i64> @test_mm256_sra_epi16(<
declare <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16>, <8 x i16>) nounwind readnone
define <4 x i64> @test_mm256_sra_epi32(<4 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm256_sra_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsrad %xmm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sra_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsrad %xmm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sra_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrad %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%res = call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %arg0, <4 x i32> %arg1)
@@ -2872,15 +2271,10 @@ define <4 x i64> @test_mm256_sra_epi32(<
declare <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32>, <4 x i32>) nounwind readnone
define <4 x i64> @test_mm256_srai_epi16(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_srai_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpsraw $3, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srai_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpsraw $3, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srai_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsraw $3, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %arg0, i32 3)
%bc = bitcast <16 x i16> %res to <4 x i64>
@@ -2889,15 +2283,10 @@ define <4 x i64> @test_mm256_srai_epi16(
declare <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16>, i32) nounwind readnone
define <4 x i64> @test_mm256_srai_epi32(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_srai_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsrad $3, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srai_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsrad $3, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srai_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrad $3, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%res = call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %arg0, i32 3)
%bc = bitcast <8 x i32> %res to <4 x i64>
@@ -2906,15 +2295,10 @@ define <4 x i64> @test_mm256_srai_epi32(
declare <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32>, i32) nounwind readnone
define <2 x i64> @test_mm_srav_epi32(<2 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_srav_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsravd %xmm1, %xmm0, %xmm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_srav_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsravd %xmm1, %xmm0, %xmm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_srav_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsravd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <4 x i32>
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%res = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %arg0, <4 x i32> %arg1)
@@ -2924,15 +2308,10 @@ define <2 x i64> @test_mm_srav_epi32(<2
declare <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x i64> @test_mm256_srav_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_srav_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsravd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srav_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsravd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srav_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsravd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %arg0, <8 x i32> %arg1)
@@ -2942,15 +2321,10 @@ define <4 x i64> @test_mm256_srav_epi32(
declare <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32>, <8 x i32>) nounwind readnone
define <4 x i64> @test_mm256_srl_epi16(<4 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm256_srl_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpsrlw %xmm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srl_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpsrlw %xmm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srl_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrlw %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <2 x i64> %a1 to <8 x i16>
%res = call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %arg0, <8 x i16> %arg1)
@@ -2960,15 +2334,10 @@ define <4 x i64> @test_mm256_srl_epi16(<
declare <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16>, <8 x i16>) nounwind readnone
define <4 x i64> @test_mm256_srl_epi32(<4 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm256_srl_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsrld %xmm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srl_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsrld %xmm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srl_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrld %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%res = call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %arg0, <4 x i32> %arg1)
@@ -2978,30 +2347,20 @@ define <4 x i64> @test_mm256_srl_epi32(<
declare <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32>, <4 x i32>) nounwind readnone
define <4 x i64> @test_mm256_srl_epi64(<4 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm256_srl_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpsrlq %xmm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srl_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpsrlq %xmm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srl_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrlq %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %a0, <2 x i64> %a1)
ret <4 x i64> %res
}
declare <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64>, <2 x i64>) nounwind readnone
define <4 x i64> @test_mm256_srli_epi16(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_srli_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpsrlw $3, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srli_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpsrlw $3, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srli_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrlw $3, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> %arg0, i32 3)
%bc = bitcast <16 x i16> %res to <4 x i64>
@@ -3010,15 +2369,10 @@ define <4 x i64> @test_mm256_srli_epi16(
declare <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16>, i32) nounwind readnone
define <4 x i64> @test_mm256_srli_epi32(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_srli_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsrld $3, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srli_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsrld $3, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srli_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrld $3, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%res = call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> %arg0, i32 3)
%bc = bitcast <8 x i32> %res to <4 x i64>
@@ -3027,30 +2381,20 @@ define <4 x i64> @test_mm256_srli_epi32(
declare <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32>, i32) nounwind readnone
define <4 x i64> @test_mm256_srli_epi64(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_srli_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpsrlq $3, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srli_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpsrlq $3, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srli_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrlq $3, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> %a0, i32 3)
ret <4 x i64> %res
}
declare <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64>, i32) nounwind readnone
define <4 x i64> @test_mm256_srli_si256(<4 x i64> %a0) {
-; X32-LABEL: test_mm256_srli_si256:
-; X32: # BB#0:
-; X32-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[3,4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,ymm0[19,20,21,22,23,24,25,26,27,28,29,30,31],zero,zero,zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srli_si256:
-; X64: # BB#0:
-; X64-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[3,4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,ymm0[19,20,21,22,23,24,25,26,27,28,29,30,31],zero,zero,zero
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srli_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[3,4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,ymm0[19,20,21,22,23,24,25,26,27,28,29,30,31],zero,zero,zero
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%shuf = shufflevector <32 x i8> %arg0, <32 x i8> zeroinitializer, <32 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50>
%res = bitcast <32 x i8> %shuf to <4 x i64>
@@ -3058,15 +2402,10 @@ define <4 x i64> @test_mm256_srli_si256(
}
define <2 x i64> @test_mm_srlv_epi32(<2 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_srlv_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_srlv_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_srlv_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <2 x i64> %a0 to <4 x i32>
%arg1 = bitcast <2 x i64> %a1 to <4 x i32>
%res = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %arg0, <4 x i32> %arg1)
@@ -3076,15 +2415,10 @@ define <2 x i64> @test_mm_srlv_epi32(<2
declare <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x i64> @test_mm256_srlv_epi32(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_srlv_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srlv_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srlv_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %arg0, <8 x i32> %arg1)
@@ -3094,46 +2428,36 @@ define <4 x i64> @test_mm256_srlv_epi32(
declare <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32>, <8 x i32>) nounwind readnone
define <2 x i64> @test_mm_srlv_epi64(<2 x i64> %a0, <2 x i64> %a1) {
-; X32-LABEL: test_mm_srlv_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm_srlv_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm_srlv_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %a0, <2 x i64> %a1)
ret <2 x i64> %res
}
declare <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64>, <2 x i64>) nounwind readnone
define <4 x i64> @test_mm256_srlv_epi64(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_srlv_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_srlv_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_srlv_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %a0, <4 x i64> %a1)
ret <4 x i64> %res
}
declare <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64>, <4 x i64>) nounwind readnone
define <4 x i64> @test_mm256_stream_load_si256(<4 x i64> *%a0) {
-; X32-LABEL: test_mm256_stream_load_si256:
-; X32: # BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vmovntdqa (%eax), %ymm0
-; X32-NEXT: retl
+; X86-LABEL: test_mm256_stream_load_si256:
+; X86: # BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vmovntdqa (%eax), %ymm0
+; X86-NEXT: ret{{[l|q]}}
;
; X64-LABEL: test_mm256_stream_load_si256:
; X64: # BB#0:
; X64-NEXT: vmovntdqa (%rdi), %ymm0
-; X64-NEXT: retq
+; X64-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> *%a0 to i8*
%res = call <4 x i64> @llvm.x86.avx2.movntdqa(i8* %arg0)
ret <4 x i64> %res
@@ -3141,15 +2465,10 @@ define <4 x i64> @test_mm256_stream_load
declare <4 x i64> @llvm.x86.avx2.movntdqa(i8*) nounwind readonly
define <4 x i64> @test_mm256_sub_epi8(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_sub_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpsubb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sub_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpsubb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sub_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsubb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%res = sub <32 x i8> %arg0, %arg1
@@ -3158,15 +2477,10 @@ define <4 x i64> @test_mm256_sub_epi8(<4
}
define <4 x i64> @test_mm256_sub_epi16(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_sub_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpsubw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sub_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpsubw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sub_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsubw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = sub <16 x i16> %arg0, %arg1
@@ -3175,15 +2489,10 @@ define <4 x i64> @test_mm256_sub_epi16(<
}
define <4 x i64> @test_mm256_sub_epi32(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_sub_epi32:
-; X32: # BB#0:
-; X32-NEXT: vpsubd %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sub_epi32:
-; X64: # BB#0:
-; X64-NEXT: vpsubd %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sub_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsubd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = sub <8 x i32> %arg0, %arg1
@@ -3192,29 +2501,19 @@ define <4 x i64> @test_mm256_sub_epi32(<
}
define <4 x i64> @test_mm256_sub_epi64(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_sub_epi64:
-; X32: # BB#0:
-; X32-NEXT: vpsubq %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_sub_epi64:
-; X64: # BB#0:
-; X64-NEXT: vpsubq %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_sub_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsubq %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = sub <4 x i64> %a0, %a1
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_subs_epi8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_subs_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpsubsb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_subs_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpsubsb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_subs_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsubsb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%res = call <32 x i8> @llvm.x86.avx2.psubs.b(<32 x i8> %arg0, <32 x i8> %arg1)
@@ -3224,15 +2523,10 @@ define <4 x i64> @test_mm256_subs_epi8(<
declare <32 x i8> @llvm.x86.avx2.psubs.b(<32 x i8>, <32 x i8>) nounwind readnone
define <4 x i64> @test_mm256_subs_epi16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_subs_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpsubsw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_subs_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpsubsw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_subs_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsubsw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.psubs.w(<16 x i16> %arg0, <16 x i16> %arg1)
@@ -3242,15 +2536,10 @@ define <4 x i64> @test_mm256_subs_epi16(
declare <16 x i16> @llvm.x86.avx2.psubs.w(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_subs_epu8(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_subs_epu8:
-; X32: # BB#0:
-; X32-NEXT: vpsubusb %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_subs_epu8:
-; X64: # BB#0:
-; X64-NEXT: vpsubusb %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_subs_epu8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsubusb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%res = call <32 x i8> @llvm.x86.avx2.psubus.b(<32 x i8> %arg0, <32 x i8> %arg1)
@@ -3260,15 +2549,10 @@ define <4 x i64> @test_mm256_subs_epu8(<
declare <32 x i8> @llvm.x86.avx2.psubus.b(<32 x i8>, <32 x i8>) nounwind readnone
define <4 x i64> @test_mm256_subs_epu16(<4 x i64> %a0, <4 x i64> %a1) {
-; X32-LABEL: test_mm256_subs_epu16:
-; X32: # BB#0:
-; X32-NEXT: vpsubusw %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_subs_epu16:
-; X64: # BB#0:
-; X64-NEXT: vpsubusw %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_subs_epu16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpsubusw %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = call <16 x i16> @llvm.x86.avx2.psubus.w(<16 x i16> %arg0, <16 x i16> %arg1)
@@ -3278,15 +2562,10 @@ define <4 x i64> @test_mm256_subs_epu16(
declare <16 x i16> @llvm.x86.avx2.psubus.w(<16 x i16>, <16 x i16>) nounwind readnone
define <4 x i64> @test_mm256_unpackhi_epi8(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_unpackhi_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpunpckhbw {{.*#+}} ymm0 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_unpackhi_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpunpckhbw {{.*#+}} ymm0 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_unpackhi_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpunpckhbw {{.*#+}} ymm0 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%res = shufflevector <32 x i8> %arg0, <32 x i8> %arg1, <32 x i32> <i32 8, i32 40, i32 9, i32 41, i32 10, i32 42, i32 11, i32 43, i32 12, i32 44, i32 13, i32 45, i32 14, i32 46, i32 15, i32 47, i32 24, i32 56, i32 25, i32 57, i32 26, i32 58, i32 27, i32 59, i32 28, i32 60, i32 29, i32 61, i32 30, i32 62, i32 31, i32 63>
@@ -3295,15 +2574,10 @@ define <4 x i64> @test_mm256_unpackhi_ep
}
define <4 x i64> @test_mm256_unpackhi_epi16(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_unpackhi_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpunpckhwd {{.*#+}} ymm0 = ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_unpackhi_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpunpckhwd {{.*#+}} ymm0 = ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_unpackhi_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpunpckhwd {{.*#+}} ymm0 = ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = shufflevector <16 x i16> %arg0, <16 x i16> %arg1, <16 x i32> <i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
@@ -3312,15 +2586,10 @@ define <4 x i64> @test_mm256_unpackhi_ep
}
define <4 x i64> @test_mm256_unpackhi_epi32(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_unpackhi_epi32:
-; X32: # BB#0:
-; X32-NEXT: vunpckhps {{.*#+}} ymm0 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_unpackhi_epi32:
-; X64: # BB#0:
-; X64-NEXT: vunpckhps {{.*#+}} ymm0 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_unpackhi_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vunpckhps {{.*#+}} ymm0 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = shufflevector <8 x i32> %arg0, <8 x i32> %arg1, <8 x i32> <i32 2, i32 10, i32 3, i32 11, i32 6, i32 14, i32 7, i32 15>
@@ -3329,29 +2598,19 @@ define <4 x i64> @test_mm256_unpackhi_ep
}
define <4 x i64> @test_mm256_unpackhi_epi64(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_unpackhi_epi64:
-; X32: # BB#0:
-; X32-NEXT: vunpckhpd {{.*#+}} ymm0 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_unpackhi_epi64:
-; X64: # BB#0:
-; X64-NEXT: vunpckhpd {{.*#+}} ymm0 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_unpackhi_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vunpckhpd {{.*#+}} ymm0 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <4 x i64> %a0, <4 x i64> %a1, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_unpacklo_epi8(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_unpacklo_epi8:
-; X32: # BB#0:
-; X32-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_unpacklo_epi8:
-; X64: # BB#0:
-; X64-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_unpacklo_epi8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <32 x i8>
%arg1 = bitcast <4 x i64> %a1 to <32 x i8>
%res = shufflevector <32 x i8> %arg0, <32 x i8> %arg1, <32 x i32> <i32 0, i32 32, i32 1, i32 33, i32 2, i32 34, i32 3, i32 35, i32 4, i32 36, i32 5, i32 37, i32 6, i32 38, i32 7, i32 39, i32 16, i32 48, i32 17, i32 49, i32 18, i32 50, i32 19, i32 51, i32 20, i32 52, i32 21, i32 53, i32 22, i32 54, i32 23, i32 55>
@@ -3360,15 +2619,10 @@ define <4 x i64> @test_mm256_unpacklo_ep
}
define <4 x i64> @test_mm256_unpacklo_epi16(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_unpacklo_epi16:
-; X32: # BB#0:
-; X32-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_unpacklo_epi16:
-; X64: # BB#0:
-; X64-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_unpacklo_epi16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <16 x i16>
%arg1 = bitcast <4 x i64> %a1 to <16 x i16>
%res = shufflevector <16 x i16> %arg0, <16 x i16> %arg1, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27>
@@ -3377,15 +2631,10 @@ define <4 x i64> @test_mm256_unpacklo_ep
}
define <4 x i64> @test_mm256_unpacklo_epi32(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_unpacklo_epi32:
-; X32: # BB#0:
-; X32-NEXT: vunpcklps {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_unpacklo_epi32:
-; X64: # BB#0:
-; X64-NEXT: vunpcklps {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_unpacklo_epi32:
+; CHECK: # BB#0:
+; CHECK-NEXT: vunpcklps {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
+; CHECK-NEXT: ret{{[l|q]}}
%arg0 = bitcast <4 x i64> %a0 to <8 x i32>
%arg1 = bitcast <4 x i64> %a1 to <8 x i32>
%res = shufflevector <8 x i32> %arg0, <8 x i32> %arg1, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 4, i32 12, i32 5, i32 13>
@@ -3394,29 +2643,19 @@ define <4 x i64> @test_mm256_unpacklo_ep
}
define <4 x i64> @test_mm256_unpacklo_epi64(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_unpacklo_epi64:
-; X32: # BB#0:
-; X32-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_unpacklo_epi64:
-; X64: # BB#0:
-; X64-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_unpacklo_epi64:
+; CHECK: # BB#0:
+; CHECK-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
+; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <4 x i64> %a0, <4 x i64> %a1, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
ret <4 x i64> %res
}
define <4 x i64> @test_mm256_xor_si256(<4 x i64> %a0, <4 x i64> %a1) nounwind {
-; X32-LABEL: test_mm256_xor_si256:
-; X32: # BB#0:
-; X32-NEXT: vxorps %ymm1, %ymm0, %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_mm256_xor_si256:
-; X64: # BB#0:
-; X64-NEXT: vxorps %ymm1, %ymm0, %ymm0
-; X64-NEXT: retq
+; CHECK-LABEL: test_mm256_xor_si256:
+; CHECK: # BB#0:
+; CHECK-NEXT: vxorps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%res = xor <4 x i64> %a0, %a1
ret <4 x i64> %res
}
Modified: llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll?rev=316326&r1=316325&r2=316326&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll Mon Oct 23 07:19:46 2017
@@ -1,12 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX2
-; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX2 --check-prefix=X86 --check-prefix=X86-AVX2
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512 --check-prefix=X86 --check-prefix=X86-AVX512
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX2 --check-prefix=X64 --check-prefix=X64-AVX2
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512 --check-prefix=X64 --check-prefix=X64-AVX512
define <16 x i16> @test_x86_avx2_pblendw(<16 x i16> %a0, <16 x i16> %a1) {
; CHECK-LABEL: test_x86_avx2_pblendw:
; CHECK: ## BB#0:
; CHECK-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7],ymm1[8,9,10],ymm0[11,12,13,14,15]
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %a0, <16 x i16> %a1, i32 7) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -17,7 +19,7 @@ define <4 x i32> @test_x86_avx2_pblendd_
; CHECK-LABEL: test_x86_avx2_pblendd_128:
; CHECK: ## BB#0:
; CHECK-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %a0, <4 x i32> %a1, i32 7) ; <<4 x i32>> [#uses=1]
ret <4 x i32> %res
}
@@ -28,7 +30,7 @@ define <8 x i32> @test_x86_avx2_pblendd_
; CHECK-LABEL: test_x86_avx2_pblendd_256:
; CHECK: ## BB#0:
; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7]
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %a0, <8 x i32> %a1, i32 7) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -36,11 +38,16 @@ declare <8 x i32> @llvm.x86.avx2.pblendd
define <4 x i64> @test_x86_avx2_movntdqa(i8* %a0) {
-; CHECK-LABEL: test_x86_avx2_movntdqa:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT: vmovntdqa (%eax), %ymm0
-; CHECK-NEXT: retl
+; X86-LABEL: test_x86_avx2_movntdqa:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vmovntdqa (%eax), %ymm0
+; X86-NEXT: ret{{[l|q]}}
+;
+; X64-LABEL: test_x86_avx2_movntdqa:
+; X64: ## BB#0:
+; X64-NEXT: vmovntdqa (%rdi), %ymm0
+; X64-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.movntdqa(i8* %a0) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -51,7 +58,7 @@ define <16 x i16> @test_x86_avx2_mpsadbw
; CHECK-LABEL: test_x86_avx2_mpsadbw:
; CHECK: ## BB#0:
; CHECK-NEXT: vmpsadbw $7, %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8> %a0, <32 x i8> %a1, i32 7) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -62,7 +69,7 @@ define <4 x i64> @test_x86_avx2_psll_dq_
; CHECK-LABEL: test_x86_avx2_psll_dq_bs:
; CHECK: ## BB#0:
; CHECK-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8],zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24]
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.psll.dq.bs(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -73,7 +80,7 @@ define <4 x i64> @test_x86_avx2_psrl_dq_
; CHECK-LABEL: test_x86_avx2_psrl_dq_bs:
; CHECK: ## BB#0:
; CHECK-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,ymm0[23,24,25,26,27,28,29,30,31],zero,zero,zero,zero,zero,zero,zero
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.psrl.dq.bs(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -84,7 +91,7 @@ define <4 x i64> @test_x86_avx2_psll_dq(
; CHECK-LABEL: test_x86_avx2_psll_dq:
; CHECK: ## BB#0:
; CHECK-NEXT: vpslldq {{.*#+}} ymm0 = zero,ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14],zero,ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28,29,30]
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.psll.dq(<4 x i64> %a0, i32 8) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -95,7 +102,7 @@ define <4 x i64> @test_x86_avx2_psrl_dq(
; CHECK-LABEL: test_x86_avx2_psrl_dq:
; CHECK: ## BB#0:
; CHECK-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero,ymm0[17,18,19,20,21,22,23,24,25,26,27,28,29,30,31],zero
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.psrl.dq(<4 x i64> %a0, i32 8) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -107,7 +114,7 @@ define <2 x i64> @test_x86_avx2_vextract
; CHECK: ## BB#0:
; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <2 x i64> @llvm.x86.avx2.vextracti128(<4 x i64> %a0, i8 7)
ret <2 x i64> %res
}
@@ -118,7 +125,7 @@ define <4 x i64> @test_x86_avx2_vinserti
; CHECK-LABEL: test_x86_avx2_vinserti128:
; CHECK: ## BB#0:
; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.vinserti128(<4 x i64> %a0, <2 x i64> %a1, i8 7)
ret <4 x i64> %res
}
@@ -129,7 +136,7 @@ define <4 x double> @test_x86_avx2_vbroa
; CHECK-LABEL: test_x86_avx2_vbroadcast_sd_pd_256:
; CHECK: ## BB#0:
; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x double> @llvm.x86.avx2.vbroadcast.sd.pd.256(<2 x double> %a0)
ret <4 x double> %res
}
@@ -140,7 +147,7 @@ define <4 x float> @test_x86_avx2_vbroad
; CHECK-LABEL: test_x86_avx2_vbroadcast_ss_ps:
; CHECK: ## BB#0:
; CHECK-NEXT: vbroadcastss %xmm0, %xmm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x float> @llvm.x86.avx2.vbroadcast.ss.ps(<4 x float> %a0)
ret <4 x float> %res
}
@@ -151,7 +158,7 @@ define <8 x float> @test_x86_avx2_vbroad
; CHECK-LABEL: test_x86_avx2_vbroadcast_ss_ps_256:
; CHECK: ## BB#0:
; CHECK-NEXT: vbroadcastss %xmm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <8 x float> @llvm.x86.avx2.vbroadcast.ss.ps.256(<4 x float> %a0)
ret <8 x float> %res
}
@@ -162,7 +169,7 @@ define <16 x i8> @test_x86_avx2_pbroadca
; CHECK-LABEL: test_x86_avx2_pbroadcastb_128:
; CHECK: ## BB#0:
; CHECK-NEXT: vpbroadcastb %xmm0, %xmm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <16 x i8> @llvm.x86.avx2.pbroadcastb.128(<16 x i8> %a0)
ret <16 x i8> %res
}
@@ -173,7 +180,7 @@ define <32 x i8> @test_x86_avx2_pbroadca
; CHECK-LABEL: test_x86_avx2_pbroadcastb_256:
; CHECK: ## BB#0:
; CHECK-NEXT: vpbroadcastb %xmm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <32 x i8> @llvm.x86.avx2.pbroadcastb.256(<16 x i8> %a0)
ret <32 x i8> %res
}
@@ -184,7 +191,7 @@ define <8 x i16> @test_x86_avx2_pbroadca
; CHECK-LABEL: test_x86_avx2_pbroadcastw_128:
; CHECK: ## BB#0:
; CHECK-NEXT: vpbroadcastw %xmm0, %xmm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <8 x i16> @llvm.x86.avx2.pbroadcastw.128(<8 x i16> %a0)
ret <8 x i16> %res
}
@@ -195,7 +202,7 @@ define <16 x i16> @test_x86_avx2_pbroadc
; CHECK-LABEL: test_x86_avx2_pbroadcastw_256:
; CHECK: ## BB#0:
; CHECK-NEXT: vpbroadcastw %xmm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <16 x i16> @llvm.x86.avx2.pbroadcastw.256(<8 x i16> %a0)
ret <16 x i16> %res
}
@@ -206,7 +213,7 @@ define <4 x i32> @test_x86_avx2_pbroadca
; CHECK-LABEL: test_x86_avx2_pbroadcastd_128:
; CHECK: ## BB#0:
; CHECK-NEXT: vbroadcastss %xmm0, %xmm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i32> @llvm.x86.avx2.pbroadcastd.128(<4 x i32> %a0)
ret <4 x i32> %res
}
@@ -217,7 +224,7 @@ define <8 x i32> @test_x86_avx2_pbroadca
; CHECK-LABEL: test_x86_avx2_pbroadcastd_256:
; CHECK: ## BB#0:
; CHECK-NEXT: vbroadcastss %xmm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <8 x i32> @llvm.x86.avx2.pbroadcastd.256(<4 x i32> %a0)
ret <8 x i32> %res
}
@@ -228,7 +235,7 @@ define <2 x i64> @test_x86_avx2_pbroadca
; CHECK-LABEL: test_x86_avx2_pbroadcastq_128:
; CHECK: ## BB#0:
; CHECK-NEXT: vpbroadcastq %xmm0, %xmm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <2 x i64> @llvm.x86.avx2.pbroadcastq.128(<2 x i64> %a0)
ret <2 x i64> %res
}
@@ -239,7 +246,7 @@ define <4 x i64> @test_x86_avx2_pbroadca
; CHECK-LABEL: test_x86_avx2_pbroadcastq_256:
; CHECK: ## BB#0:
; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.pbroadcastq.256(<2 x i64> %a0)
ret <4 x i64> %res
}
@@ -250,7 +257,7 @@ define <8 x i32> @test_x86_avx2_pmovsxbd
; CHECK-LABEL: test_x86_avx2_pmovsxbd:
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovsxbd %xmm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <8 x i32> @llvm.x86.avx2.pmovsxbd(<16 x i8> %a0) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -261,7 +268,7 @@ define <4 x i64> @test_x86_avx2_pmovsxbq
; CHECK-LABEL: test_x86_avx2_pmovsxbq:
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovsxbq %xmm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.pmovsxbq(<16 x i8> %a0) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -272,7 +279,7 @@ define <16 x i16> @test_x86_avx2_pmovsxb
; CHECK-LABEL: test_x86_avx2_pmovsxbw:
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovsxbw %xmm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <16 x i16> @llvm.x86.avx2.pmovsxbw(<16 x i8> %a0) ; <<8 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -283,7 +290,7 @@ define <4 x i64> @test_x86_avx2_pmovsxdq
; CHECK-LABEL: test_x86_avx2_pmovsxdq:
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovsxdq %xmm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.pmovsxdq(<4 x i32> %a0) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -294,7 +301,7 @@ define <8 x i32> @test_x86_avx2_pmovsxwd
; CHECK-LABEL: test_x86_avx2_pmovsxwd:
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovsxwd %xmm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <8 x i32> @llvm.x86.avx2.pmovsxwd(<8 x i16> %a0) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -305,7 +312,7 @@ define <4 x i64> @test_x86_avx2_pmovsxwq
; CHECK-LABEL: test_x86_avx2_pmovsxwq:
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovsxwq %xmm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.pmovsxwq(<8 x i16> %a0) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -316,7 +323,7 @@ define <8 x i32> @test_x86_avx2_pmovzxbd
; CHECK-LABEL: test_x86_avx2_pmovzxbd:
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <8 x i32> @llvm.x86.avx2.pmovzxbd(<16 x i8> %a0) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -327,7 +334,7 @@ define <4 x i64> @test_x86_avx2_pmovzxbq
; CHECK-LABEL: test_x86_avx2_pmovzxbq:
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovzxbq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.pmovzxbq(<16 x i8> %a0) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -338,7 +345,7 @@ define <16 x i16> @test_x86_avx2_pmovzxb
; CHECK-LABEL: test_x86_avx2_pmovzxbw:
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <16 x i16> @llvm.x86.avx2.pmovzxbw(<16 x i8> %a0) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -349,7 +356,7 @@ define <4 x i64> @test_x86_avx2_pmovzxdq
; CHECK-LABEL: test_x86_avx2_pmovzxdq:
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.pmovzxdq(<4 x i32> %a0) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -360,7 +367,7 @@ define <8 x i32> @test_x86_avx2_pmovzxwd
; CHECK-LABEL: test_x86_avx2_pmovzxwd:
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <8 x i32> @llvm.x86.avx2.pmovzxwd(<8 x i16> %a0) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -371,7 +378,7 @@ define <4 x i64> @test_x86_avx2_pmovzxwq
; CHECK-LABEL: test_x86_avx2_pmovzxwq:
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovzxwq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.pmovzxwq(<8 x i16> %a0) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -380,14 +387,22 @@ declare <4 x i64> @llvm.x86.avx2.pmovzxw
; This is checked here because the execution dependency fix pass makes it hard to test in AVX mode since we don't have 256-bit integer instructions
define void @test_x86_avx_storeu_dq_256(i8* %a0, <32 x i8> %a1) {
; add operation forces the execution domain.
-; CHECK-LABEL: test_x86_avx_storeu_dq_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
-; CHECK-NEXT: vpsubb %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: vmovdqu %ymm0, (%eax)
-; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: retl
+; X86-LABEL: test_x86_avx_storeu_dq_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; X86-NEXT: vpsubb %ymm1, %ymm0, %ymm0
+; X86-NEXT: vmovdqu %ymm0, (%eax)
+; X86-NEXT: vzeroupper
+; X86-NEXT: ret{{[l|q]}}
+;
+; X64-LABEL: test_x86_avx_storeu_dq_256:
+; X64: ## BB#0:
+; X64-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; X64-NEXT: vpsubb %ymm1, %ymm0, %ymm0
+; X64-NEXT: vmovdqu %ymm0, (%rdi)
+; X64-NEXT: vzeroupper
+; X64-NEXT: ret{{[l|q]}}
%a2 = add <32 x i8> %a1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
call void @llvm.x86.avx.storeu.dq.256(i8* %a0, <32 x i8> %a2)
ret void
@@ -398,7 +413,7 @@ define <32 x i8> @mm256_max_epi8(<32 x i
; CHECK-LABEL: mm256_max_epi8:
; CHECK: ## BB#0:
; CHECK-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <32 x i8> @llvm.x86.avx2.pmaxs.b(<32 x i8> %a0, <32 x i8> %a1)
ret <32 x i8> %res
}
@@ -408,7 +423,7 @@ define <16 x i16> @mm256_max_epi16(<16 x
; CHECK-LABEL: mm256_max_epi16:
; CHECK: ## BB#0:
; CHECK-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <16 x i16> @llvm.x86.avx2.pmaxs.w(<16 x i16> %a0, <16 x i16> %a1)
ret <16 x i16> %res
}
@@ -418,7 +433,7 @@ define <8 x i32> @mm256_max_epi32(<8 x i
; CHECK-LABEL: mm256_max_epi32:
; CHECK: ## BB#0:
; CHECK-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <8 x i32> @llvm.x86.avx2.pmaxs.d(<8 x i32> %a0, <8 x i32> %a1)
ret <8 x i32> %res
}
@@ -428,7 +443,7 @@ define <32 x i8> @mm256_max_epu8(<32 x i
; CHECK-LABEL: mm256_max_epu8:
; CHECK: ## BB#0:
; CHECK-NEXT: vpmaxub %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <32 x i8> @llvm.x86.avx2.pmaxu.b(<32 x i8> %a0, <32 x i8> %a1)
ret <32 x i8> %res
}
@@ -438,7 +453,7 @@ define <16 x i16> @mm256_max_epu16(<16 x
; CHECK-LABEL: mm256_max_epu16:
; CHECK: ## BB#0:
; CHECK-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <16 x i16> @llvm.x86.avx2.pmaxu.w(<16 x i16> %a0, <16 x i16> %a1)
ret <16 x i16> %res
}
@@ -448,7 +463,7 @@ define <8 x i32> @mm256_max_epu32(<8 x i
; CHECK-LABEL: mm256_max_epu32:
; CHECK: ## BB#0:
; CHECK-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <8 x i32> @llvm.x86.avx2.pmaxu.d(<8 x i32> %a0, <8 x i32> %a1)
ret <8 x i32> %res
}
@@ -458,7 +473,7 @@ define <32 x i8> @mm256_min_epi8(<32 x i
; CHECK-LABEL: mm256_min_epi8:
; CHECK: ## BB#0:
; CHECK-NEXT: vpminsb %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <32 x i8> @llvm.x86.avx2.pmins.b(<32 x i8> %a0, <32 x i8> %a1)
ret <32 x i8> %res
}
@@ -468,7 +483,7 @@ define <16 x i16> @mm256_min_epi16(<16 x
; CHECK-LABEL: mm256_min_epi16:
; CHECK: ## BB#0:
; CHECK-NEXT: vpminsw %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <16 x i16> @llvm.x86.avx2.pmins.w(<16 x i16> %a0, <16 x i16> %a1)
ret <16 x i16> %res
}
@@ -478,7 +493,7 @@ define <8 x i32> @mm256_min_epi32(<8 x i
; CHECK-LABEL: mm256_min_epi32:
; CHECK: ## BB#0:
; CHECK-NEXT: vpminsd %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <8 x i32> @llvm.x86.avx2.pmins.d(<8 x i32> %a0, <8 x i32> %a1)
ret <8 x i32> %res
}
@@ -488,7 +503,7 @@ define <32 x i8> @mm256_min_epu8(<32 x i
; CHECK-LABEL: mm256_min_epu8:
; CHECK: ## BB#0:
; CHECK-NEXT: vpminub %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <32 x i8> @llvm.x86.avx2.pminu.b(<32 x i8> %a0, <32 x i8> %a1)
ret <32 x i8> %res
}
@@ -498,7 +513,7 @@ define <16 x i16> @mm256_min_epu16(<16 x
; CHECK-LABEL: mm256_min_epu16:
; CHECK: ## BB#0:
; CHECK-NEXT: vpminuw %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <16 x i16> @llvm.x86.avx2.pminu.w(<16 x i16> %a0, <16 x i16> %a1)
ret <16 x i16> %res
}
@@ -508,7 +523,7 @@ define <8 x i32> @mm256_min_epu32(<8 x i
; CHECK-LABEL: mm256_min_epu32:
; CHECK: ## BB#0:
; CHECK-NEXT: vpminud %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <8 x i32> @llvm.x86.avx2.pminu.d(<8 x i32> %a0, <8 x i32> %a1)
ret <8 x i32> %res
}
@@ -518,7 +533,7 @@ define <32 x i8> @mm256_avg_epu8(<32 x i
; CHECK-LABEL: mm256_avg_epu8:
; CHECK: ## BB#0:
; CHECK-NEXT: vpavgb %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <32 x i8> @llvm.x86.avx2.pavg.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -528,7 +543,7 @@ define <16 x i16> @mm256_avg_epu16(<16 x
; CHECK-LABEL: mm256_avg_epu16:
; CHECK: ## BB#0:
; CHECK-NEXT: vpavgw %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <16 x i16> @llvm.x86.avx2.pavg.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -538,7 +553,7 @@ define <32 x i8> @test_x86_avx2_pabs_b(<
; CHECK-LABEL: test_x86_avx2_pabs_b:
; CHECK: ## BB#0:
; CHECK-NEXT: vpabsb %ymm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <32 x i8> @llvm.x86.avx2.pabs.b(<32 x i8> %a0) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -548,7 +563,7 @@ define <8 x i32> @test_x86_avx2_pabs_d(<
; CHECK-LABEL: test_x86_avx2_pabs_d:
; CHECK: ## BB#0:
; CHECK-NEXT: vpabsd %ymm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <8 x i32> @llvm.x86.avx2.pabs.d(<8 x i32> %a0) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -559,7 +574,7 @@ define <16 x i16> @test_x86_avx2_pabs_w(
; CHECK-LABEL: test_x86_avx2_pabs_w:
; CHECK: ## BB#0:
; CHECK-NEXT: vpabsw %ymm0, %ymm0
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <16 x i16> @llvm.x86.avx2.pabs.w(<16 x i16> %a0) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -570,7 +585,7 @@ define <4 x i64> @test_x86_avx2_vperm2i1
; CHECK-LABEL: test_x86_avx2_vperm2i128:
; CHECK: ## BB#0:
; CHECK-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[2,3,0,1]
-; CHECK-NEXT: retl
+; CHECK-NEXT: ret{{[l|q]}}
%res = call <4 x i64> @llvm.x86.avx2.vperm2i128(<4 x i64> %a0, <4 x i64> %a1, i8 1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
Modified: llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll?rev=316326&r1=316325&r2=316326&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll Mon Oct 23 07:19:46 2017
@@ -1,17 +1,19 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=avx2 -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX2
-; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512VL
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=avx2 -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX2 --check-prefix=X86 --check-prefix=X86-AVX
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512VL --check-prefix=X86 --check-prefix=X86-AVX512VL
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=avx2 -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX2 --check-prefix=X64 --check-prefix=X64-AVX
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512VL --check-prefix=X64 --check-prefix=X64-AVX512VL
define <16 x i16> @test_x86_avx2_packssdw(<8 x i32> %a0, <8 x i32> %a1) {
; AVX2-LABEL: test_x86_avx2_packssdw:
; AVX2: ## BB#0:
; AVX2-NEXT: vpackssdw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x6b,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_packssdw:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpackssdw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6b,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> %a0, <8 x i32> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -19,19 +21,33 @@ declare <16 x i16> @llvm.x86.avx2.packss
define <16 x i16> @test_x86_avx2_packssdw_fold() {
-; AVX2-LABEL: test_x86_avx2_packssdw_fold:
-; AVX2: ## BB#0:
-; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
-; AVX2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; AVX2-NEXT: ## fixup A - offset: 4, value: LCPI1_0, kind: FK_Data_4
-; AVX2-NEXT: retl ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_packssdw_fold:
-; AVX512VL: ## BB#0:
-; AVX512VL-NEXT: vmovaps LCPI1_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
-; AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI1_0, kind: FK_Data_4
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_packssdw_fold:
+; X86-AVX: ## BB#0:
+; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
+; X86-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X86-AVX-NEXT: ## fixup A - offset: 4, value: LCPI1_0, kind: FK_Data_4
+; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_packssdw_fold:
+; X86-AVX512VL: ## BB#0:
+; X86-AVX512VL-NEXT: vmovaps LCPI1_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
+; X86-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI1_0, kind: FK_Data_4
+; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_packssdw_fold:
+; X64-AVX: ## BB#0:
+; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
+; X64-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X64-AVX-NEXT: ## fixup A - offset: 4, value: LCPI1_0-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_packssdw_fold:
+; X64-AVX512VL: ## BB#0:
+; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 ## EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
+; X64-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI1_0-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> zeroinitializer, <8 x i32> <i32 255, i32 32767, i32 65535, i32 -1, i32 -32767, i32 -65535, i32 0, i32 -256>)
ret <16 x i16> %res
}
@@ -41,12 +57,12 @@ define <32 x i8> @test_x86_avx2_packsswb
; AVX2-LABEL: test_x86_avx2_packsswb:
; AVX2: ## BB#0:
; AVX2-NEXT: vpacksswb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x63,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_packsswb:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpacksswb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x63,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> %a0, <16 x i16> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -54,19 +70,33 @@ declare <32 x i8> @llvm.x86.avx2.packssw
define <32 x i8> @test_x86_avx2_packsswb_fold() {
-; AVX2-LABEL: test_x86_avx2_packsswb_fold:
-; AVX2: ## BB#0:
-; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
-; AVX2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; AVX2-NEXT: ## fixup A - offset: 4, value: LCPI3_0, kind: FK_Data_4
-; AVX2-NEXT: retl ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_packsswb_fold:
-; AVX512VL: ## BB#0:
-; AVX512VL-NEXT: vmovaps LCPI3_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
-; AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI3_0, kind: FK_Data_4
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_packsswb_fold:
+; X86-AVX: ## BB#0:
+; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
+; X86-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X86-AVX-NEXT: ## fixup A - offset: 4, value: LCPI3_0, kind: FK_Data_4
+; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_packsswb_fold:
+; X86-AVX512VL: ## BB#0:
+; X86-AVX512VL-NEXT: vmovaps LCPI3_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
+; X86-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI3_0, kind: FK_Data_4
+; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_packsswb_fold:
+; X64-AVX: ## BB#0:
+; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
+; X64-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X64-AVX-NEXT: ## fixup A - offset: 4, value: LCPI3_0-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_packsswb_fold:
+; X64-AVX512VL: ## BB#0:
+; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 ## EVEX TO VEX Compression ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
+; X64-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI3_0-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678, i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <16 x i16> zeroinitializer)
ret <32 x i8> %res
}
@@ -76,12 +106,12 @@ define <32 x i8> @test_x86_avx2_packuswb
; AVX2-LABEL: test_x86_avx2_packuswb:
; AVX2: ## BB#0:
; AVX2-NEXT: vpackuswb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x67,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_packuswb:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpackuswb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x67,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> %a0, <16 x i16> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -89,19 +119,33 @@ declare <32 x i8> @llvm.x86.avx2.packusw
define <32 x i8> @test_x86_avx2_packuswb_fold() {
-; AVX2-LABEL: test_x86_avx2_packuswb_fold:
-; AVX2: ## BB#0:
-; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
-; AVX2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; AVX2-NEXT: ## fixup A - offset: 4, value: LCPI5_0, kind: FK_Data_4
-; AVX2-NEXT: retl ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_packuswb_fold:
-; AVX512VL: ## BB#0:
-; AVX512VL-NEXT: vmovaps LCPI5_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
-; AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI5_0, kind: FK_Data_4
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_packuswb_fold:
+; X86-AVX: ## BB#0:
+; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
+; X86-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X86-AVX-NEXT: ## fixup A - offset: 4, value: LCPI5_0, kind: FK_Data_4
+; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_packuswb_fold:
+; X86-AVX512VL: ## BB#0:
+; X86-AVX512VL-NEXT: vmovaps LCPI5_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
+; X86-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI5_0, kind: FK_Data_4
+; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_packuswb_fold:
+; X64-AVX: ## BB#0:
+; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
+; X64-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X64-AVX-NEXT: ## fixup A - offset: 4, value: LCPI5_0-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_packuswb_fold:
+; X64-AVX512VL: ## BB#0:
+; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 ## EVEX TO VEX Compression ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
+; X64-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI5_0-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678, i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <16 x i16> zeroinitializer)
ret <32 x i8> %res
}
@@ -111,12 +155,12 @@ define <32 x i8> @test_x86_avx2_padds_b(
; AVX2-LABEL: test_x86_avx2_padds_b:
; AVX2: ## BB#0:
; AVX2-NEXT: vpaddsb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xec,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_padds_b:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpaddsb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xec,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.padds.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -127,12 +171,12 @@ define <16 x i16> @test_x86_avx2_padds_w
; AVX2-LABEL: test_x86_avx2_padds_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpaddsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xed,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_padds_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpaddsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xed,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.padds.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -143,12 +187,12 @@ define <32 x i8> @test_x86_avx2_paddus_b
; AVX2-LABEL: test_x86_avx2_paddus_b:
; AVX2: ## BB#0:
; AVX2-NEXT: vpaddusb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xdc,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_paddus_b:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpaddusb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xdc,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.paddus.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -159,12 +203,12 @@ define <16 x i16> @test_x86_avx2_paddus_
; AVX2-LABEL: test_x86_avx2_paddus_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpaddusw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xdd,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_paddus_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpaddusw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xdd,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.paddus.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -175,12 +219,12 @@ define <8 x i32> @test_x86_avx2_pmadd_wd
; AVX2-LABEL: test_x86_avx2_pmadd_wd:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf5,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmadd_wd:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf5,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a0, <16 x i16> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -191,12 +235,12 @@ define <16 x i16> @test_x86_avx2_pmaxs_w
; AVX2-LABEL: test_x86_avx2_pmaxs_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xee,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmaxs_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xee,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pmaxs.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -207,12 +251,12 @@ define <32 x i8> @test_x86_avx2_pmaxu_b(
; AVX2-LABEL: test_x86_avx2_pmaxu_b:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xde,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmaxu_b:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xde,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.pmaxu.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -223,12 +267,12 @@ define <16 x i16> @test_x86_avx2_pmins_w
; AVX2-LABEL: test_x86_avx2_pmins_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpminsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xea,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmins_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpminsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xea,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pmins.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -239,12 +283,12 @@ define <32 x i8> @test_x86_avx2_pminu_b(
; AVX2-LABEL: test_x86_avx2_pminu_b:
; AVX2: ## BB#0:
; AVX2-NEXT: vpminub %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xda,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pminu_b:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpminub %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xda,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.pminu.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -256,7 +300,7 @@ define i32 @test_x86_avx2_pmovmskb(<32 x
; CHECK: ## BB#0:
; CHECK-NEXT: vpmovmskb %ymm0, %eax ## encoding: [0xc5,0xfd,0xd7,0xc0]
; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call i32 @llvm.x86.avx2.pmovmskb(<32 x i8> %a0) ; <i32> [#uses=1]
ret i32 %res
}
@@ -267,12 +311,12 @@ define <16 x i16> @test_x86_avx2_pmulh_w
; AVX2-LABEL: test_x86_avx2_pmulh_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmulhw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe5,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmulh_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmulhw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe5,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -283,12 +327,12 @@ define <16 x i16> @test_x86_avx2_pmulhu_
; AVX2-LABEL: test_x86_avx2_pmulhu_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe4,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmulhu_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe4,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -299,12 +343,12 @@ define <4 x i64> @test_x86_avx2_pmulu_dq
; AVX2-LABEL: test_x86_avx2_pmulu_dq:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmuludq %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf4,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmulu_dq:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmuludq %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf4,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.pmulu.dq(<8 x i32> %a0, <8 x i32> %a1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -315,12 +359,12 @@ define <4 x i64> @test_x86_avx2_psad_bw(
; AVX2-LABEL: test_x86_avx2_psad_bw:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf6,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psad_bw:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf6,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8> %a0, <32 x i8> %a1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -331,12 +375,12 @@ define <8 x i32> @test_x86_avx2_psll_d(<
; AVX2-LABEL: test_x86_avx2_psll_d:
; AVX2: ## BB#0:
; AVX2-NEXT: vpslld %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf2,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psll_d:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpslld %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf2,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %a0, <4 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -347,12 +391,12 @@ define <4 x i64> @test_x86_avx2_psll_q(<
; AVX2-LABEL: test_x86_avx2_psll_q:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsllq %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf3,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psll_q:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsllq %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf3,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %a0, <2 x i64> %a1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -363,12 +407,12 @@ define <16 x i16> @test_x86_avx2_psll_w(
; AVX2-LABEL: test_x86_avx2_psll_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsllw %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf1,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psll_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsllw %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf1,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %a0, <8 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -379,12 +423,12 @@ define <8 x i32> @test_x86_avx2_pslli_d(
; AVX2-LABEL: test_x86_avx2_pslli_d:
; AVX2: ## BB#0:
; AVX2-NEXT: vpslld $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x72,0xf0,0x07]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pslli_d:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpslld $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x72,0xf0,0x07]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %a0, i32 7) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -395,12 +439,12 @@ define <4 x i64> @test_x86_avx2_pslli_q(
; AVX2-LABEL: test_x86_avx2_pslli_q:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsllq $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x73,0xf0,0x07]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pslli_q:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsllq $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x73,0xf0,0x07]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -411,12 +455,12 @@ define <16 x i16> @test_x86_avx2_pslli_w
; AVX2-LABEL: test_x86_avx2_pslli_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsllw $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x71,0xf0,0x07]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pslli_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsllw $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x71,0xf0,0x07]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %a0, i32 7) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -427,12 +471,12 @@ define <8 x i32> @test_x86_avx2_psra_d(<
; AVX2-LABEL: test_x86_avx2_psra_d:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrad %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe2,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psra_d:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrad %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe2,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %a0, <4 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -443,12 +487,12 @@ define <16 x i16> @test_x86_avx2_psra_w(
; AVX2-LABEL: test_x86_avx2_psra_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsraw %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe1,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psra_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsraw %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe1,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %a0, <8 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -459,12 +503,12 @@ define <8 x i32> @test_x86_avx2_psrai_d(
; AVX2-LABEL: test_x86_avx2_psrai_d:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrad $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x72,0xe0,0x07]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrai_d:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrad $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x72,0xe0,0x07]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %a0, i32 7) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -475,12 +519,12 @@ define <16 x i16> @test_x86_avx2_psrai_w
; AVX2-LABEL: test_x86_avx2_psrai_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsraw $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x71,0xe0,0x07]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrai_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsraw $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x71,0xe0,0x07]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %a0, i32 7) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -491,12 +535,12 @@ define <8 x i32> @test_x86_avx2_psrl_d(<
; AVX2-LABEL: test_x86_avx2_psrl_d:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrld %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd2,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrl_d:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrld %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd2,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %a0, <4 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -507,12 +551,12 @@ define <4 x i64> @test_x86_avx2_psrl_q(<
; AVX2-LABEL: test_x86_avx2_psrl_q:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrlq %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd3,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrl_q:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrlq %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd3,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %a0, <2 x i64> %a1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -523,12 +567,12 @@ define <16 x i16> @test_x86_avx2_psrl_w(
; AVX2-LABEL: test_x86_avx2_psrl_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrlw %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd1,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrl_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrlw %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd1,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %a0, <8 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -539,12 +583,12 @@ define <8 x i32> @test_x86_avx2_psrli_d(
; AVX2-LABEL: test_x86_avx2_psrli_d:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrld $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x72,0xd0,0x07]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrli_d:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrld $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x72,0xd0,0x07]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> %a0, i32 7) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -555,12 +599,12 @@ define <4 x i64> @test_x86_avx2_psrli_q(
; AVX2-LABEL: test_x86_avx2_psrli_q:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrlq $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x73,0xd0,0x07]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrli_q:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrlq $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x73,0xd0,0x07]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -571,12 +615,12 @@ define <16 x i16> @test_x86_avx2_psrli_w
; AVX2-LABEL: test_x86_avx2_psrli_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrlw $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x71,0xd0,0x07]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrli_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrlw $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x71,0xd0,0x07]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> %a0, i32 7) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -587,12 +631,12 @@ define <32 x i8> @test_x86_avx2_psubs_b(
; AVX2-LABEL: test_x86_avx2_psubs_b:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsubsb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe8,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psubs_b:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsubsb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe8,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.psubs.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -603,12 +647,12 @@ define <16 x i16> @test_x86_avx2_psubs_w
; AVX2-LABEL: test_x86_avx2_psubs_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsubsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe9,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psubs_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsubsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe9,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psubs.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -619,12 +663,12 @@ define <32 x i8> @test_x86_avx2_psubus_b
; AVX2-LABEL: test_x86_avx2_psubus_b:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsubusb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd8,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psubus_b:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsubusb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd8,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.psubus.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -635,12 +679,12 @@ define <16 x i16> @test_x86_avx2_psubus_
; AVX2-LABEL: test_x86_avx2_psubus_w:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsubusw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd9,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psubus_w:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsubusw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd9,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psubus.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -650,7 +694,7 @@ define <8 x i32> @test_x86_avx2_phadd_d(
; CHECK-LABEL: test_x86_avx2_phadd_d:
; CHECK: ## BB#0:
; CHECK-NEXT: vphaddd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x02,0xc1]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -661,7 +705,7 @@ define <16 x i16> @test_x86_avx2_phadd_s
; CHECK-LABEL: test_x86_avx2_phadd_sw:
; CHECK: ## BB#0:
; CHECK-NEXT: vphaddsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x03,0xc1]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.phadd.sw(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -672,7 +716,7 @@ define <16 x i16> @test_x86_avx2_phadd_w
; CHECK-LABEL: test_x86_avx2_phadd_w:
; CHECK: ## BB#0:
; CHECK-NEXT: vphaddw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x01,0xc1]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -683,7 +727,7 @@ define <8 x i32> @test_x86_avx2_phsub_d(
; CHECK-LABEL: test_x86_avx2_phsub_d:
; CHECK: ## BB#0:
; CHECK-NEXT: vphsubd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x06,0xc1]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -694,7 +738,7 @@ define <16 x i16> @test_x86_avx2_phsub_s
; CHECK-LABEL: test_x86_avx2_phsub_sw:
; CHECK: ## BB#0:
; CHECK-NEXT: vphsubsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x07,0xc1]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.phsub.sw(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -705,7 +749,7 @@ define <16 x i16> @test_x86_avx2_phsub_w
; CHECK-LABEL: test_x86_avx2_phsub_w:
; CHECK: ## BB#0:
; CHECK-NEXT: vphsubw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x05,0xc1]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.phsub.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -716,12 +760,12 @@ define <16 x i16> @test_x86_avx2_pmadd_u
; AVX2-LABEL: test_x86_avx2_pmadd_ub_sw:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x04,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmadd_ub_sw:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x04,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8> %a0, <32 x i8> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -729,19 +773,31 @@ declare <16 x i16> @llvm.x86.avx2.pmadd.
; Make sure we don't commute this operation.
define <16 x i16> @test_x86_avx2_pmadd_ub_sw_load_op0(<32 x i8>* %ptr, <32 x i8> %a1) {
-; AVX2-LABEL: test_x86_avx2_pmadd_ub_sw_load_op0:
-; AVX2: ## BB#0:
-; AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; AVX2-NEXT: vmovdqa (%eax), %ymm1 ## encoding: [0xc5,0xfd,0x6f,0x08]
-; AVX2-NEXT: vpmaddubsw %ymm0, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0x04,0xc0]
-; AVX2-NEXT: retl ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pmadd_ub_sw_load_op0:
-; AVX512VL: ## BB#0:
-; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; AVX512VL-NEXT: vmovdqa (%eax), %ymm1 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0x08]
-; AVX512VL-NEXT: vpmaddubsw %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x04,0xc0]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pmadd_ub_sw_load_op0:
+; X86-AVX: ## BB#0:
+; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-AVX-NEXT: vmovdqa (%eax), %ymm1 ## encoding: [0xc5,0xfd,0x6f,0x08]
+; X86-AVX-NEXT: vpmaddubsw %ymm0, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0x04,0xc0]
+; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pmadd_ub_sw_load_op0:
+; X86-AVX512VL: ## BB#0:
+; X86-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-AVX512VL-NEXT: vmovdqa (%eax), %ymm1 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0x08]
+; X86-AVX512VL-NEXT: vpmaddubsw %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x04,0xc0]
+; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pmadd_ub_sw_load_op0:
+; X64-AVX: ## BB#0:
+; X64-AVX-NEXT: vmovdqa (%rdi), %ymm1 ## encoding: [0xc5,0xfd,0x6f,0x0f]
+; X64-AVX-NEXT: vpmaddubsw %ymm0, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0x04,0xc0]
+; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pmadd_ub_sw_load_op0:
+; X64-AVX512VL: ## BB#0:
+; X64-AVX512VL-NEXT: vmovdqa (%rdi), %ymm1 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0x0f]
+; X64-AVX512VL-NEXT: vpmaddubsw %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x04,0xc0]
+; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%a0 = load <32 x i8>, <32 x i8>* %ptr
%res = call <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8> %a0, <32 x i8> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
@@ -751,12 +807,12 @@ define <16 x i16> @test_x86_avx2_pmul_hr
; AVX2-LABEL: test_x86_avx2_pmul_hr_sw:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmulhrsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x0b,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmul_hr_sw:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmulhrsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x0b,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pmul.hr.sw(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -767,12 +823,12 @@ define <32 x i8> @test_x86_avx2_pshuf_b(
; AVX2-LABEL: test_x86_avx2_pshuf_b:
; AVX2: ## BB#0:
; AVX2-NEXT: vpshufb %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x00,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pshuf_b:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpshufb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x00,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> %a1) ; <<16 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -783,7 +839,7 @@ define <32 x i8> @test_x86_avx2_psign_b(
; CHECK-LABEL: test_x86_avx2_psign_b:
; CHECK: ## BB#0:
; CHECK-NEXT: vpsignb %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x08,0xc1]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.psign.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -794,7 +850,7 @@ define <8 x i32> @test_x86_avx2_psign_d(
; CHECK-LABEL: test_x86_avx2_psign_d:
; CHECK: ## BB#0:
; CHECK-NEXT: vpsignd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x0a,0xc1]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psign.d(<8 x i32> %a0, <8 x i32> %a1) ; <<4 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -805,7 +861,7 @@ define <16 x i16> @test_x86_avx2_psign_w
; CHECK-LABEL: test_x86_avx2_psign_w:
; CHECK: ## BB#0:
; CHECK-NEXT: vpsignw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x09,0xc1]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psign.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -816,7 +872,7 @@ define <16 x i16> @test_x86_avx2_mpsadbw
; CHECK-LABEL: test_x86_avx2_mpsadbw:
; CHECK: ## BB#0:
; CHECK-NEXT: vmpsadbw $7, %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x42,0xc1,0x07]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8> %a0, <32 x i8> %a1, i8 7) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -827,12 +883,12 @@ define <16 x i16> @test_x86_avx2_packusd
; AVX2-LABEL: test_x86_avx2_packusdw:
; AVX2: ## BB#0:
; AVX2-NEXT: vpackusdw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x2b,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_packusdw:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpackusdw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x2b,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> %a0, <8 x i32> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -840,19 +896,33 @@ declare <16 x i16> @llvm.x86.avx2.packus
define <16 x i16> @test_x86_avx2_packusdw_fold() {
-; AVX2-LABEL: test_x86_avx2_packusdw_fold:
-; AVX2: ## BB#0:
-; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
-; AVX2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; AVX2-NEXT: ## fixup A - offset: 4, value: LCPI55_0, kind: FK_Data_4
-; AVX2-NEXT: retl ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_packusdw_fold:
-; AVX512VL: ## BB#0:
-; AVX512VL-NEXT: vmovaps LCPI55_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
-; AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI55_0, kind: FK_Data_4
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_packusdw_fold:
+; X86-AVX: ## BB#0:
+; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
+; X86-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X86-AVX-NEXT: ## fixup A - offset: 4, value: LCPI55_0, kind: FK_Data_4
+; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_packusdw_fold:
+; X86-AVX512VL: ## BB#0:
+; X86-AVX512VL-NEXT: vmovaps LCPI55_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
+; X86-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI55_0, kind: FK_Data_4
+; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_packusdw_fold:
+; X64-AVX: ## BB#0:
+; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
+; X64-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X64-AVX-NEXT: ## fixup A - offset: 4, value: LCPI55_0-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_packusdw_fold:
+; X64-AVX512VL: ## BB#0:
+; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 ## EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
+; X64-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI55_0-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> zeroinitializer, <8 x i32> <i32 255, i32 32767, i32 65535, i32 -1, i32 -32767, i32 -65535, i32 0, i32 -256>)
ret <16 x i16> %res
}
@@ -862,7 +932,7 @@ define <32 x i8> @test_x86_avx2_pblendvb
; CHECK-LABEL: test_x86_avx2_pblendvb:
; CHECK: ## BB#0:
; CHECK-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x4c,0xc1,0x20]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> %a2) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -874,7 +944,7 @@ define <16 x i16> @test_x86_avx2_pblendw
; CHECK: ## BB#0:
; CHECK-NEXT: vpblendw $7, %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x0e,0xc1,0x07]
; CHECK-NEXT: ## ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7],ymm1[8,9,10],ymm0[11,12,13,14,15]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %a0, <16 x i16> %a1, i8 7) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -885,12 +955,12 @@ define <32 x i8> @test_x86_avx2_pmaxsb(<
; AVX2-LABEL: test_x86_avx2_pmaxsb:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3c,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmaxsb:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3c,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.pmaxs.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -901,12 +971,12 @@ define <8 x i32> @test_x86_avx2_pmaxsd(<
; AVX2-LABEL: test_x86_avx2_pmaxsd:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3d,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmaxsd:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3d,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.pmaxs.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -917,12 +987,12 @@ define <8 x i32> @test_x86_avx2_pmaxud(<
; AVX2-LABEL: test_x86_avx2_pmaxud:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3f,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmaxud:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3f,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.pmaxu.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -933,12 +1003,12 @@ define <16 x i16> @test_x86_avx2_pmaxuw(
; AVX2-LABEL: test_x86_avx2_pmaxuw:
; AVX2: ## BB#0:
; AVX2-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3e,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pmaxuw:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3e,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pmaxu.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -949,12 +1019,12 @@ define <32 x i8> @test_x86_avx2_pminsb(<
; AVX2-LABEL: test_x86_avx2_pminsb:
; AVX2: ## BB#0:
; AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x38,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pminsb:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpminsb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x38,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.pmins.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -965,12 +1035,12 @@ define <8 x i32> @test_x86_avx2_pminsd(<
; AVX2-LABEL: test_x86_avx2_pminsd:
; AVX2: ## BB#0:
; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x39,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pminsd:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpminsd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x39,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.pmins.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -981,12 +1051,12 @@ define <8 x i32> @test_x86_avx2_pminud(<
; AVX2-LABEL: test_x86_avx2_pminud:
; AVX2: ## BB#0:
; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3b,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pminud:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpminud %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3b,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.pminu.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -997,12 +1067,12 @@ define <16 x i16> @test_x86_avx2_pminuw(
; AVX2-LABEL: test_x86_avx2_pminuw:
; AVX2: ## BB#0:
; AVX2-NEXT: vpminuw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3a,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_pminuw:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpminuw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3a,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pminu.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -1021,7 +1091,7 @@ define <4 x i32> @test_x86_avx2_pblendd_
; CHECK: ## BB#0:
; CHECK-NEXT: vblendps $8, %xmm0, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x71,0x0c,0xc0,0x08]
; CHECK-NEXT: ## xmm0 = xmm1[0,1,2],xmm0[3]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %a0, <4 x i32> %a1, i8 7) ; <<4 x i32>> [#uses=1]
ret <4 x i32> %res
}
@@ -1033,7 +1103,7 @@ define <8 x i32> @test_x86_avx2_pblendd_
; CHECK: ## BB#0:
; CHECK-NEXT: vblendps $7, %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x0c,0xc1,0x07]
; CHECK-NEXT: ## ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %a0, <8 x i32> %a1, i8 7) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -1047,12 +1117,12 @@ define <8 x i32> @test_x86_avx2_permd(<8
; AVX2-LABEL: test_x86_avx2_permd:
; AVX2: ## BB#0:
; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0x16,0xc0]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_permd:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x16,0xc0]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -1066,12 +1136,12 @@ define <8 x float> @test_x86_avx2_permps
; AVX2-LABEL: test_x86_avx2_permps:
; AVX2: ## BB#0:
; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0x16,0xc0]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_permps:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x16,0xc0]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> %a1) ; <<8 x float>> [#uses=1]
ret <8 x float> %res
}
@@ -1079,11 +1149,16 @@ declare <8 x float> @llvm.x86.avx2.permp
define <2 x i64> @test_x86_avx2_maskload_q(i8* %a0, <2 x i64> %a1) {
-; CHECK-LABEL: test_x86_avx2_maskload_q:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpmaskmovq (%eax), %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0xf9,0x8c,0x00]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_maskload_q:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpmaskmovq (%eax), %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0xf9,0x8c,0x00]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_maskload_q:
+; X64: ## BB#0:
+; X64-NEXT: vpmaskmovq (%rdi), %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0xf9,0x8c,0x07]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx2.maskload.q(i8* %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
ret <2 x i64> %res
}
@@ -1091,11 +1166,16 @@ declare <2 x i64> @llvm.x86.avx2.maskloa
define <4 x i64> @test_x86_avx2_maskload_q_256(i8* %a0, <4 x i64> %a1) {
-; CHECK-LABEL: test_x86_avx2_maskload_q_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpmaskmovq (%eax), %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0xfd,0x8c,0x00]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_maskload_q_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpmaskmovq (%eax), %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0xfd,0x8c,0x00]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_maskload_q_256:
+; X64: ## BB#0:
+; X64-NEXT: vpmaskmovq (%rdi), %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0xfd,0x8c,0x07]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.maskload.q.256(i8* %a0, <4 x i64> %a1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -1103,11 +1183,16 @@ declare <4 x i64> @llvm.x86.avx2.maskloa
define <4 x i32> @test_x86_avx2_maskload_d(i8* %a0, <4 x i32> %a1) {
-; CHECK-LABEL: test_x86_avx2_maskload_d:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpmaskmovd (%eax), %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x8c,0x00]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_maskload_d:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpmaskmovd (%eax), %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x8c,0x00]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_maskload_d:
+; X64: ## BB#0:
+; X64-NEXT: vpmaskmovd (%rdi), %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x8c,0x07]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.maskload.d(i8* %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
ret <4 x i32> %res
}
@@ -1115,11 +1200,16 @@ declare <4 x i32> @llvm.x86.avx2.maskloa
define <8 x i32> @test_x86_avx2_maskload_d_256(i8* %a0, <8 x i32> %a1) {
-; CHECK-LABEL: test_x86_avx2_maskload_d_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpmaskmovd (%eax), %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x8c,0x00]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_maskload_d_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpmaskmovd (%eax), %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x8c,0x00]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_maskload_d_256:
+; X64: ## BB#0:
+; X64-NEXT: vpmaskmovd (%rdi), %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x8c,0x07]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.maskload.d.256(i8* %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -1127,11 +1217,16 @@ declare <8 x i32> @llvm.x86.avx2.maskloa
define void @test_x86_avx2_maskstore_q(i8* %a0, <2 x i64> %a1, <2 x i64> %a2) {
-; CHECK-LABEL: test_x86_avx2_maskstore_q:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpmaskmovq %xmm1, %xmm0, (%eax) ## encoding: [0xc4,0xe2,0xf9,0x8e,0x08]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_maskstore_q:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpmaskmovq %xmm1, %xmm0, (%eax) ## encoding: [0xc4,0xe2,0xf9,0x8e,0x08]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_maskstore_q:
+; X64: ## BB#0:
+; X64-NEXT: vpmaskmovq %xmm1, %xmm0, (%rdi) ## encoding: [0xc4,0xe2,0xf9,0x8e,0x0f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
call void @llvm.x86.avx2.maskstore.q(i8* %a0, <2 x i64> %a1, <2 x i64> %a2)
ret void
}
@@ -1139,12 +1234,18 @@ declare void @llvm.x86.avx2.maskstore.q(
define void @test_x86_avx2_maskstore_q_256(i8* %a0, <4 x i64> %a1, <4 x i64> %a2) {
-; CHECK-LABEL: test_x86_avx2_maskstore_q_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpmaskmovq %ymm1, %ymm0, (%eax) ## encoding: [0xc4,0xe2,0xfd,0x8e,0x08]
-; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_maskstore_q_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpmaskmovq %ymm1, %ymm0, (%eax) ## encoding: [0xc4,0xe2,0xfd,0x8e,0x08]
+; X86-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_maskstore_q_256:
+; X64: ## BB#0:
+; X64-NEXT: vpmaskmovq %ymm1, %ymm0, (%rdi) ## encoding: [0xc4,0xe2,0xfd,0x8e,0x0f]
+; X64-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
call void @llvm.x86.avx2.maskstore.q.256(i8* %a0, <4 x i64> %a1, <4 x i64> %a2)
ret void
}
@@ -1152,11 +1253,16 @@ declare void @llvm.x86.avx2.maskstore.q.
define void @test_x86_avx2_maskstore_d(i8* %a0, <4 x i32> %a1, <4 x i32> %a2) {
-; CHECK-LABEL: test_x86_avx2_maskstore_d:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpmaskmovd %xmm1, %xmm0, (%eax) ## encoding: [0xc4,0xe2,0x79,0x8e,0x08]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_maskstore_d:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpmaskmovd %xmm1, %xmm0, (%eax) ## encoding: [0xc4,0xe2,0x79,0x8e,0x08]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_maskstore_d:
+; X64: ## BB#0:
+; X64-NEXT: vpmaskmovd %xmm1, %xmm0, (%rdi) ## encoding: [0xc4,0xe2,0x79,0x8e,0x0f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
call void @llvm.x86.avx2.maskstore.d(i8* %a0, <4 x i32> %a1, <4 x i32> %a2)
ret void
}
@@ -1164,12 +1270,18 @@ declare void @llvm.x86.avx2.maskstore.d(
define void @test_x86_avx2_maskstore_d_256(i8* %a0, <8 x i32> %a1, <8 x i32> %a2) {
-; CHECK-LABEL: test_x86_avx2_maskstore_d_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpmaskmovd %ymm1, %ymm0, (%eax) ## encoding: [0xc4,0xe2,0x7d,0x8e,0x08]
-; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_maskstore_d_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpmaskmovd %ymm1, %ymm0, (%eax) ## encoding: [0xc4,0xe2,0x7d,0x8e,0x08]
+; X86-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_maskstore_d_256:
+; X64: ## BB#0:
+; X64-NEXT: vpmaskmovd %ymm1, %ymm0, (%rdi) ## encoding: [0xc4,0xe2,0x7d,0x8e,0x0f]
+; X64-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
call void @llvm.x86.avx2.maskstore.d.256(i8* %a0, <8 x i32> %a1, <8 x i32> %a2)
ret void
}
@@ -1180,12 +1292,12 @@ define <4 x i32> @test_x86_avx2_psllv_d(
; AVX2-LABEL: test_x86_avx2_psllv_d:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x47,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psllv_d:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsllvd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x47,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
ret <4 x i32> %res
}
@@ -1196,12 +1308,12 @@ define <8 x i32> @test_x86_avx2_psllv_d_
; AVX2-LABEL: test_x86_avx2_psllv_d_256:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x47,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psllv_d_256:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x47,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -1212,12 +1324,12 @@ define <2 x i64> @test_x86_avx2_psllv_q(
; AVX2-LABEL: test_x86_avx2_psllv_q:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsllvq %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0xf9,0x47,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psllv_q:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsllvq %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x47,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
ret <2 x i64> %res
}
@@ -1228,12 +1340,12 @@ define <4 x i64> @test_x86_avx2_psllv_q_
; AVX2-LABEL: test_x86_avx2_psllv_q_256:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsllvq %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0xfd,0x47,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psllv_q_256:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsllvq %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x47,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %a0, <4 x i64> %a1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -1244,12 +1356,12 @@ define <4 x i32> @test_x86_avx2_psrlv_d(
; AVX2-LABEL: test_x86_avx2_psrlv_d:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x45,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrlv_d:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x45,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
ret <4 x i32> %res
}
@@ -1260,12 +1372,12 @@ define <8 x i32> @test_x86_avx2_psrlv_d_
; AVX2-LABEL: test_x86_avx2_psrlv_d_256:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x45,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrlv_d_256:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x45,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -1276,12 +1388,12 @@ define <2 x i64> @test_x86_avx2_psrlv_q(
; AVX2-LABEL: test_x86_avx2_psrlv_q:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0xf9,0x45,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrlv_q:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x45,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
ret <2 x i64> %res
}
@@ -1292,12 +1404,12 @@ define <4 x i64> @test_x86_avx2_psrlv_q_
; AVX2-LABEL: test_x86_avx2_psrlv_q_256:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0xfd,0x45,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrlv_q_256:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x45,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %a0, <4 x i64> %a1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -1308,34 +1420,52 @@ define <4 x i32> @test_x86_avx2_psrav_d(
; AVX2-LABEL: test_x86_avx2_psrav_d:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsravd %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x46,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrav_d:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsravd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
ret <4 x i32> %res
}
define <4 x i32> @test_x86_avx2_psrav_d_const(<4 x i32> %a0, <4 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_psrav_d_const:
-; AVX2: ## BB#0:
-; AVX2-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,4294967284,23]
-; AVX2-NEXT: ## encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; AVX2-NEXT: ## fixup A - offset: 4, value: LCPI88_0, kind: FK_Data_4
-; AVX2-NEXT: vpsravd LCPI88_1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
-; AVX2-NEXT: ## fixup A - offset: 5, value: LCPI88_1, kind: FK_Data_4
-; AVX2-NEXT: retl ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psrav_d_const:
-; AVX512VL: ## BB#0:
-; AVX512VL-NEXT: vmovdqa LCPI88_0, %xmm0 ## EVEX TO VEX Compression xmm0 = [2,9,4294967284,23]
-; AVX512VL-NEXT: ## encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI88_0, kind: FK_Data_4
-; AVX512VL-NEXT: vpsravd LCPI88_1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
-; AVX512VL-NEXT: ## fixup A - offset: 5, value: LCPI88_1, kind: FK_Data_4
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psrav_d_const:
+; X86-AVX: ## BB#0:
+; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,4294967284,23]
+; X86-AVX-NEXT: ## encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
+; X86-AVX-NEXT: ## fixup A - offset: 4, value: LCPI88_0, kind: FK_Data_4
+; X86-AVX-NEXT: vpsravd LCPI88_1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
+; X86-AVX-NEXT: ## fixup A - offset: 5, value: LCPI88_1, kind: FK_Data_4
+; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psrav_d_const:
+; X86-AVX512VL: ## BB#0:
+; X86-AVX512VL-NEXT: vmovdqa LCPI88_0, %xmm0 ## EVEX TO VEX Compression xmm0 = [2,9,4294967284,23]
+; X86-AVX512VL-NEXT: ## encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI88_0, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vpsravd LCPI88_1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: ## fixup A - offset: 5, value: LCPI88_1, kind: FK_Data_4
+; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psrav_d_const:
+; X64-AVX: ## BB#0:
+; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,4294967284,23]
+; X64-AVX-NEXT: ## encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
+; X64-AVX-NEXT: ## fixup A - offset: 4, value: LCPI88_0-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
+; X64-AVX-NEXT: ## fixup A - offset: 5, value: LCPI88_1-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psrav_d_const:
+; X64-AVX512VL: ## BB#0:
+; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm0 ## EVEX TO VEX Compression xmm0 = [2,9,4294967284,23]
+; X64-AVX512VL-NEXT: ## encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI88_0-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: ## fixup A - offset: 5, value: LCPI88_1-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> <i32 2, i32 9, i32 -12, i32 23>, <4 x i32> <i32 1, i32 18, i32 35, i32 52>)
ret <4 x i32> %res
}
@@ -1345,45 +1475,68 @@ define <8 x i32> @test_x86_avx2_psrav_d_
; AVX2-LABEL: test_x86_avx2_psrav_d_256:
; AVX2: ## BB#0:
; AVX2-NEXT: vpsravd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x46,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
+; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
; AVX512VL-LABEL: test_x86_avx2_psrav_d_256:
; AVX512VL: ## BB#0:
; AVX512VL-NEXT: vpsravd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0xc1]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
define <8 x i32> @test_x86_avx2_psrav_d_256_const(<8 x i32> %a0, <8 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_psrav_d_256_const:
-; AVX2: ## BB#0:
-; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
-; AVX2-NEXT: ## encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; AVX2-NEXT: ## fixup A - offset: 4, value: LCPI90_0, kind: FK_Data_4
-; AVX2-NEXT: vpsravd LCPI90_1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
-; AVX2-NEXT: ## fixup A - offset: 5, value: LCPI90_1, kind: FK_Data_4
-; AVX2-NEXT: retl ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psrav_d_256_const:
-; AVX512VL: ## BB#0:
-; AVX512VL-NEXT: vmovdqa LCPI90_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
-; AVX512VL-NEXT: ## encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI90_0, kind: FK_Data_4
-; AVX512VL-NEXT: vpsravd LCPI90_1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
-; AVX512VL-NEXT: ## fixup A - offset: 5, value: LCPI90_1, kind: FK_Data_4
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psrav_d_256_const:
+; X86-AVX: ## BB#0:
+; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
+; X86-AVX-NEXT: ## encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
+; X86-AVX-NEXT: ## fixup A - offset: 4, value: LCPI90_0, kind: FK_Data_4
+; X86-AVX-NEXT: vpsravd LCPI90_1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
+; X86-AVX-NEXT: ## fixup A - offset: 5, value: LCPI90_1, kind: FK_Data_4
+; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psrav_d_256_const:
+; X86-AVX512VL: ## BB#0:
+; X86-AVX512VL-NEXT: vmovdqa LCPI90_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
+; X86-AVX512VL-NEXT: ## encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI90_0, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vpsravd LCPI90_1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: ## fixup A - offset: 5, value: LCPI90_1, kind: FK_Data_4
+; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psrav_d_256_const:
+; X64-AVX: ## BB#0:
+; X64-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
+; X64-AVX-NEXT: ## encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
+; X64-AVX-NEXT: ## fixup A - offset: 4, value: LCPI90_0-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
+; X64-AVX-NEXT: ## fixup A - offset: 5, value: LCPI90_1-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psrav_d_256_const:
+; X64-AVX512VL: ## BB#0:
+; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %ymm0 ## EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
+; X64-AVX512VL-NEXT: ## encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI90_0-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
+; X64-AVX512VL-NEXT: ## fixup A - offset: 5, value: LCPI90_1-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> <i32 2, i32 9, i32 -12, i32 23, i32 -26, i32 37, i32 -40, i32 51>, <8 x i32> <i32 1, i32 18, i32 35, i32 52, i32 69, i32 15, i32 32, i32 49>)
ret <8 x i32> %res
}
declare <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32>, <8 x i32>) nounwind readnone
define <2 x double> @test_x86_avx2_gather_d_pd(<2 x double> %a0, i8* %a1, <4 x i32> %idx, <2 x double> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_d_pd:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vgatherdpd %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x92,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_d_pd:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vgatherdpd %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x92,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_d_pd:
+; X64: ## BB#0:
+; X64-NEXT: vgatherdpd %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x92,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <2 x double> @llvm.x86.avx2.gather.d.pd(<2 x double> %a0,
i8* %a1, <4 x i32> %idx, <2 x double> %mask, i8 2) ;
ret <2 x double> %res
@@ -1392,11 +1545,16 @@ declare <2 x double> @llvm.x86.avx2.gath
<4 x i32>, <2 x double>, i8) nounwind readonly
define <4 x double> @test_x86_avx2_gather_d_pd_256(<4 x double> %a0, i8* %a1, <4 x i32> %idx, <4 x double> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_d_pd_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vgatherdpd %ymm2, (%eax,%xmm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x92,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_d_pd_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vgatherdpd %ymm2, (%eax,%xmm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x92,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_d_pd_256:
+; X64: ## BB#0:
+; X64-NEXT: vgatherdpd %ymm2, (%rdi,%xmm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x92,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double> %a0,
i8* %a1, <4 x i32> %idx, <4 x double> %mask, i8 2) ;
ret <4 x double> %res
@@ -1405,11 +1563,16 @@ declare <4 x double> @llvm.x86.avx2.gath
<4 x i32>, <4 x double>, i8) nounwind readonly
define <2 x double> @test_x86_avx2_gather_q_pd(<2 x double> %a0, i8* %a1, <2 x i64> %idx, <2 x double> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_q_pd:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vgatherqpd %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x93,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_q_pd:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vgatherqpd %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x93,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_q_pd:
+; X64: ## BB#0:
+; X64-NEXT: vgatherqpd %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x93,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <2 x double> @llvm.x86.avx2.gather.q.pd(<2 x double> %a0,
i8* %a1, <2 x i64> %idx, <2 x double> %mask, i8 2) ;
ret <2 x double> %res
@@ -1418,11 +1581,16 @@ declare <2 x double> @llvm.x86.avx2.gath
<2 x i64>, <2 x double>, i8) nounwind readonly
define <4 x double> @test_x86_avx2_gather_q_pd_256(<4 x double> %a0, i8* %a1, <4 x i64> %idx, <4 x double> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_q_pd_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vgatherqpd %ymm2, (%eax,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x93,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_q_pd_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vgatherqpd %ymm2, (%eax,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x93,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_q_pd_256:
+; X64: ## BB#0:
+; X64-NEXT: vgatherqpd %ymm2, (%rdi,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x93,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double> %a0,
i8* %a1, <4 x i64> %idx, <4 x double> %mask, i8 2) ;
ret <4 x double> %res
@@ -1431,11 +1599,16 @@ declare <4 x double> @llvm.x86.avx2.gath
<4 x i64>, <4 x double>, i8) nounwind readonly
define <4 x float> @test_x86_avx2_gather_d_ps(<4 x float> %a0, i8* %a1, <4 x i32> %idx, <4 x float> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_d_ps:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vgatherdps %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x92,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_d_ps:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vgatherdps %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x92,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_d_ps:
+; X64: ## BB#0:
+; X64-NEXT: vgatherdps %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x92,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float> %a0,
i8* %a1, <4 x i32> %idx, <4 x float> %mask, i8 2) ;
ret <4 x float> %res
@@ -1444,11 +1617,16 @@ declare <4 x float> @llvm.x86.avx2.gathe
<4 x i32>, <4 x float>, i8) nounwind readonly
define <8 x float> @test_x86_avx2_gather_d_ps_256(<8 x float> %a0, i8* %a1, <8 x i32> %idx, <8 x float> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_d_ps_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vgatherdps %ymm2, (%eax,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0x6d,0x92,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_d_ps_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vgatherdps %ymm2, (%eax,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0x6d,0x92,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_d_ps_256:
+; X64: ## BB#0:
+; X64-NEXT: vgatherdps %ymm2, (%rdi,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0x6d,0x92,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> %a0,
i8* %a1, <8 x i32> %idx, <8 x float> %mask, i8 2) ;
ret <8 x float> %res
@@ -1457,11 +1635,16 @@ declare <8 x float> @llvm.x86.avx2.gathe
<8 x i32>, <8 x float>, i8) nounwind readonly
define <4 x float> @test_x86_avx2_gather_q_ps(<4 x float> %a0, i8* %a1, <2 x i64> %idx, <4 x float> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_q_ps:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vgatherqps %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x93,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_q_ps:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vgatherqps %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x93,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_q_ps:
+; X64: ## BB#0:
+; X64-NEXT: vgatherqps %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x93,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x float> @llvm.x86.avx2.gather.q.ps(<4 x float> %a0,
i8* %a1, <2 x i64> %idx, <4 x float> %mask, i8 2) ;
ret <4 x float> %res
@@ -1470,12 +1653,18 @@ declare <4 x float> @llvm.x86.avx2.gathe
<2 x i64>, <4 x float>, i8) nounwind readonly
define <4 x float> @test_x86_avx2_gather_q_ps_256(<4 x float> %a0, i8* %a1, <4 x i64> %idx, <4 x float> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_q_ps_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vgatherqps %xmm2, (%eax,%ymm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x6d,0x93,0x04,0x48]
-; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_q_ps_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vgatherqps %xmm2, (%eax,%ymm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x6d,0x93,0x04,0x48]
+; X86-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_q_ps_256:
+; X64: ## BB#0:
+; X64-NEXT: vgatherqps %xmm2, (%rdi,%ymm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x6d,0x93,0x04,0x4f]
+; X64-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x float> @llvm.x86.avx2.gather.q.ps.256(<4 x float> %a0,
i8* %a1, <4 x i64> %idx, <4 x float> %mask, i8 2) ;
ret <4 x float> %res
@@ -1484,11 +1673,16 @@ declare <4 x float> @llvm.x86.avx2.gathe
<4 x i64>, <4 x float>, i8) nounwind readonly
define <2 x i64> @test_x86_avx2_gather_d_q(<2 x i64> %a0, i8* %a1, <4 x i32> %idx, <2 x i64> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_d_q:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpgatherdq %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x90,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_d_q:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpgatherdq %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x90,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_d_q:
+; X64: ## BB#0:
+; X64-NEXT: vpgatherdq %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x90,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx2.gather.d.q(<2 x i64> %a0,
i8* %a1, <4 x i32> %idx, <2 x i64> %mask, i8 2) ;
ret <2 x i64> %res
@@ -1497,11 +1691,16 @@ declare <2 x i64> @llvm.x86.avx2.gather.
<4 x i32>, <2 x i64>, i8) nounwind readonly
define <4 x i64> @test_x86_avx2_gather_d_q_256(<4 x i64> %a0, i8* %a1, <4 x i32> %idx, <4 x i64> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_d_q_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpgatherdq %ymm2, (%eax,%xmm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x90,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_d_q_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpgatherdq %ymm2, (%eax,%xmm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x90,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_d_q_256:
+; X64: ## BB#0:
+; X64-NEXT: vpgatherdq %ymm2, (%rdi,%xmm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x90,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64> %a0,
i8* %a1, <4 x i32> %idx, <4 x i64> %mask, i8 2) ;
ret <4 x i64> %res
@@ -1510,11 +1709,16 @@ declare <4 x i64> @llvm.x86.avx2.gather.
<4 x i32>, <4 x i64>, i8) nounwind readonly
define <2 x i64> @test_x86_avx2_gather_q_q(<2 x i64> %a0, i8* %a1, <2 x i64> %idx, <2 x i64> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_q_q:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpgatherqq %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x91,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_q_q:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpgatherqq %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x91,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_q_q:
+; X64: ## BB#0:
+; X64-NEXT: vpgatherqq %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x91,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64> %a0,
i8* %a1, <2 x i64> %idx, <2 x i64> %mask, i8 2) ;
ret <2 x i64> %res
@@ -1523,11 +1727,16 @@ declare <2 x i64> @llvm.x86.avx2.gather.
<2 x i64>, <2 x i64>, i8) nounwind readonly
define <4 x i64> @test_x86_avx2_gather_q_q_256(<4 x i64> %a0, i8* %a1, <4 x i64> %idx, <4 x i64> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_q_q_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpgatherqq %ymm2, (%eax,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x91,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_q_q_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpgatherqq %ymm2, (%eax,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x91,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_q_q_256:
+; X64: ## BB#0:
+; X64-NEXT: vpgatherqq %ymm2, (%rdi,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x91,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64> %a0,
i8* %a1, <4 x i64> %idx, <4 x i64> %mask, i8 2) ;
ret <4 x i64> %res
@@ -1536,11 +1745,16 @@ declare <4 x i64> @llvm.x86.avx2.gather.
<4 x i64>, <4 x i64>, i8) nounwind readonly
define <4 x i32> @test_x86_avx2_gather_d_d(<4 x i32> %a0, i8* %a1, <4 x i32> %idx, <4 x i32> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_d_d:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpgatherdd %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x90,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_d_d:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpgatherdd %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x90,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_d_d:
+; X64: ## BB#0:
+; X64-NEXT: vpgatherdd %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x90,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.gather.d.d(<4 x i32> %a0,
i8* %a1, <4 x i32> %idx, <4 x i32> %mask, i8 2) ;
ret <4 x i32> %res
@@ -1549,11 +1763,16 @@ declare <4 x i32> @llvm.x86.avx2.gather.
<4 x i32>, <4 x i32>, i8) nounwind readonly
define <8 x i32> @test_x86_avx2_gather_d_d_256(<8 x i32> %a0, i8* %a1, <8 x i32> %idx, <8 x i32> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_d_d_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpgatherdd %ymm2, (%eax,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0x6d,0x90,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_d_d_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpgatherdd %ymm2, (%eax,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0x6d,0x90,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_d_d_256:
+; X64: ## BB#0:
+; X64-NEXT: vpgatherdd %ymm2, (%rdi,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0x6d,0x90,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.gather.d.d.256(<8 x i32> %a0,
i8* %a1, <8 x i32> %idx, <8 x i32> %mask, i8 2) ;
ret <8 x i32> %res
@@ -1562,11 +1781,16 @@ declare <8 x i32> @llvm.x86.avx2.gather.
<8 x i32>, <8 x i32>, i8) nounwind readonly
define <4 x i32> @test_x86_avx2_gather_q_d(<4 x i32> %a0, i8* %a1, <2 x i64> %idx, <4 x i32> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_q_d:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpgatherqd %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x91,0x04,0x48]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_q_d:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpgatherqd %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x91,0x04,0x48]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_q_d:
+; X64: ## BB#0:
+; X64-NEXT: vpgatherqd %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x91,0x04,0x4f]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.gather.q.d(<4 x i32> %a0,
i8* %a1, <2 x i64> %idx, <4 x i32> %mask, i8 2) ;
ret <4 x i32> %res
@@ -1575,12 +1799,18 @@ declare <4 x i32> @llvm.x86.avx2.gather.
<2 x i64>, <4 x i32>, i8) nounwind readonly
define <4 x i32> @test_x86_avx2_gather_q_d_256(<4 x i32> %a0, i8* %a1, <4 x i64> %idx, <4 x i32> %mask) {
-; CHECK-LABEL: test_x86_avx2_gather_q_d_256:
-; CHECK: ## BB#0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; CHECK-NEXT: vpgatherqd %xmm2, (%eax,%ymm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x6d,0x91,0x04,0x48]
-; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
-; CHECK-NEXT: retl ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_gather_q_d_256:
+; X86: ## BB#0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
+; X86-NEXT: vpgatherqd %xmm2, (%eax,%ymm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x6d,0x91,0x04,0x48]
+; X86-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_gather_q_d_256:
+; X64: ## BB#0:
+; X64-NEXT: vpgatherqd %xmm2, (%rdi,%ymm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x6d,0x91,0x04,0x4f]
+; X64-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.gather.q.d.256(<4 x i32> %a0,
i8* %a1, <4 x i64> %idx, <4 x i32> %mask, i8 2) ;
ret <4 x i32> %res
@@ -1591,23 +1821,37 @@ declare <4 x i32> @llvm.x86.avx2.gather.
; PR13298
define <8 x float> @test_gather_mask(<8 x float> %a0, float* %a, <8 x i32> %idx, <8 x float> %mask, float* nocapture %out) {
;; gather with mask
-; AVX2-LABEL: test_gather_mask:
-; AVX2: ## BB#0:
-; AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08]
-; AVX2-NEXT: movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x04]
-; AVX2-NEXT: vmovaps %ymm2, %ymm3 ## encoding: [0xc5,0xfc,0x28,0xda]
-; AVX2-NEXT: vgatherdps %ymm3, (%ecx,%ymm1,4), %ymm0 ## encoding: [0xc4,0xe2,0x65,0x92,0x04,0x89]
-; AVX2-NEXT: vmovups %ymm2, (%eax) ## encoding: [0xc5,0xfc,0x11,0x10]
-; AVX2-NEXT: retl ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_gather_mask:
-; AVX512VL: ## BB#0:
-; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08]
-; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x04]
-; AVX512VL-NEXT: vmovaps %ymm2, %ymm3 ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xda]
-; AVX512VL-NEXT: vgatherdps %ymm3, (%ecx,%ymm1,4), %ymm0 ## encoding: [0xc4,0xe2,0x65,0x92,0x04,0x89]
-; AVX512VL-NEXT: vmovups %ymm2, (%eax) ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x11,0x10]
-; AVX512VL-NEXT: retl ## encoding: [0xc3]
+; X86-AVX-LABEL: test_gather_mask:
+; X86-AVX: ## BB#0:
+; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08]
+; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x04]
+; X86-AVX-NEXT: vmovaps %ymm2, %ymm3 ## encoding: [0xc5,0xfc,0x28,0xda]
+; X86-AVX-NEXT: vgatherdps %ymm3, (%ecx,%ymm1,4), %ymm0 ## encoding: [0xc4,0xe2,0x65,0x92,0x04,0x89]
+; X86-AVX-NEXT: vmovups %ymm2, (%eax) ## encoding: [0xc5,0xfc,0x11,0x10]
+; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_gather_mask:
+; X86-AVX512VL: ## BB#0:
+; X86-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08]
+; X86-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x04]
+; X86-AVX512VL-NEXT: vmovaps %ymm2, %ymm3 ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xda]
+; X86-AVX512VL-NEXT: vgatherdps %ymm3, (%ecx,%ymm1,4), %ymm0 ## encoding: [0xc4,0xe2,0x65,0x92,0x04,0x89]
+; X86-AVX512VL-NEXT: vmovups %ymm2, (%eax) ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x11,0x10]
+; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_gather_mask:
+; X64-AVX: ## BB#0:
+; X64-AVX-NEXT: vmovaps %ymm2, %ymm3 ## encoding: [0xc5,0xfc,0x28,0xda]
+; X64-AVX-NEXT: vgatherdps %ymm3, (%rdi,%ymm1,4), %ymm0 ## encoding: [0xc4,0xe2,0x65,0x92,0x04,0x8f]
+; X64-AVX-NEXT: vmovups %ymm2, (%rsi) ## encoding: [0xc5,0xfc,0x11,0x16]
+; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_gather_mask:
+; X64-AVX512VL: ## BB#0:
+; X64-AVX512VL-NEXT: vmovaps %ymm2, %ymm3 ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xda]
+; X64-AVX512VL-NEXT: vgatherdps %ymm3, (%rdi,%ymm1,4), %ymm0 ## encoding: [0xc4,0xe2,0x65,0x92,0x04,0x8f]
+; X64-AVX512VL-NEXT: vmovups %ymm2, (%rsi) ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x11,0x16]
+; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%a_i8 = bitcast float* %a to i8*
%res = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> %a0,
i8* %a_i8, <8 x i32> %idx, <8 x float> %mask, i8 4) ;
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