[PATCH] D39171: AMDGPU: Handle s_buffer_load_dword hazard on SI

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle added inline comments.


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Comment at: lib/Target/AMDGPU/GCNHazardRecognizer.cpp:347-374
+  // This fixes what appears to be undocumented hardware behavior in SI where
+  // s_mov writing a descriptor and s_buffer_load_dword reading the descriptor
+  // needs some number of nops in between. We don't know how many we need, but
+  // let's use 4. This wasn't discovered before probably because the only
+  // case when this happens is when we expand a 64-bit pointer into a full
+  // descriptor and use s_buffer_load_dword instead of s_load_dword, which was
+  // probably never encountered in the closed-source land.
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This could be merged with the previous loop, right?


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Comment at: test/CodeGen/AMDGPU/smrd.ll:93
+; GCN-DAG: s_mov_b32 s0, 0
+; SI-NEXT: nop 3
+; GCN-NEXT: s_buffer_load_dword s0, s[0:3], 0x0
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Please add a NOTSI-NOT-NEXT line as well (or CIVIGFX9-NOT-NEXT?)


https://reviews.llvm.org/D39171