[PATCH] D39123: [mips] Fix (dis)assembly of abs.fmt for micromips

[Simon Dardis via Phabricator via llvm-commits]

sdardis created this revision.
Herald added a subscriber: arichardson.

These instructions were previously marked as codegen only preventing
them from being assembled as microMIPS or disassembled.


https://reviews.llvm.org/D39123

Files:
  lib/Target/Mips/MicroMipsInstrFPU.td
  lib/Target/Mips/MipsInstrFPU.td
  test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
  test/MC/Disassembler/Mips/micromips32r3/valid.txt
  test/MC/Mips/micromips/valid.s


Index: test/MC/Mips/micromips/valid.s
===================================================================
--- test/MC/Mips/micromips/valid.s
+++ test/MC/Mips/micromips/valid.s
@@ -49,6 +49,10 @@
 lw $3, 32($sp)              # CHECK: lw $3, 32($sp)     # encoding: [0x48,0x68]
 sw $4, 124($sp)             # CHECK: sw $4, 124($sp)    # encoding: [0xc8,0x9f]
 lw $3, 32($gp)              # CHECK: lw $3, 32($gp)     # encoding: [0x65,0x88]
+abs.s $f0, $f2              # CHECK:  abs.s $f0, $f2    # encoding: [0x54,0x02,0x03,0x7b]
+                            # CHECK-NEXT:               # <MCInst #{{[0-9]+}} FABS_S_MM
+abs.d $f4, $f6              # CHECK:  abs.d $f4, $f6    # encoding: [0x54,0x86,0x23,0x7b]
+                            # CHECK-NEXT:               # <MCInst #{{[0-9]+}} FABS_MM
 add $9, $6, $7              # CHECK: add $9, $6, $7         # encoding: [0x00,0xe6,0x49,0x10]
 addi $9, $6, 17767          # CHECK: addi $9, $6, 17767     # encoding: [0x11,0x26,0x45,0x67]
 addiu $9, $6, -15001        # CHECK: addiu $9, $6, -15001   # encoding: [0x31,0x26,0xc5,0x67]
Index: test/MC/Disassembler/Mips/micromips32r3/valid.txt
===================================================================
--- test/MC/Disassembler/Mips/micromips32r3/valid.txt
+++ test/MC/Disassembler/Mips/micromips32r3/valid.txt
@@ -49,6 +49,8 @@
 0x46 0x88 # CHECK: break16 8
 0x46 0xce # CHECK: sdbbp16 14
 0x84 0x34 # CHECK: movep $5, $6, $2, $3
+0x54 0x40 0x03 0x7b # CHECK: abs.s $f2, $f0
+0x54 0x40 0x23 0x7b # CHECK: abs.d $f2, $f0
 0x00 0xe6 0x49 0x10 # CHECK: add $9, $6, $7
 0x11 0x26 0x45 0x67 # CHECK: addi $9, $6, 17767
 0x31 0x26 0xc5 0x67 # CHECK: addiu $9, $6, -15001
Index: test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
===================================================================
--- test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
+++ test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
@@ -49,6 +49,8 @@
 0x88 0x46 # CHECK: break16 8
 0xce 0x46 # CHECK: sdbbp16 14
 0x34 0x84 # CHECK: movep $5, $6, $2, $3
+0x40 0x54 0x7b 0x03 # CHECK: abs.s $f2, $f0
+0x40 0x54 0x7b 0x23 # CHECK: abs.d $f2, $f0
 0xe6 0x00 0x10 0x49 # CHECK: add $9, $6, $7
 0x26 0x11 0x67 0x45 # CHECK: addi $9, $6, 17767
 0x26 0x31 0x67 0xc5 # CHECK: addiu $9, $6, -15001
Index: lib/Target/Mips/MipsInstrFPU.td
===================================================================
--- lib/Target/Mips/MipsInstrFPU.td
+++ lib/Target/Mips/MipsInstrFPU.td
@@ -448,11 +448,14 @@
   def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
 }
 
-def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
-             ABSS_FM<0x5, 16>;
+let AdditionalPredicates = [NotInMicroMips] in {
+  def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
+               ABSS_FM<0x5, 16>;
+  defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>;
+}
+
 def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
              ABSS_FM<0x7, 16>;
-defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>;
 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>;
 
 def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,
Index: lib/Target/Mips/MicroMipsInstrFPU.td
===================================================================
--- lib/Target/Mips/MicroMipsInstrFPU.td
+++ lib/Target/Mips/MicroMipsInstrFPU.td
@@ -95,8 +95,16 @@
 def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
                    ROUND_W_FM_MM<1, 0x4>, ISA_MICROMIPS, FGR_64;
 
-def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
-                ABS_FM_MM<0, 0xd>, ISA_MICROMIPS;
+}
+
+let DecoderNamespace = "MicroMips" in {
+  def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
+                  ABS_FM_MM<0, 0xd>, ISA_MICROMIPS;
+  def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, II_ABS, fabs>,
+                ABS_FM_MM<1, 0xd>, ISA_MICROMIPS, FGR_32;
+}
+
+let isCodeGenOnly = 1 in {
 def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
                 ABS_FM_MM<0, 0x1>, ISA_MICROMIPS;
 def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
@@ -110,8 +118,6 @@
 def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
                  ABS_FM_MM<1, 0x6d>, ISA_MICROMIPS;
 
-def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, II_ABS, fabs>,
-              ABS_FM_MM<1, 0xd>, ISA_MICROMIPS, FGR_32;
 def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>,
               ABS_FM_MM<1, 0x2d>, ISA_MICROMIPS, FGR_32;
 


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