[llvm] r316170 - [Hexagon] Fix store conversion from rr to io in optimize addressing modes

Krzysztof Parzyszek via llvm-commits llvm-commits at lists.llvm.org
Thu Oct 19 09:59:22 PDT 2017


Author: kparzysz
Date: Thu Oct 19 09:59:22 2017
New Revision: 316170

URL: http://llvm.org/viewvc/llvm-project?rev=316170&view=rev
Log:
[Hexagon] Fix store conversion from rr to io in optimize addressing modes

Added:
    llvm/trunk/test/CodeGen/Hexagon/addrmode-rr-to-io.mir
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp?rev=316170&r1=316169&r2=316170&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp Thu Oct 19 09:59:22 2017
@@ -361,7 +361,7 @@ bool HexagonOptAddrMode::changeLoad(Mach
       Changed = false;
 
     DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
-    DEBUG(dbgs() << "[TO]: " << MIB << "\n");
+    DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
   } else if (ImmOpNum == 2 && OldMI->getOperand(3).getImm() == 0) {
     short NewOpCode = HII->changeAddrMode_rr_io(*OldMI);
     assert(NewOpCode >= 0 && "Invalid New opcode\n");
@@ -372,7 +372,7 @@ bool HexagonOptAddrMode::changeLoad(Mach
     OpStart = 4;
     Changed = true;
     DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
-    DEBUG(dbgs() << "[TO]: " << MIB << "\n");
+    DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
   }
 
   if (Changed)
@@ -414,18 +414,17 @@ bool HexagonOptAddrMode::changeStore(Mac
     }
     Changed = true;
     DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
-    DEBUG(dbgs() << "[TO]: " << MIB << "\n");
+    DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
   } else if (ImmOpNum == 1 && OldMI->getOperand(2).getImm() == 0) {
     short NewOpCode = HII->changeAddrMode_rr_io(*OldMI);
     assert(NewOpCode >= 0 && "Invalid New opcode\n");
     MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
     MIB.add(OldMI->getOperand(0));
     MIB.add(ImmOp);
-    MIB.add(OldMI->getOperand(1));
-    OpStart = 2;
+    OpStart = 3;
     Changed = true;
     DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
-    DEBUG(dbgs() << "[TO]: " << MIB << "\n");
+    DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
   }
   if (Changed)
     for (unsigned i = OpStart; i < OpEnd; ++i)

Added: llvm/trunk/test/CodeGen/Hexagon/addrmode-rr-to-io.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/addrmode-rr-to-io.mir?rev=316170&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/addrmode-rr-to-io.mir (added)
+++ llvm/trunk/test/CodeGen/Hexagon/addrmode-rr-to-io.mir Thu Oct 19 09:59:22 2017
@@ -0,0 +1,22 @@
+# RUN: llc -march=hexagon -run-pass amode-opt %s -o - | FileCheck %s
+
+# This testcase used to crash.
+# CHECK: S2_storerb_io killed %r0, @var_i8, killed %r2
+
+--- |
+  define void @fred() { ret void }
+  @var_i8 = global [10 x i8] zeroinitializer, align 8
+...
+
+---
+name: fred
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: %r0
+      %r1 = A2_tfrsi @var_i8
+      %r2 = A2_tfrsi 255
+      S4_storerb_rr killed %r0, killed %r1, 0, killed %r2
+      PS_jmpret %r31, implicit-def %pc
+...
+




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