[PATCH] D39087: [AArch64][SVE] Asm: Extend EnforceVectorSubVectorTypeIs to distinguish Scalable Vectors

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
Herald added subscribers: kristof.beyls, tschuett, aemerson.

Patch [1/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions.


https://reviews.llvm.org/D39087

Files:
  utils/TableGen/CodeGenDAGPatterns.cpp


Index: utils/TableGen/CodeGenDAGPatterns.cpp
===================================================================
--- utils/TableGen/CodeGenDAGPatterns.cpp
+++ utils/TableGen/CodeGenDAGPatterns.cpp
@@ -603,6 +603,11 @@
   auto IsSubVec = [](MVT B, MVT P) -> bool {
     if (!B.isVector() || !P.isVector())
       return false;
+    // Logically a <4 x i32> is a valid subvector of <n x 4 x i32>
+    // but until there are obvious use-cases for this, keep the
+    // types separate.
+    if (B.isScalableVector() != P.isScalableVector())
+      return false;
     if (B.getVectorElementType() != P.getVectorElementType())
       return false;
     return B.getVectorNumElements() < P.getVectorNumElements();


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D39087.119566.patch
Type: text/x-patch
Size: 708 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20171019/70fa80fd/attachment.bin>