[llvm] r316099 - [Hexagon] Update Hexagon ArchEnum and sync some downstream changes(NFC)
Sumanth Gundapaneni via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 18 10:45:22 PDT 2017
Author: sgundapa
Date: Wed Oct 18 10:45:22 2017
New Revision: 316099
URL: http://llvm.org/viewvc/llvm-project?rev=316099&view=rev
Log:
[Hexagon] Update Hexagon ArchEnum and sync some downstream changes(NFC)
Differential Revision: https://reviews.llvm.org/D38850
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonDepArch.h
llvm/trunk/lib/Target/Hexagon/HexagonDepArch.td
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h
Modified: llvm/trunk/lib/Target/Hexagon/HexagonDepArch.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonDepArch.h?rev=316099&r1=316098&r2=316099&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonDepArch.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonDepArch.h Wed Oct 18 10:45:22 2017
@@ -7,4 +7,11 @@
//
//===----------------------------------------------------------------------===//
-enum HexagonArchEnum { V4,V5,V55,V60,V62 };
+#ifndef HEXAGON_DEP_ARCH_H
+#define HEXAGON_DEP_ARCH_H
+namespace llvm {
+namespace Hexagon {
+enum class ArchEnum { V4, V5, V55, V60, V62 };
+} // namespace Hexagon
+} // namespace llvm
+#endif // HEXAGON_DEP_ARCH_H
Modified: llvm/trunk/lib/Target/Hexagon/HexagonDepArch.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonDepArch.td?rev=316099&r1=316098&r2=316099&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonDepArch.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonDepArch.td Wed Oct 18 10:45:22 2017
@@ -7,13 +7,13 @@
//
//===----------------------------------------------------------------------===//
-def ArchV62: SubtargetFeature<"v62", "HexagonArchVersion", "V62", "Enable Hexagon V62 architecture">;
+def ArchV62: SubtargetFeature<"v62", "HexagonArchVersion", "Hexagon::ArchEnum::V62", "Enable Hexagon V62 architecture">;
def HasV62T : Predicate<"HST->hasV62TOps()">, AssemblerPredicate<"ArchV62">;
-def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "V60", "Enable Hexagon V60 architecture">;
+def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "Hexagon::ArchEnum::V60", "Enable Hexagon V60 architecture">;
def HasV60T : Predicate<"HST->hasV60TOps()">, AssemblerPredicate<"ArchV60">;
-def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "V55", "Enable Hexagon V55 architecture">;
+def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "Hexagon::ArchEnum::V55", "Enable Hexagon V55 architecture">;
def HasV55T : Predicate<"HST->hasV55TOps()">, AssemblerPredicate<"ArchV55">;
-def ArchV4: SubtargetFeature<"v4", "HexagonArchVersion", "V4", "Enable Hexagon V4 architecture">;
+def ArchV4: SubtargetFeature<"v4", "HexagonArchVersion", "Hexagon::ArchEnum::V4", "Enable Hexagon V4 architecture">;
def HasV4T : Predicate<"HST->hasV4TOps()">, AssemblerPredicate<"ArchV4">;
-def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "V5", "Enable Hexagon V5 architecture">;
+def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "Hexagon::ArchEnum::V5", "Enable Hexagon V5 architecture">;
def HasV5T : Predicate<"HST->hasV5TOps()">, AssemblerPredicate<"ArchV5">;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=316099&r1=316098&r2=316099&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Wed Oct 18 10:45:22 2017
@@ -356,10 +356,8 @@ static bool CC_HexagonVector(unsigned Va
};
auto &MF = State.getMachineFunction();
auto &HST = MF.getSubtarget<HexagonSubtarget>();
- bool UseHVX = HST.useHVXOps();
- bool UseHVXDbl = HST.useHVXDblOps();
- if ((UseHVX && !UseHVXDbl) &&
+ if (HST.useHVXSglOps() &&
(LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
LocVT == MVT::v64i8 || LocVT == MVT::v512i1)) {
if (unsigned Reg = State.AllocateReg(VecLstS)) {
@@ -370,9 +368,8 @@ static bool CC_HexagonVector(unsigned Va
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
return false;
}
- if ((UseHVX && !UseHVXDbl) &&
- (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
- LocVT == MVT::v128i8)) {
+ if (HST.useHVXSglOps() && (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 ||
+ LocVT == MVT::v64i16 || LocVT == MVT::v128i8)) {
if (unsigned Reg = State.AllocateReg(VecLstD)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
@@ -381,9 +378,9 @@ static bool CC_HexagonVector(unsigned Va
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
return false;
}
- if ((UseHVX && UseHVXDbl) &&
- (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 ||
- LocVT == MVT::v256i8)) {
+ // 128B Mode
+ if (HST.useHVXDblOps() && (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 ||
+ LocVT == MVT::v128i16 || LocVT == MVT::v256i8)) {
if (unsigned Reg = State.AllocateReg(VecLstD)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
@@ -392,7 +389,7 @@ static bool CC_HexagonVector(unsigned Va
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
return false;
}
- if ((UseHVX && UseHVXDbl) &&
+ if (HST.useHVXDblOps() &&
(LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) {
if (unsigned Reg = State.AllocateReg(VecLstS)) {
@@ -411,8 +408,6 @@ static bool RetCC_Hexagon(unsigned ValNo
ISD::ArgFlagsTy ArgFlags, CCState &State) {
auto &MF = State.getMachineFunction();
auto &HST = MF.getSubtarget<HexagonSubtarget>();
- bool UseHVX = HST.useHVXOps();
- bool UseHVXDbl = HST.useHVXDblOps();
if (LocVT == MVT::i1) {
// Return values of type MVT::i1 still need to be assigned to R0, but
@@ -442,7 +437,7 @@ static bool RetCC_Hexagon(unsigned ValNo
LocInfo = CCValAssign::Full;
} else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 ||
LocVT == MVT::v32i32 || LocVT == MVT::v16i64 ||
- (LocVT == MVT::v1024i1 && UseHVX && UseHVXDbl)) {
+ (LocVT == MVT::v1024i1 && HST.useHVXDblOps())) {
LocVT = MVT::v32i32;
ValVT = MVT::v32i32;
LocInfo = CCValAssign::Full;
@@ -505,8 +500,6 @@ static bool RetCC_HexagonVector(unsigned
ISD::ArgFlagsTy ArgFlags, CCState &State) {
auto &MF = State.getMachineFunction();
auto &HST = MF.getSubtarget<HexagonSubtarget>();
- bool UseHVX = HST.useHVXOps();
- bool UseHVXDbl = HST.useHVXDblOps();
if (LocVT == MVT::v16i32) {
if (unsigned Reg = State.AllocateReg(Hexagon::V0)) {
@@ -514,7 +507,7 @@ static bool RetCC_HexagonVector(unsigned
return false;
}
} else if (LocVT == MVT::v32i32) {
- unsigned Req = (UseHVX && UseHVXDbl) ? Hexagon::V0 : Hexagon::W0;
+ unsigned Req = HST.useHVXDblOps() ? Hexagon::V0 : Hexagon::W0;
if (unsigned Reg = State.AllocateReg(Req)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
@@ -946,14 +939,12 @@ static bool getIndexedAddressParts(SDNod
return false;
auto &HST = static_cast<const HexagonSubtarget&>(DAG.getSubtarget());
- bool UseHVX = HST.useHVXOps();
- bool UseHVXDbl = HST.useHVXDblOps();
bool ValidHVXDblType =
- (UseHVX && UseHVXDbl) && (VT == MVT::v32i32 || VT == MVT::v16i64 ||
- VT == MVT::v64i16 || VT == MVT::v128i8);
+ HST.useHVXDblOps() && (VT == MVT::v32i32 || VT == MVT::v16i64 ||
+ VT == MVT::v64i16 || VT == MVT::v128i8);
bool ValidHVXType =
- UseHVX && !UseHVXDbl && (VT == MVT::v16i32 || VT == MVT::v8i64 ||
+ HST.useHVXSglOps() && (VT == MVT::v16i32 || VT == MVT::v8i64 ||
VT == MVT::v32i16 || VT == MVT::v64i8);
if (ValidHVXDblType || ValidHVXType ||
@@ -1143,7 +1134,6 @@ SDValue HexagonTargetLowering::LowerForm
// callee return the result direclty through R0/R1.
SmallVector<SDValue, 8> MemOps;
- bool UseHVX = Subtarget.useHVXOps(), UseHVXDbl = Subtarget.useHVXDblOps();
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
@@ -1192,9 +1182,9 @@ SDValue HexagonTargetLowering::LowerForm
RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
- } else if (UseHVX && UseHVXDbl &&
- ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||
- RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) {
+ } else if (Subtarget.useHVXDblOps() &&
+ ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||
+ RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) {
unsigned VReg =
RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
@@ -1207,9 +1197,9 @@ SDValue HexagonTargetLowering::LowerForm
RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
- } else if (UseHVX && UseHVXDbl &&
- ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 ||
- RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) {
+ } else if (Subtarget.useHVXDblOps() &&
+ ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 ||
+ RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) {
unsigned VReg =
RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
@@ -1709,9 +1699,6 @@ HexagonTargetLowering::HexagonTargetLowe
Subtarget(ST) {
bool IsV4 = !Subtarget.hasV5TOps();
auto &HRI = *Subtarget.getRegisterInfo();
- bool UseHVX = Subtarget.useHVXOps();
- bool UseHVXSgl = Subtarget.useHVXSglOps();
- bool UseHVXDbl = Subtarget.useHVXDblOps();
setPrefLoopAlignment(4);
setPrefFunctionAlignment(4);
@@ -2004,8 +1991,8 @@ HexagonTargetLowering::HexagonTargetLowe
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
- if (UseHVX) {
- if (UseHVXSgl) {
+ if (Subtarget.useHVXOps()) {
+ if (Subtarget.useHVXSglOps()) {
setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i8, Custom);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i16, Custom);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i32, Custom);
@@ -2017,7 +2004,7 @@ HexagonTargetLowering::HexagonTargetLowe
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v64i8, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i16, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i32, Custom);
- } else if (UseHVXDbl) {
+ } else if (Subtarget.useHVXDblOps()) {
setOperationAction(ISD::CONCAT_VECTORS, MVT::v256i8, Custom);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i16, Custom);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i32, Custom);
@@ -2095,13 +2082,13 @@ HexagonTargetLowering::HexagonTargetLowe
setIndexedStoreAction(ISD::POST_INC, VT, Legal);
}
- if (UseHVXSgl) {
+ if (Subtarget.useHVXSglOps()) {
for (MVT VT : {MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64,
MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64}) {
setIndexedLoadAction(ISD::POST_INC, VT, Legal);
setIndexedStoreAction(ISD::POST_INC, VT, Legal);
}
- } else if (UseHVXDbl) {
+ } else if (Subtarget.useHVXDblOps()) {
for (MVT VT : {MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64,
MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v32i64}) {
setIndexedLoadAction(ISD::POST_INC, VT, Legal);
@@ -2977,7 +2964,6 @@ HexagonTargetLowering::getConstraintType
std::pair<unsigned, const TargetRegisterClass*>
HexagonTargetLowering::getRegForInlineAsmConstraint(
const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
- bool UseHVX = Subtarget.useHVXOps(), UseHVXDbl = Subtarget.useHVXDblOps();
if (Constraint.size() == 1) {
switch (Constraint[0]) {
@@ -3015,7 +3001,7 @@ HexagonTargetLowering::getRegForInlineAs
case 512:
return std::make_pair(0U, &Hexagon::HvxVRRegClass);
case 1024:
- if (Subtarget.hasV60TOps() && UseHVX && UseHVXDbl)
+ if (Subtarget.hasV60TOps() && Subtarget.useHVXDblOps())
return std::make_pair(0U, &Hexagon::HvxVRRegClass);
return std::make_pair(0U, &Hexagon::HvxWRRegClass);
case 2048:
Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp?rev=316099&r1=316098&r2=316099&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp Wed Oct 18 10:45:22 2017
@@ -118,11 +118,11 @@ HexagonRegisterInfo::getCalleeSavedRegs(
bool HasEHReturn = MF->getInfo<HexagonMachineFunctionInfo>()->hasEHReturn();
switch (MF->getSubtarget<HexagonSubtarget>().getHexagonArchVersion()) {
- case HexagonSubtarget::V4:
- case HexagonSubtarget::V5:
- case HexagonSubtarget::V55:
- case HexagonSubtarget::V60:
- case HexagonSubtarget::V62:
+ case Hexagon::ArchEnum::V4:
+ case Hexagon::ArchEnum::V5:
+ case Hexagon::ArchEnum::V55:
+ case Hexagon::ArchEnum::V60:
+ case Hexagon::ArchEnum::V62:
return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3;
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp?rev=316099&r1=316098&r2=316099&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp Wed Oct 18 10:45:22 2017
@@ -112,12 +112,12 @@ HexagonSubtarget::HexagonSubtarget(const
HexagonSubtarget &
HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
- static std::map<StringRef, HexagonArchEnum> CpuTable {
- { "hexagonv4", V4 },
- { "hexagonv5", V5 },
- { "hexagonv55", V55 },
- { "hexagonv60", V60 },
- { "hexagonv62", V62 },
+ static std::map<StringRef, Hexagon::ArchEnum> CpuTable{
+ {"hexagonv4", Hexagon::ArchEnum::V4},
+ {"hexagonv5", Hexagon::ArchEnum::V5},
+ {"hexagonv55", Hexagon::ArchEnum::V55},
+ {"hexagonv60", Hexagon::ArchEnum::V60},
+ {"hexagonv62", Hexagon::ArchEnum::V62},
};
auto FoundIt = CpuTable.find(CPUString);
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h?rev=316099&r1=316098&r2=316099&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h Wed Oct 18 10:45:22 2017
@@ -14,9 +14,10 @@
#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
#define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
+#include "HexagonDepArch.h"
#include "HexagonFrameLowering.h"
-#include "HexagonInstrInfo.h"
#include "HexagonISelLowering.h"
+#include "HexagonInstrInfo.h"
#include "HexagonRegisterInfo.h"
#include "HexagonSelectionDAGInfo.h"
#include "llvm/ADT/SmallSet.h"
@@ -50,9 +51,7 @@ class HexagonSubtarget : public HexagonG
bool ModeIEEERndNear;
public:
-#include "HexagonDepArch.h"
-
- HexagonArchEnum HexagonArchVersion;
+ Hexagon::ArchEnum HexagonArchVersion;
/// True if the target should use Back-Skip-Back scheduling. This is the
/// default for V60.
bool UseBSBScheduling;
@@ -113,14 +112,30 @@ public:
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool useMemOps() const { return UseMemOps; }
- bool hasV5TOps() const { return getHexagonArchVersion() >= V5; }
- bool hasV5TOpsOnly() const { return getHexagonArchVersion() == V5; }
- bool hasV55TOps() const { return getHexagonArchVersion() >= V55; }
- bool hasV55TOpsOnly() const { return getHexagonArchVersion() == V55; }
- bool hasV60TOps() const { return getHexagonArchVersion() >= V60; }
- bool hasV60TOpsOnly() const { return getHexagonArchVersion() == V60; }
- bool hasV62TOps() const { return getHexagonArchVersion() >= V62; }
- bool hasV62TOpsOnly() const { return getHexagonArchVersion() == V62; }
+ bool hasV5TOps() const {
+ return getHexagonArchVersion() >= Hexagon::ArchEnum::V5;
+ }
+ bool hasV5TOpsOnly() const {
+ return getHexagonArchVersion() == Hexagon::ArchEnum::V5;
+ }
+ bool hasV55TOps() const {
+ return getHexagonArchVersion() >= Hexagon::ArchEnum::V55;
+ }
+ bool hasV55TOpsOnly() const {
+ return getHexagonArchVersion() == Hexagon::ArchEnum::V55;
+ }
+ bool hasV60TOps() const {
+ return getHexagonArchVersion() >= Hexagon::ArchEnum::V60;
+ }
+ bool hasV60TOpsOnly() const {
+ return getHexagonArchVersion() == Hexagon::ArchEnum::V60;
+ }
+ bool hasV62TOps() const {
+ return getHexagonArchVersion() >= Hexagon::ArchEnum::V62;
+ }
+ bool hasV62TOpsOnly() const {
+ return getHexagonArchVersion() == Hexagon::ArchEnum::V62;
+ }
bool modeIEEERndNear() const { return ModeIEEERndNear; }
bool useHVXOps() const { return UseHVXOps; }
@@ -149,7 +164,7 @@ public:
return Hexagon_SMALL_DATA_THRESHOLD;
}
- const HexagonArchEnum &getHexagonArchVersion() const {
+ const Hexagon::ArchEnum &getHexagonArchVersion() const {
return HexagonArchVersion;
}
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