[PATCH] D39054: [X86][Broadwell] Added the instruction scheduling information for the Broadwell CPU.

[Gadi Haber via Phabricator via llvm-commits]

gadi.haber created this revision.

Adding the scheduling information for the Browadwell (BDW) CPU target.

This patch adds the instruction scheduling information for the Broadwell (BDW) architecture target by adding the file X86SchedBroadwell.td located under the X86 Target.
We used the scheduling information retrieved from the Broadwell architects in order to create the file.
The scheduling information includes latency, number of micro-Ops and used ports by each BDW instruction.

The patch continues the scheduling replacement and insertion effort started with the SandyBrodge (SNB) target in r310792, the Haswell (HSW) target in r311879, the SkylakeClient (SKL) target in https://reviews.llvm.org/rL313613 + https://reviews.llvm.org/rL315978 and the SkylakeServer (SKX) in https://reviews.llvm.org/rL315175.

Performance fluctuations may be expected due to code alignment effects.


Repository:
  rL LLVM

https://reviews.llvm.org/D39054

Files:
  lib/Target/X86/X86.td
  lib/Target/X86/X86SchedBroadwell.td
  lib/Target/X86/X86Schedule.td
  test/CodeGen/X86/aes-schedule.ll
  test/CodeGen/X86/avx-schedule.ll
  test/CodeGen/X86/avx2-schedule.ll
  test/CodeGen/X86/bmi-schedule.ll
  test/CodeGen/X86/bmi2-schedule.ll
  test/CodeGen/X86/f16c-schedule.ll
  test/CodeGen/X86/fma-schedule.ll
  test/CodeGen/X86/lea32-schedule.ll
  test/CodeGen/X86/lea64-schedule.ll
  test/CodeGen/X86/lzcnt-schedule.ll
  test/CodeGen/X86/mmx-schedule.ll
  test/CodeGen/X86/movbe-schedule.ll
  test/CodeGen/X86/popcnt-schedule.ll
  test/CodeGen/X86/sse-schedule.ll
  test/CodeGen/X86/sse2-schedule.ll
  test/CodeGen/X86/sse3-schedule.ll
  test/CodeGen/X86/sse41-schedule.ll
  test/CodeGen/X86/sse42-schedule.ll
  test/CodeGen/X86/ssse3-schedule.ll

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