[PATCH] D39056: [mips] Use register scavenging with MSA.

[Simon Dardis via Phabricator via llvm-commits]

sdardis created this revision.
Herald added subscribers: arichardson, qcolombet.

MSA stores and loads to the stack are more likely to require an
emergency GPR spill slot due to the smaller offsets available
with those instructions.

Handle this by overestimating the size of the stack by determining
the largest offset presuming that all callee save registers are
spilled and accounting of incoming arguments.


Repository:
  rL LLVM

https://reviews.llvm.org/D39056

Files:
  lib/Target/Mips/MipsFrameLowering.cpp
  lib/Target/Mips/MipsSEFrameLowering.cpp
  test/CodeGen/Mips/msa/emergency-spill.mir
  test/CodeGen/Mips/msa/frameindex.ll

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