[llvm] r316047 - [aarch64][globalisel] Register banks and classes should have distinct names.

[Daniel Sanders via llvm-commits]

Author: dsanders
Date: Tue Oct 17 17:12:43 2017
New Revision: 316047

URL: http://llvm.org/viewvc/llvm-project?rev=316047&view=rev
Log:
[aarch64][globalisel] Register banks and classes should have distinct names.

Otherwise they are ambiguous in MIR.


Modified:
    llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
    llvm/trunk/lib/Target/AArch64/AArch64RegisterBanks.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=316047&r1=316046&r2=316047&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Tue Oct 17 17:12:43 2017
@@ -59,10 +59,9 @@ AArch64RegisterBankInfo::AArch64Register
   assert(&AArch64::FPRRegBank == &RBFPR &&
          "The order in RegBanks is messed up");
 
-  const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID);
+  const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID);
   (void)RBCCR;
-  assert(&AArch64::CCRRegBank == &RBCCR &&
-         "The order in RegBanks is messed up");
+  assert(&AArch64::CCRegBank == &RBCCR && "The order in RegBanks is messed up");
 
   // The GPR register bank is fully defined by all the registers in
   // GR64all + its subclasses.
@@ -229,7 +228,7 @@ const RegisterBank &AArch64RegisterBankI
   case AArch64::XSeqPairsClassRegClassID:
     return getRegBank(AArch64::GPRRegBankID);
   case AArch64::CCRRegClassID:
-    return getRegBank(AArch64::CCRRegBankID);
+    return getRegBank(AArch64::CCRegBankID);
   default:
     llvm_unreachable("Register class not supported");
   }

Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBanks.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBanks.td?rev=316047&r1=316046&r2=316047&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBanks.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBanks.td Tue Oct 17 17:12:43 2017
@@ -17,4 +17,4 @@ def GPRRegBank : RegisterBank<"GPR", [GP
 def FPRRegBank : RegisterBank<"FPR", [QQQQ]>;
 
 /// Conditional register: NZCV.
-def CCRRegBank : RegisterBank<"CCR", [CCR]>;
+def CCRegBank : RegisterBank<"CC", [CCR]>;