[llvm] r315978 - [X86][SKL] Updated scheduling information for the SkylakeClient target
Haber, Gadi via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 17 00:48:05 PDT 2017
HI Vitaly.
One of the regression test mmx-schedule.ll has failed.
The problem is that the test was not updated.
No sure why it didn’t fail while running it on my branch.
I’m about to commit the fixed version of the test.
Best Regards:
Gadi.
From: Vitaly Buka [mailto:vitalybuka at google.com]
Sent: Tuesday, October 17, 2017 10:43
To: Haber, Gadi <gadi.haber at intel.com>
Cc: llvm-commits <llvm-commits at lists.llvm.org>
Subject: Re: [llvm] r315978 - [X86][SKL] Updated scheduling information for the SkylakeClient target
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/8811/steps/check-llvm%20ubsan/logs/stdio
Testing: 0 .. 10.. 20.. 30.. 40.. 50..
FAIL: LLVM :: CodeGen/X86/mmx-schedule.ll (13526 of 22418)
******************** TEST 'LLVM :: CodeGen/X86/mmx-schedule.ll' FAILED ********************
Script:
--
/b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llc < /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+ssse3 | /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll --check-prefix=CHECK --check-prefix=GENERIC
/b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llc < /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=atom | /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll --check-prefix=CHECK --check-prefix=ATOM
/b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llc < /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=slm | /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll --check-prefix=CHECK --check-prefix=SLM
/b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llc < /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=sandybridge | /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll --check-prefix=CHECK --check-prefix=SANDY
/b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llc < /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=ivybridge | /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll --check-prefix=CHECK --check-prefix=SANDY
/b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llc < /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=haswell | /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll --check-prefix=CHECK --check-prefix=HASWELL
/b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llc < /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skylake | /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll --check-prefix=CHECK --check-prefix=SKYLAKE
/b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llc < /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skx | /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll --check-prefix=CHECK --check-prefix=SKX
/b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llc < /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=btver2 | /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll --check-prefix=CHECK --check-prefix=BTVER2
/b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llc < /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 | /b/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll --check-prefix=CHECK --check-prefix=ZNVER1
--
Exit Code: 1
Command Output (stderr):
--
/b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll:57:17: error: expected string not found in input
; SKYLAKE-NEXT: cvtpd2pi (%rdi), %mm1 # sched: [5:1.00]
^
<stdin>:9:2: note: scanning from here
cvtpd2pi (%rdi), %mm1 # sched: [11:1.00]
^
/b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll:133:17: error: expected string not found in input
; SKYLAKE-NEXT: cvtpi2pd (%rdi), %xmm1 # sched: [5:1.00]
^
<stdin>:23:2: note: scanning from here
cvtpi2pd (%rdi), %xmm1 # sched: [10:1.00]
^
/b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/X86/mmx-schedule.ll:204:17: error: expected string not found in input
; SKYLAKE-NEXT: cvtpi2ps (%rdi), %xmm1 # sched: [4:1.00]
^
<stdin>:36:2: note: scanning from here
cvtpi2ps (%rdi), %xmm1 # sched: [9:1.00]
On Mon, Oct 16, 2017 at 11:47 PM, Gadi Haber via llvm-commits <llvm-commits at lists.llvm.org<mailto:llvm-commits at lists.llvm.org>> wrote:
Author: gadi.haber
Date: Mon Oct 16 23:47:04 2017
New Revision: 315978
URL: http://llvm.org/viewvc/llvm-project?rev=315978&view=rev
Log:
[X86][SKL] Updated scheduling information for the SkylakeClient target
Updated the scheduling information for the SkylakeClient target with the following changes:
1. regrouped the instructions after adding load and store latencies.
2. regrouped the instructions after adding identified missing ports in several groups.
The changes were made after revisiting the latencies impact of all the load and store uOps.
Reviewers: zvi, RKSimon, craig.topper
Differential Revision: https://reviews.llvm.org/D38727
Change-Id: I778a308cc11e490e8fa5e27e2047412a1dca029f
Modified:
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/test/CodeGen/X86/aes-schedule.ll
llvm/trunk/test/CodeGen/X86/avx-schedule.ll
llvm/trunk/test/CodeGen/X86/avx2-schedule.ll
llvm/trunk/test/CodeGen/X86/bmi-schedule.ll
llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll
llvm/trunk/test/CodeGen/X86/f16c-schedule.ll
llvm/trunk/test/CodeGen/X86/fma-schedule.ll
llvm/trunk/test/CodeGen/X86/lea32-schedule.ll
llvm/trunk/test/CodeGen/X86/lea64-schedule.ll
llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll
llvm/trunk/test/CodeGen/X86/movbe-schedule.ll
llvm/trunk/test/CodeGen/X86/popcnt-schedule.ll
llvm/trunk/test/CodeGen/X86/sse-schedule.ll
llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
llvm/trunk/test/CodeGen/X86/sse3-schedule.ll
llvm/trunk/test/CodeGen/X86/sse41-schedule.ll
llvm/trunk/test/CodeGen/X86/sse42-schedule.ll
llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=315978&r1=315977&r2=315978&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Mon Oct 16 23:47:04 2017
@@ -307,3705 +307,3904 @@ def : WriteRes<WritePHAddLd, [SKLPort15,
// Remaining instrs.
-def SKLWriteResGroup0 : SchedWriteRes<[SKLPort23]> {
+def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> {
let Latency = 1;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup0], (instregex "LDDQUrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "LD_F32m")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "LD_F64m")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "LD_F80m")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MMX_MOVD64from64rm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MMX_MOVD64rm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MMX_MOVD64to64rm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MMX_MOVQ64rm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MOV(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MOV64toPQIrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MOV8rm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVAPDrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVAPSrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVDDUPrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVDI2PDIrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVDQArm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVDQUrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVNTDQArm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVSHDUPrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVSLDUPrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVSSrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVSX(16|32|64)rm16")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVSX(16|32|64)rm32")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVSX(16|32|64)rm8")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVUPDrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVUPSrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVZX(16|32|64)rm16")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "MOVZX(16|32|64)rm8")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "PREFETCHNTA")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "PREFETCHT0")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "PREFETCHT1")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "PREFETCHT2")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VBROADCASTF128")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VBROADCASTI128")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VBROADCASTSDYrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VBROADCASTSSYrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VBROADCASTSSrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VLDDQUYrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VLDDQUrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOV64toPQIrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVAPDYrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVAPDrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVAPSYrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVAPSrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVDDUPYrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVDDUPrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVDI2PDIrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVDQAYrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVDQArm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVDQUYrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVDQUrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVNTDQAYrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVNTDQArm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVQI2PQIrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVSDrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVSHDUPYrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVSHDUPrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVSLDUPYrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVSLDUPrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVSSrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVUPDYrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVUPDrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVUPSYrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VMOVUPSrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VPBROADCASTDYrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VPBROADCASTDrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VPBROADCASTQYrm")>;
-def: InstRW<[SKLWriteResGroup0], (instregex "VPBROADCASTQrm")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDSBirr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDSWirr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDUSBirr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDUSWirr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PAVGBirr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PAVGWirr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PCMPEQBirr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PCMPEQDirr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PCMPEQWirr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PCMPGTBirr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PCMPGTDirr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PCMPGTWirr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PMAXSWirr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PMAXUBirr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PMINSWirr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PMINUBirr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSLLDri")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSLLDrr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSLLQri")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSLLQrr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSLLWri")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSLLWrr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSRADri")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSRADrr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSRAWri")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSRAWrr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSRLDri")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSRLDrr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSRLQri")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSRLQrr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSRLWri")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSRLWrr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSUBSBirr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSUBSWirr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSUBUSBirr")>;
+def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSUBUSWirr")>;
+
+def SKLWriteResGroup2 : SchedWriteRes<[SKLPort1]> {
+ let Latency = 1;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup2], (instregex "MMX_MASKMOVQ64")>;
+
+def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {
+ let Latency = 1;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup3], (instregex "COMP_FST0r")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "COM_FST0r")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "INSERTPSrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_MOVD64rr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_MOVD64to64rr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PALIGNR64irr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PSHUFBrr64")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PSHUFWri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PUNPCKHBWirr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PUNPCKHDQirr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PUNPCKHWDirr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PUNPCKLBWirr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PUNPCKLDQirr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MMX_PUNPCKLWDirr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MOV64toPQIrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MOVDDUPrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MOVDI2PDIrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MOVHLPSrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MOVLHPSrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MOVSDrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MOVSHDUPrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MOVSLDUPrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MOVUPDrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "MOVUPSrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PACKSSDWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PACKSSWBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PACKUSDWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PACKUSWBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PALIGNRrri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PBLENDWrri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVSXBDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVSXBQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVSXBWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVSXDQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVSXWDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVSXWQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVZXBDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVZXBQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVZXBWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVZXDQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVZXWDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PMOVZXWQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PSHUFBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PSHUFDri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PSHUFHWri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PSHUFLWri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PSLLDQri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PSRLDQri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PUNPCKHBWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PUNPCKHDQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PUNPCKHQDQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PUNPCKHWDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PUNPCKLBWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PUNPCKLDQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PUNPCKLQDQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "PUNPCKLWDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "SHUFPDrri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "SHUFPSrri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "UCOM_FPr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "UCOM_Fr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "UNPCKHPDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "UNPCKHPSrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "UNPCKLPDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "UNPCKLPSrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VBROADCASTSSrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VINSERTPSrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOV64toPQIrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVDDUPYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVDDUPrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVDI2PDIrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVHLPSrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVLHPSrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVSDrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVSHDUPYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVSHDUPrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVSLDUPYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVSLDUPrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVUPDYrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVUPDrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVUPSYrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VMOVUPSrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPACKSSDWYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPACKSSDWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPACKSSWBYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPACKSSWBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPACKUSDWYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPACKUSDWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPACKUSWBYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPACKUSWBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPALIGNRYrri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPALIGNRrri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPBLENDWYrri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPBLENDWrri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPBROADCASTDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPBROADCASTQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPERMILPDYri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPERMILPDYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPERMILPDri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPERMILPDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPERMILPSYri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPERMILPSYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPERMILPSri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPERMILPSrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVSXBDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVSXBQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVSXBWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVSXDQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVSXWDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVSXWQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVZXBDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVZXBQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVZXBWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVZXDQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVZXWDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPMOVZXWQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSHUFBYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSHUFBrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSHUFDYri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSHUFDri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSHUFHWYri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSHUFHWri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSHUFLWYri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSHUFLWri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLDQYri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLDQri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLDQYri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLDQri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKHBWYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKHBWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKHDQYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKHDQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKHQDQYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKHQDQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKHWDYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKHWDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKLBWYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKLBWrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKLDQYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKLDQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKLQDQYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKLQDQrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKLWDYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VPUNPCKLWDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VSHUFPDYrri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VSHUFPDrri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VSHUFPSYrri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VSHUFPSrri")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VUNPCKHPDYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VUNPCKHPDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VUNPCKHPSYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VUNPCKHPSrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VUNPCKLPDYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VUNPCKLPDrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VUNPCKLPSYrr")>;
+def: InstRW<[SKLWriteResGroup3], (instregex "VUNPCKLPSrr")>;
+
+def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {
+ let Latency = 1;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>;
+
+def SKLWriteResGroup5 : SchedWriteRes<[SKLPort01]> {
+ let Latency = 1;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup5], (instregex "PABSBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PABSDrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PABSWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PADDSBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PADDSWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PADDUSBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PADDUSWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PAVGBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PAVGWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PCMPEQBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PCMPEQDrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PCMPEQQrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PCMPEQWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PCMPGTBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PCMPGTDrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PCMPGTWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PMAXSBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PMAXSDrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PMAXSWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PMAXUBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PMAXUDrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PMAXUWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PMINSBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PMINSDrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PMINSWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PMINUBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PMINUDrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PMINUWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PSIGNBrr128")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PSIGNDrr128")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PSIGNWrr128")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PSLLDri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PSLLQri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PSLLWri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PSRADri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PSRAWri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PSRLDri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PSRLQri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PSRLWri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PSUBSBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PSUBSWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PSUBUSBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "PSUBUSWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPABSBYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPABSBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPABSDYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPABSDrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPABSWYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPABSWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPADDSBYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPADDSBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPADDSWYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPADDSWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPADDUSBYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPADDUSBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPADDUSWYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPADDUSWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPAVGBYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPAVGBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPAVGWYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPAVGWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPEQBYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPEQBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPEQDYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPEQDrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPEQQYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPEQQrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPEQWYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPEQWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPGTBYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPGTBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPGTDYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPGTDrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPGTWYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPCMPGTWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXSBYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXSBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXSDYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXSDrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXSWYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXSWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXUBYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXUBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXUDYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXUDrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXUWYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMAXUWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINSBYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINSBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINSDYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINSDrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINSWYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINSWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINUBYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINUBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINUDYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINUDrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINUWYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPMINUWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNBYrr256")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNBrr128")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNDYrr256")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNDrr128")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNWYrr256")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSIGNWrr128")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLDYri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLDri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLQYri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLQri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLVDYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLVDrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLVQYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLVQrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLWYri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSLLWri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRADYri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRADri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRAVDYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRAVDrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRAWYri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRAWri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRLDYri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRLDri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRLQYri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRLQri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRLVDYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRLVDrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRLVQYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRLVQrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRLWYri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSRLWri")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSUBSBYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSUBSBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSUBSWYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSUBSWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSUBUSBYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSUBUSBrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSUBUSWYrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "VPSUBUSWrr")>;
+
+def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> {
+ let Latency = 1;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup6], (instregex "FINCSTP")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "FNOP")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_MOVQ64rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PABSBrr64")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PABSDrr64")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PABSWrr64")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PADDBirr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PADDDirr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PADDQirr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PADDWirr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PANDNirr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PANDirr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PORirr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSIGNBrr64")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSIGNDrr64")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSIGNWrr64")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSUBBirr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSUBDirr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSUBQirr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PSUBWirr")>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_PXORirr")>;
+
+def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {
+ let Latency = 1;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "ADC8rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "ADCX32rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "ADCX64rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "ADOX32rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "ADOX64rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "BT(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "BT(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "BTC(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "BTC(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "BTR(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "BTR(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "BTS(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "BTS(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CDQ")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CLAC")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVAE(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVB(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVE(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVG(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVGE(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVL(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVLE(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVNE(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVNO(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVNP(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVNS(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVO(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVP(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CMOVS(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "CQO")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JAE_1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JAE_4")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JA_1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JA_4")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JBE_1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JBE_4")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JB_1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JB_4")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JE_1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JE_4")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JGE_1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JGE_4")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JG_1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JG_4")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JLE_1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JLE_4")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JL_1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JL_4")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JMP_1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JMP_4")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JNE_1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JNE_4")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JNO_1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JNO_4")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JNP_1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JNP_4")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JNS_1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JNS_4")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JO_1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JO_4")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JP_1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JP_4")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JS_1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "JS_4")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "RORX32ri")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "RORX64ri")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SAR(16|32|64)r1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SAR(16|32|64)ri")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SAR8r1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SAR8ri")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SARX32rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SARX64rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SBB(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SBB(16|32|64)rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SBB8rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SETAEr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SETBr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SETEr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SETGEr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SETGr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SETLEr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SETLr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SETNEr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SETNOr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SETNPr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SETNSr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SETOr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SETPr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SETSr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SHL(16|32|64)r1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SHL(16|32|64)ri")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SHL8r1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SHL8ri")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SHLX32rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SHLX64rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SHR(16|32|64)r1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SHR(16|32|64)ri")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SHR8r1")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SHR8ri")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SHRX32rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "SHRX64rr")>;
+def: InstRW<[SKLWriteResGroup7], (instregex "STAC")>;
+
+def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {
+ let Latency = 1;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup8], (instregex "ANDN32rr")>;
+def: InstRW<[SKLWriteResGroup8], (instregex "ANDN64rr")>;
+def: InstRW<[SKLWriteResGroup8], (instregex "BLSI32rr")>;
+def: InstRW<[SKLWriteResGroup8], (instregex "BLSI64rr")>;
+def: InstRW<[SKLWriteResGroup8], (instregex "BLSMSK32rr")>;
+def: InstRW<[SKLWriteResGroup8], (instregex "BLSMSK64rr")>;
+def: InstRW<[SKLWriteResGroup8], (instregex "BLSR32rr")>;
+def: InstRW<[SKLWriteResGroup8], (instregex "BLSR64rr")>;
+def: InstRW<[SKLWriteResGroup8], (instregex "BZHI32rr")>;
+def: InstRW<[SKLWriteResGroup8], (instregex "BZHI64rr")>;
+def: InstRW<[SKLWriteResGroup8], (instregex "LEA(16|32|64)r")>;
+
+def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
+ let Latency = 1;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup9], (instregex "ANDNPDrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "ANDNPSrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "ANDPDrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "ANDPSrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "BLENDPDrri")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "BLENDPSrri")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "MMX_MOVD64from64rr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "MOVAPDrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "MOVAPSrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "MOVDQArr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "MOVDQUrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "MOVPQI2QIrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "MOVSSrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "ORPDrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "ORPSrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "PADDBrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "PADDDrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "PADDQrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "PADDWrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "PANDNrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "PANDrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "PORrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "PSUBBrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "PSUBDrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "PSUBQrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "PSUBWrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "PXORrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VANDNPDYrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VANDNPDrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VANDNPSYrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VANDNPSrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VANDPDYrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VANDPDrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VANDPSYrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VANDPSrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VBLENDPDYrri")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VBLENDPDrri")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VBLENDPSYrri")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VBLENDPSrri")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVAPDYrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVAPDrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVAPSYrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVAPSrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVDQAYrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVDQArr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVDQUYrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVDQUrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVPQI2QIrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVSSrr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VMOVZPQILo2PQIrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VORPDYrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VORPDrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VORPSYrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VORPSrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPADDBYrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPADDBrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPADDDYrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPADDDrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPADDQYrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPADDQrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPADDWYrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPADDWrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPANDNYrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPANDNrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPANDYrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPANDrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPBLENDDYrri")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPBLENDDrri")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPORYrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPORrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPSUBBYrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPSUBBrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPSUBDYrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPSUBDrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPSUBQYrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPSUBQrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPSUBWYrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPSUBWrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPXORYrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VPXORrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VXORPDYrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VXORPDrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VXORPSYrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "VXORPSrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "XORPDrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "XORPSrr")>;
+
+def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
+ let Latency = 1;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup10], (instregex "ADD(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "ADD(16|32|64)rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "ADD8i8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "ADD8ri")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "ADD8rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "AND(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "AND(16|32|64)rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "AND8i8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "AND8ri")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "AND8rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "CBW")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "CLC")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "CMC")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "CMP(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "CMP(16|32|64)rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "CMP8i8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "CMP8ri")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "CMP8rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "CWDE")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "DEC(16|32|64)r")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "DEC8r")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "INC(16|32|64)r")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "INC8r")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "LAHF")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "MOV(16|32|64)rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "MOV8ri(_alt?)")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "MOV8rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "MOVSX(16|32|64)rr16")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "MOVSX(16|32|64)rr32")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "MOVSX(16|32|64)rr8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "MOVZX(16|32|64)rr16")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "MOVZX(16|32|64)rr8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "NEG(16|32|64)r")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "NEG8r")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "NOOP")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "NOT(16|32|64)r")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "NOT8r")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "OR(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "OR(16|32|64)rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "OR8i8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "OR8ri")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "OR8rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "SAHF")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "SGDT64m")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "SIDT64m")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "SLDT64m")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "SMSW16m")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "STC")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "STRm")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "SUB(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "SUB(16|32|64)rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "SUB8i8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "SUB8ri")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "SUB8rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "SYSCALL")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "TEST(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "TEST8i8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "TEST8ri")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "TEST8rr")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "XOR(16|32|64)ri8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "XOR(16|32|64)rr(_REV?)")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "XOR8i8")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "XOR8ri")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "XOR8rr(_REV?)")>;
+
+def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {
+ let Latency = 1;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup11], (instregex "FBSTPm")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MMX_MOVD64from64rm")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MMX_MOVD64mr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MMX_MOVNTQmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MMX_MOVQ64mr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOV(16|32|64)mr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOV8mi")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOV8mr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVAPDmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVAPSmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVDQAmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVDQUmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVHPDmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVHPSmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVLPDmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVLPSmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVNTDQmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVNTI_64mr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVNTImr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVNTPDmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVNTPSmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVPDI2DImr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVPQI2QImr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVPQIto64mr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVSSmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVUPDmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "MOVUPSmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP32m")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP64m")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP80m")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VEXTRACTF128mr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VEXTRACTI128mr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVAPDYmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVAPDmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVAPSYmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVAPSmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVDQAYmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVDQAmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVDQUYmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVDQUmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVHPDmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVHPSmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVLPDmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVLPSmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVNTDQYmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVNTDQmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVNTPDYmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVNTPDmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVNTPSYmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVNTPSmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVPDI2DImr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVPQI2QImr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVPQIto64mr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVSDmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVSSmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVUPDYmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVUPDmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVUPSYmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMOVUPSmr")>;
+def: InstRW<[SKLWriteResGroup11], (instregex "VMPTRSTm")>;
+
+def SKLWriteResGroup12 : SchedWriteRes<[SKLPort0]> {
+ let Latency = 2;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup12], (instregex "COMISDrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "COMISSrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_MOVD64from64rr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_MOVD64grr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PMOVMSKBrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MOVMSKPDrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MOVMSKPSrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MOVPDI2DIrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "MOVPQIto64rr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "PMOVMSKBrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "UCOMISDrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "UCOMISSrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "VCOMISDrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "VCOMISSrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "VMOVMSKPDYrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "VMOVMSKPDrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "VMOVMSKPSYrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "VMOVMSKPSrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "VMOVPDI2DIrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "VMOVPQIto64rr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "VPMOVMSKBYrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "VPMOVMSKBrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "VTESTPDYrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "VTESTPDrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "VTESTPSYrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "VTESTPSrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "VUCOMISDrr")>;
+def: InstRW<[SKLWriteResGroup12], (instregex "VUCOMISSrr")>;
-def SKLWriteResGroup1 : SchedWriteRes<[SKLPort4,SKLPort237]> {
- let Latency = 1;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup1], (instregex "FBSTPm")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MMX_MOVD64from64rm")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MMX_MOVD64mr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MMX_MOVNTQmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MMX_MOVQ64mr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOV(16|32|64)mr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOV8mi")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOV8mr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVAPDmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVAPSmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVDQAmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVDQUmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVHPDmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVHPSmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVLPDmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVLPSmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVNTDQmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVNTI_64mr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVNTImr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVNTPDmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVNTPSmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVPDI2DImr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVPQI2QImr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVPQIto64mr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVSSmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVUPDmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "MOVUPSmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "ST_FP32m")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "ST_FP64m")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "ST_FP80m")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VEXTRACTF128mr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VEXTRACTI128mr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVAPDYmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVAPDmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVAPSYmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVAPSmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVDQAYmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVDQAmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVDQUYmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVDQUmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVHPDmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVHPSmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVLPDmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVLPSmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVNTDQYmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVNTDQmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVNTPDYmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVNTPDmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVNTPSYmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVNTPSmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVPDI2DImr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVPQI2QImr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVPQIto64mr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVSDmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVSSmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVUPDYmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVUPDmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVUPSYmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMOVUPSmr")>;
-def: InstRW<[SKLWriteResGroup1], (instregex "VMPTRSTm")>;
-
-def SKLWriteResGroup2 : SchedWriteRes<[SKLPort0]> {
- let Latency = 1;
- let NumMicroOps = 1;
- let ResourceCycles = [1];
-}
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PADDSBirr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PADDSWirr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PADDUSBirr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PADDUSWirr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PAVGBirr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PAVGWirr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PCMPEQBirr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PCMPEQDirr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PCMPEQWirr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PCMPGTBirr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PCMPGTDirr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PCMPGTWirr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PMAXSWirr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PMAXUBirr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PMINSWirr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PMINUBirr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSLLDri")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSLLDrr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSLLQri")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSLLQrr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSLLWri")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSLLWrr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRADri")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRADrr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRAWri")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRAWrr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRLDri")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRLDrr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRLQri")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRLQrr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRLWri")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSRLWrr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSUBSBirr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSUBSWirr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSUBUSBirr")>;
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_PSUBUSWirr")>;
-
-def SKLWriteResGroup3 : SchedWriteRes<[SKLPort1]> {
- let Latency = 1;
- let NumMicroOps = 1;
- let ResourceCycles = [1];
-}
-def: InstRW<[SKLWriteResGroup3], (instregex "MMX_MASKMOVQ64")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PABSBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PABSDrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PABSWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PADDSBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PADDSWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PADDUSBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PADDUSWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PAVGBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PAVGWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PCMPEQBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PCMPEQDrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PCMPEQQrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PCMPEQWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PCMPGTBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PCMPGTDrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PCMPGTWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PMAXSBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PMAXSDrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PMAXSWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PMAXUBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PMAXUDrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PMAXUWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PMINSBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PMINSDrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PMINSWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PMINUBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PMINUDrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PMINUWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PSIGNBrr128")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PSIGNDrr128")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PSIGNWrr128")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PSLLDri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PSLLQri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PSLLWri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PSRADri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PSRAWri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PSRLDri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PSRLQri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PSRLWri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PSUBSBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PSUBSWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PSUBUSBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "PSUBUSWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPABSBYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPABSBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPABSDYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPABSDrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPABSWYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPABSWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPADDSBYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPADDSBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPADDSWYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPADDSWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPADDUSBYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPADDUSBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPADDUSWYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPADDUSWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPAVGBYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPAVGBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPAVGWYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPAVGWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQBYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQDYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQDrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQQYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQQrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQWYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPEQWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPGTBYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPGTBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPGTDYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPGTDrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPGTWYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPCMPGTWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXSBYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXSBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXSDYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXSDrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXSWYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXSWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXUBYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXUBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXUDYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXUDrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXUWYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMAXUWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINSBYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINSBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINSDYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINSDrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINSWYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINSWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINUBYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINUBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINUDYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINUDrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINUWYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPMINUWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSIGNBYrr256")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSIGNBrr128")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSIGNDYrr256")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSIGNDrr128")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSIGNWYrr256")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSIGNWrr128")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLDYri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLDri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLQYri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLQri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLVDYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLVDrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLVQYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLVQrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLWYri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSLLWri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRADYri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRADri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRAVDYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRAVDrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRAWYri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRAWri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLDYri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLDri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLQYri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLQri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLVDYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLVDrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLVQYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLVQrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLWYri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSRLWri")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBSBYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBSBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBSWYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBSWrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBUSBYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBUSBrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBUSWYrr")>;
-def: InstRW<[SKLWriteResGroup3], (instregex "VPSUBUSWrr")>;
-
-def SKLWriteResGroup4 : SchedWriteRes<[SKLPort5]> {
- let Latency = 1;
- let NumMicroOps = 1;
- let ResourceCycles = [1];
-}
-def: InstRW<[SKLWriteResGroup4], (instregex "COMP_FST0r")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "COM_FST0r")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "FINCSTP")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "FNOP")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "INSERTPSrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_MOVD64rr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_MOVD64to64rr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_MOVQ64rr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PABSBrr64")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PABSDrr64")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PABSWrr64")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PADDBirr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PADDDirr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PADDQirr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PADDWirr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PALIGNR64irr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PANDNirr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PANDirr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PORirr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSHUFBrr64")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSHUFWri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSIGNBrr64")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSIGNDrr64")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSIGNWrr64")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSUBBirr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSUBDirr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSUBQirr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PSUBWirr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PUNPCKHBWirr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PUNPCKHDQirr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PUNPCKHWDirr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PUNPCKLBWirr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PUNPCKLDQirr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PUNPCKLWDirr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MMX_PXORirr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MOV64toPQIrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MOVDDUPrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MOVDI2PDIrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MOVHLPSrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MOVLHPSrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MOVSDrr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MOVSHDUPrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MOVSLDUPrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MOVUPDrr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "MOVUPSrr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PACKSSDWrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PACKSSWBrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PACKUSDWrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PACKUSWBrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PALIGNRrri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PBLENDWrri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVSXBDrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVSXBQrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVSXBWrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVSXDQrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVSXWDrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVSXWQrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVZXBDrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVZXBQrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVZXBWrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVZXDQrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVZXWDrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PMOVZXWQrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PSHUFBrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PSHUFDri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PSHUFHWri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PSHUFLWri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PSLLDQri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PSRLDQri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKHBWrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKHDQrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKHQDQrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKHWDrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKLBWrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKLDQrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKLQDQrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "PUNPCKLWDrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "SHUFPDrri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "SHUFPSrri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "UCOM_FPr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "UCOM_Fr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "UNPCKHPDrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "UNPCKHPSrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "UNPCKLPDrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "UNPCKLPSrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VBROADCASTSSrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VINSERTPSrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOV64toPQIrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVDDUPYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVDDUPrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVDI2PDIrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVHLPSrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVLHPSrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVSDrr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVSHDUPYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVSHDUPrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVSLDUPYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVSLDUPrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVUPDYrr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVUPDrr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVUPSYrr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VMOVUPSrr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPACKSSDWYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPACKSSDWrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPACKSSWBYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPACKSSWBrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPACKUSDWYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPACKUSDWrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPACKUSWBYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPACKUSWBrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPALIGNRYrri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPALIGNRrri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPBLENDWYrri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPBLENDWrri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPBROADCASTDrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPBROADCASTQrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPDYri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPDYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPDri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPDrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPSYri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPSYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPSri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPERMILPSrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVSXBDrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVSXBQrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVSXBWrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVSXDQrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVSXWDrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVSXWQrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVZXBDrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVZXBQrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVZXBWrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVZXDQrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVZXWDrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPMOVZXWQrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFBYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFBrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFDYri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFDri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFHWYri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFHWri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFLWYri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSHUFLWri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSLLDQYri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSLLDQri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSRLDQYri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPSRLDQri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHBWYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHBWrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHDQYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHDQrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHQDQYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHQDQrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHWDYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKHWDrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLBWYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLBWrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLDQYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLDQrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLQDQYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLQDQrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLWDYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VPUNPCKLWDrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VSHUFPDYrri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VSHUFPDrri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VSHUFPSYrri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VSHUFPSrri")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKHPDYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKHPDrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKHPSYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKHPSrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKLPDYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKLPDrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKLPSYrr")>;
-def: InstRW<[SKLWriteResGroup4], (instregex "VUNPCKLPSrr")>;
-
-def SKLWriteResGroup5 : SchedWriteRes<[SKLPort6]> {
- let Latency = 1;
- let NumMicroOps = 1;
- let ResourceCycles = [1];
-}
-def: InstRW<[SKLWriteResGroup5], (instregex "ADC(16|32|64)ri8")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "ADC(16|32|64)rr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "ADC8rr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "ADCX32rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "ADCX64rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "ADOX32rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "ADOX64rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "BT(16|32|64)ri8")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "BT(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "BTC(16|32|64)ri8")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "BTC(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "BTR(16|32|64)ri8")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "BTR(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "BTS(16|32|64)ri8")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "BTS(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "CDQ")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "CLAC")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVAE(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVB(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVE(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVG(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVGE(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVL(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVLE(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVNE(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVNO(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVNP(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVNS(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVO(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVP(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "CMOVS(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "CQO")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JAE_1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JAE_4")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JA_1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JA_4")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JBE_1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JBE_4")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JB_1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JB_4")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JE_1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JE_4")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JGE_1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JGE_4")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JG_1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JG_4")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JLE_1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JLE_4")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JL_1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JL_4")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JMP(16|32|64)r")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JMP_1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JMP_4")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JNE_1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JNE_4")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JNO_1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JNO_4")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JNP_1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JNP_4")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JNS_1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JNS_4")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JO_1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JO_4")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JP_1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JP_4")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JS_1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "JS_4")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "RORX32ri")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "RORX64ri")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SAR(16|32|64)r1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SAR(16|32|64)ri")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SAR8r1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SAR8ri")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SARX32rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SARX64rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SBB(16|32|64)ri8")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SBB(16|32|64)rr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SBB8rr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SETAEr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SETBr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SETEr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SETGEr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SETGr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SETLEr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SETLr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SETNEr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SETNOr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SETNPr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SETNSr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SETOr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SETPr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SETSr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SHL(16|32|64)r1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SHL(16|32|64)ri")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SHL8r1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SHL8ri")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SHLX32rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SHLX64rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SHR(16|32|64)r1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SHR(16|32|64)ri")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SHR8r1")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SHR8ri")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SHRX32rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "SHRX64rr")>;
-def: InstRW<[SKLWriteResGroup5], (instregex "STAC")>;
-
-def SKLWriteResGroup6 : SchedWriteRes<[SKLPort15]> {
- let Latency = 1;
- let NumMicroOps = 1;
- let ResourceCycles = [1];
-}
-def: InstRW<[SKLWriteResGroup6], (instregex "ANDN32rr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "ANDN64rr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "ANDNPDrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "ANDNPSrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "ANDPDrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "ANDPSrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "BLENDPDrri")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "BLENDPSrri")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "BLSI32rr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "BLSI64rr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "BLSMSK32rr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "BLSMSK64rr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "BLSR32rr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "BLSR64rr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "BZHI32rr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "BZHI64rr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "LEA(16|32|64)r")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "MMX_MOVD64from64rr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "MOVAPDrr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "MOVAPSrr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "MOVDQArr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "MOVDQUrr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "MOVPQI2QIrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "MOVSSrr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "ORPDrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "ORPSrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "PADDBrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "PADDDrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "PADDQrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "PADDWrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "PANDNrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "PANDrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "PORrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "PSUBBrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "PSUBDrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "PSUBQrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "PSUBWrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "PXORrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VANDNPDYrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VANDNPDrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VANDNPSYrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VANDNPSrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VANDPDYrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VANDPDrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VANDPSYrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VANDPSrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VBLENDPDYrri")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VBLENDPDrri")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VBLENDPSYrri")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VBLENDPSrri")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVAPDYrr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVAPDrr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVAPSYrr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVAPSrr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVDQAYrr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVDQArr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVDQUYrr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVDQUrr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVPQI2QIrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVSSrr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VMOVZPQILo2PQIrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VORPDYrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VORPDrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VORPSYrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VORPSrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPADDBYrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPADDBrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPADDDYrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPADDDrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPADDQYrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPADDQrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPADDWYrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPADDWrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPANDNYrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPANDNrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPANDYrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPANDrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPBLENDDYrri")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPBLENDDrri")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPORYrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPORrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBBYrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBBrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBDYrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBDrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBQYrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBQrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBWYrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPSUBWrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPXORYrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VPXORrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VXORPDYrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VXORPDrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VXORPSYrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "VXORPSrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "XORPDrr")>;
-def: InstRW<[SKLWriteResGroup6], (instregex "XORPSrr")>;
-
-def SKLWriteResGroup7 : SchedWriteRes<[SKLPort0156]> {
- let Latency = 1;
- let NumMicroOps = 1;
- let ResourceCycles = [1];
-}
-def: InstRW<[SKLWriteResGroup7], (instregex "ADD(16|32|64)ri8")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "ADD(16|32|64)rr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "ADD8i8")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "ADD8ri")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "ADD8rr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "AND(16|32|64)ri8")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "AND(16|32|64)rr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "AND8i8")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "AND8ri")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "AND8rr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "CBW")>;
-//def: InstRW<[SKLWriteResGroup7], (instregex "CDQE")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "CLC")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "CMC")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "CMP(16|32|64)ri8")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "CMP(16|32|64)rr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "CMP8i8")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "CMP8ri")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "CMP8rr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "CWDE")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "DEC(16|32|64)r")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "DEC8r")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "INC(16|32|64)r")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "INC8r")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "LAHF")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "MOV(16|32|64)rr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "MOV8ri(_alt?)")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "MOV8rr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "MOVSX(16|32|64)rr16")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "MOVSX(16|32|64)rr32")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "MOVSX(16|32|64)rr8")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "MOVZX(16|32|64)rr16")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "MOVZX(16|32|64)rr8")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "NEG(16|32|64)r")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "NEG8r")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "NOOP")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "NOT(16|32|64)r")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "NOT8r")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "OR(16|32|64)ri8")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "OR(16|32|64)rr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "OR8i8")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "OR8ri")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "OR8rr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "SAHF")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "SGDT64m")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "SIDT64m")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "SLDT64m")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "SMSW16m")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "STC")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "STRm")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "SUB(16|32|64)ri8")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "SUB(16|32|64)rr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "SUB8i8")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "SUB8ri")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "SUB8rr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "SYSCALL")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "TEST(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "TEST8i8")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "TEST8ri")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "TEST8rr")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "XCHG(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "XOR(16|32|64)ri8")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "XOR(16|32|64)rr(_REV?)")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "XOR8i8")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "XOR8ri")>;
-def: InstRW<[SKLWriteResGroup7], (instregex "XOR8rr(_REV?)")>;
-
-def SKLWriteResGroup12 : SchedWriteRes<[SKLPort0,SKLPort23]> {
- let Latency = 1;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PADDSBirm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PADDSWirm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PADDUSBirm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PADDUSWirm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PAVGBirm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PAVGWirm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PCMPEQBirm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PCMPEQDirm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PCMPEQWirm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PCMPGTBirm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PCMPGTDirm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PCMPGTWirm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PMAXSWirm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PMAXUBirm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PMINSWirm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PMINUBirm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSLLDrm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSLLQrm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSLLWrm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSRADrm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSRAWrm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSRLDrm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSRLQrm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSRLWrm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSUBSBirm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSUBSWirm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSUBUSBirm")>;
-def: InstRW<[SKLWriteResGroup12], (instregex "MMX_PSUBUSWirm")>;
-
-def SKLWriteResGroup13 : SchedWriteRes<[SKLPort0,SKLPort237]> {
- let Latency = 1;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup13], (instregex "MMX_MASKMOVQ64")>;
-def: InstRW<[SKLWriteResGroup13], (instregex "VMASKMOVDQU")>;
-def: InstRW<[SKLWriteResGroup13], (instregex "VMASKMOVPDYmr")>;
-def: InstRW<[SKLWriteResGroup13], (instregex "VMASKMOVPDmr")>;
-def: InstRW<[SKLWriteResGroup13], (instregex "VMASKMOVPSYmr")>;
-def: InstRW<[SKLWriteResGroup13], (instregex "VMASKMOVPSmr")>;
-def: InstRW<[SKLWriteResGroup13], (instregex "VPMASKMOVDYmr")>;
-def: InstRW<[SKLWriteResGroup13], (instregex "VPMASKMOVDmr")>;
-def: InstRW<[SKLWriteResGroup13], (instregex "VPMASKMOVQYmr")>;
-def: InstRW<[SKLWriteResGroup13], (instregex "VPMASKMOVQmr")>;
-
-def SKLWriteResGroup14 : SchedWriteRes<[SKLPort5,SKLPort23]> {
- let Latency = 1;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup14], (instregex "FCOM32m")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "FCOM64m")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "FCOMP32m")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "FCOMP64m")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "INSERTPSrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PALIGNR64irm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PINSRWirmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PSHUFBrm64")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PSHUFWmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PUNPCKHBWirm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PUNPCKHDQirm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PUNPCKHWDirm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PUNPCKLBWirm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PUNPCKLDQirm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "MMX_PUNPCKLWDirm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "MOVHPDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "MOVHPSrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "MOVLPDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "MOVLPSrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PACKSSDWrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PACKSSWBrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PACKUSDWrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PACKUSWBrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PALIGNRrmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PBLENDWrmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PINSRBrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PINSRDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PINSRQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PINSRWrmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVSXBDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVSXBQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVSXBWrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVSXDQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVSXWDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVSXWQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVZXBDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVZXBQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVZXBWrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVZXDQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVZXWDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PMOVZXWQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PSHUFBrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PSHUFDmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PSHUFHWmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PSHUFLWmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKHBWrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKHDQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKHQDQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKHWDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKLBWrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKLDQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKLQDQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "PUNPCKLWDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "SHUFPDrmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "SHUFPSrmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "UNPCKHPDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "UNPCKHPSrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "UNPCKLPDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "UNPCKLPSrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VINSERTPSrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VMOVHPDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VMOVHPSrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VMOVLPDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VMOVLPSrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPACKSSDWYrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPACKSSDWrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPACKSSWBYrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPACKSSWBrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPACKUSDWYrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPACKUSDWrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPACKUSWBYrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPACKUSWBrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPALIGNRYrmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPALIGNRrmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPBLENDWYrmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPBLENDWrmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPBROADCASTBYrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPBROADCASTBrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPBROADCASTWYrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPBROADCASTWrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPDYmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPDYrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPDmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPSYmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPSYrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPSmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPERMILPSrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPINSRBrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPINSRDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPINSRQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPINSRWrmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVSXBDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVSXBQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVSXBWrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVSXDQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVSXWDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVSXWQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVZXBDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVZXBQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVZXBWrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVZXDQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVZXWDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPMOVZXWQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFBYrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFBrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFDYmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFDmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFHWYmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFHWmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFLWYmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPSHUFLWmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHBWYrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHBWrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHDQYrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHDQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHQDQYrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHQDQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHWDYrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKHWDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLBWYrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLBWrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLDQYrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLDQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLQDQYrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLQDQrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLWDYrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VPUNPCKLWDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VSHUFPDYrmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VSHUFPDrmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VSHUFPSYrmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VSHUFPSrmi")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKHPDYrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKHPDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKHPSYrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKHPSrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKLPDYrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKLPDrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKLPSYrm")>;
-def: InstRW<[SKLWriteResGroup14], (instregex "VUNPCKLPSrm")>;
-
-def SKLWriteResGroup15 : SchedWriteRes<[SKLPort6,SKLPort23]> {
- let Latency = 1;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup15], (instregex "FARJMP64")>;
-def: InstRW<[SKLWriteResGroup15], (instregex "JMP(16|32|64)m")>;
-
-def SKLWriteResGroup16 : SchedWriteRes<[SKLPort01,SKLPort23]> {
- let Latency = 1;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup16], (instregex "PABSBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PABSDrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PABSWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PADDSBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PADDSWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PADDUSBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PADDUSWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PAVGBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PAVGWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PCMPEQBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PCMPEQDrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PCMPEQQrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PCMPEQWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PCMPGTBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PCMPGTDrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PCMPGTWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PMAXSBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PMAXSDrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PMAXSWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PMAXUBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PMAXUDrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PMAXUWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PMINSBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PMINSDrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PMINSWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PMINUBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PMINUDrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PMINUWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PSIGNBrm128")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PSIGNDrm128")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PSIGNWrm128")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PSLLDrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PSLLQrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PSLLWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PSRADrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PSRAWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PSRLDrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PSRLQrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PSRLWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PSUBSBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PSUBSWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PSUBUSBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "PSUBUSWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPABSBYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPABSBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPABSDYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPABSDrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPABSWYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPABSWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPADDSBYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPADDSBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPADDSWYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPADDSWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPADDUSBYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPADDUSBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPADDUSWYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPADDUSWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPAVGBYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPAVGBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPAVGWYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPAVGWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQBYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQDYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQDrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQQYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQQrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQWYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPEQWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPGTBYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPGTBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPGTDYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPGTDrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPGTWYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPCMPGTWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXSBYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXSBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXSDYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXSDrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXSWYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXSWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXUBYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXUBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXUDYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXUDrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXUWYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMAXUWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINSBYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINSBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINSDYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINSDrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINSWYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINSWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINUBYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINUBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINUDYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINUDrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINUWYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPMINUWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSIGNBYrm256")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSIGNBrm128")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSIGNDYrm256")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSIGNDrm128")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSIGNWYrm256")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSIGNWrm128")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLDYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLDrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLQYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLQrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLVDYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLVDrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLVQYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLVQrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLWYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSLLWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRADYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRADrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRAVDYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRAVDrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRAWYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRAWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLDYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLDrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLQYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLQrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLVDYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLVDrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLVQYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLVQrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLWYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSRLWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBSBYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBSBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBSWYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBSWrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBUSBYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBUSBrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBUSWYrm")>;
-def: InstRW<[SKLWriteResGroup16], (instregex "VPSUBUSWrm")>;
-
-def SKLWriteResGroup17 : SchedWriteRes<[SKLPort23,SKLPort05]> {
- let Latency = 1;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PABSBrm64")>;
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PABSDrm64")>;
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PABSWrm64")>;
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PADDBirm")>;
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PADDDirm")>;
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PADDQirm")>;
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PADDWirm")>;
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PANDNirm")>;
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PANDirm")>;
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PORirm")>;
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PSIGNBrm64")>;
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PSIGNDrm64")>;
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PSIGNWrm64")>;
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PSUBBirm")>;
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PSUBDirm")>;
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PSUBQirm")>;
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PSUBWirm")>;
-def: InstRW<[SKLWriteResGroup17], (instregex "MMX_PXORirm")>;
-
-def SKLWriteResGroup18 : SchedWriteRes<[SKLPort23,SKLPort06]> {
- let Latency = 1;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup18], (instregex "ADC(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "ADC8rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "ADCX32rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "ADCX64rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "ADOX32rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "ADOX64rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "BT(16|32|64)mi8")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVAE(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVB(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVE(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVG(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVGE(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVL(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVLE(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVNE(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVNO(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVNP(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVNS(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVO(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVP(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "CMOVS(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "RORX32mi")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "RORX64mi")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "SARX32rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "SARX64rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "SBB(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "SBB8rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "SHLX32rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "SHLX64rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "SHRX32rm")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "SHRX64rm")>;
-
-def SKLWriteResGroup19 : SchedWriteRes<[SKLPort23,SKLPort15]> {
- let Latency = 1;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup19], (instregex "ANDN32rm")>;
-def: InstRW<[SKLWriteResGroup19], (instregex "ANDN64rm")>;
-def: InstRW<[SKLWriteResGroup19], (instregex "BLSI32rm")>;
-def: InstRW<[SKLWriteResGroup19], (instregex "BLSI64rm")>;
-def: InstRW<[SKLWriteResGroup19], (instregex "BLSMSK32rm")>;
-def: InstRW<[SKLWriteResGroup19], (instregex "BLSMSK64rm")>;
-def: InstRW<[SKLWriteResGroup19], (instregex "BLSR32rm")>;
-def: InstRW<[SKLWriteResGroup19], (instregex "BLSR64rm")>;
-def: InstRW<[SKLWriteResGroup19], (instregex "BZHI32rm")>;
-def: InstRW<[SKLWriteResGroup19], (instregex "BZHI64rm")>;
-def: InstRW<[SKLWriteResGroup19], (instregex "MOVBE(16|32|64)rm")>;
-
-def SKLWriteResGroup20 : SchedWriteRes<[SKLPort23,SKLPort015]> {
- let Latency = 1;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup20], (instregex "ANDNPDrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "ANDNPSrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "ANDPDrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "ANDPSrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "BLENDPDrmi")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "BLENDPSrmi")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "ORPDrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "ORPSrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "PADDBrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "PADDDrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "PADDQrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "PADDWrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "PANDNrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "PANDrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "PORrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "PSUBBrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "PSUBDrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "PSUBQrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "PSUBWrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "PXORrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VANDNPDYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VANDNPDrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VANDNPSYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VANDNPSrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VANDPDYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VANDPDrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VANDPSYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VANDPSrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VBLENDPDYrmi")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VBLENDPDrmi")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VBLENDPSYrmi")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VBLENDPSrmi")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VINSERTF128rm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VINSERTI128rm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VMASKMOVPDYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VMASKMOVPDrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VMASKMOVPSYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VMASKMOVPSrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VORPDYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VORPDrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VORPSYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VORPSrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPADDBYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPADDBrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPADDDYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPADDDrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPADDQYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPADDQrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPADDWYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPADDWrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPANDNYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPANDNrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPANDYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPANDrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPBLENDDYrmi")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPBLENDDrmi")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPMASKMOVDYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPMASKMOVDrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPMASKMOVQYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPMASKMOVQrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPORYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPORrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBBYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBBrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBDYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBDrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBQYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBQrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBWYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPSUBWrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPXORYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VPXORrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VXORPDYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VXORPDrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VXORPSYrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "VXORPSrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "XORPDrm")>;
-def: InstRW<[SKLWriteResGroup20], (instregex "XORPSrm")>;
-
-def SKLWriteResGroup21 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
- let Latency = 1;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup21], (instregex "ADD(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "ADD8rm")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "AND(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "AND8rm")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "CMP(16|32|64)mi8")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "CMP(16|32|64)mr")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "CMP(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "CMP8mi")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "CMP8mr")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "CMP8rm")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "OR(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "OR8rm")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "POP(16|32|64)r(mr?)")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "SUB(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "SUB8rm")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "TEST(16|32|64)mr")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "TEST8mi")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "TEST8mr")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "XOR(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "XOR8rm")>;
-
-def SKLWriteResGroup22 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
- let Latency = 1;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup22], (instregex "SFENCE")>;
-
-def SKLWriteResGroup23 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {
- let Latency = 1;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SKLWriteResGroup23], (instregex "EXTRACTPSmr")>;
-def: InstRW<[SKLWriteResGroup23], (instregex "PEXTRBmr")>;
-def: InstRW<[SKLWriteResGroup23], (instregex "PEXTRDmr")>;
-def: InstRW<[SKLWriteResGroup23], (instregex "PEXTRQmr")>;
-def: InstRW<[SKLWriteResGroup23], (instregex "PEXTRWmr")>;
-def: InstRW<[SKLWriteResGroup23], (instregex "STMXCSR")>;
-def: InstRW<[SKLWriteResGroup23], (instregex "VEXTRACTPSmr")>;
-def: InstRW<[SKLWriteResGroup23], (instregex "VPEXTRBmr")>;
-def: InstRW<[SKLWriteResGroup23], (instregex "VPEXTRDmr")>;
-def: InstRW<[SKLWriteResGroup23], (instregex "VPEXTRQmr")>;
-def: InstRW<[SKLWriteResGroup23], (instregex "VPEXTRWmr")>;
-def: InstRW<[SKLWriteResGroup23], (instregex "VSTMXCSR")>;
-
-def SKLWriteResGroup24 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {
- let Latency = 1;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SKLWriteResGroup24], (instregex "FNSTCW16m")>;
-
-def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
- let Latency = 1;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SKLWriteResGroup25], (instregex "SETAEm")>;
-def: InstRW<[SKLWriteResGroup25], (instregex "SETBm")>;
-def: InstRW<[SKLWriteResGroup25], (instregex "SETEm")>;
-def: InstRW<[SKLWriteResGroup25], (instregex "SETGEm")>;
-def: InstRW<[SKLWriteResGroup25], (instregex "SETGm")>;
-def: InstRW<[SKLWriteResGroup25], (instregex "SETLEm")>;
-def: InstRW<[SKLWriteResGroup25], (instregex "SETLm")>;
-def: InstRW<[SKLWriteResGroup25], (instregex "SETNEm")>;
-def: InstRW<[SKLWriteResGroup25], (instregex "SETNOm")>;
-def: InstRW<[SKLWriteResGroup25], (instregex "SETNPm")>;
-def: InstRW<[SKLWriteResGroup25], (instregex "SETNSm")>;
-def: InstRW<[SKLWriteResGroup25], (instregex "SETOm")>;
-def: InstRW<[SKLWriteResGroup25], (instregex "SETPm")>;
-def: InstRW<[SKLWriteResGroup25], (instregex "SETSm")>;
-
-def SKLWriteResGroup26 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> {
- let Latency = 1;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SKLWriteResGroup26], (instregex "MOVBE(16|32|64)mr")>;
-
-def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
- let Latency = 1;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SKLWriteResGroup27], (instregex "PUSH(16|32|64)r(mr?)")>;
-def: InstRW<[SKLWriteResGroup27], (instregex "PUSH64i8")>;
-def: InstRW<[SKLWriteResGroup27], (instregex "STOSB")>;
-def: InstRW<[SKLWriteResGroup27], (instregex "STOSL")>;
-def: InstRW<[SKLWriteResGroup27], (instregex "STOSQ")>;
-def: InstRW<[SKLWriteResGroup27], (instregex "STOSW")>;
-
-def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
- let Latency = 1;
- let NumMicroOps = 4;
- let ResourceCycles = [1,1,1,1];
-}
-def: InstRW<[SKLWriteResGroup28], (instregex "BTC(16|32|64)mi8")>;
-def: InstRW<[SKLWriteResGroup28], (instregex "BTR(16|32|64)mi8")>;
-def: InstRW<[SKLWriteResGroup28], (instregex "BTS(16|32|64)mi8")>;
-def: InstRW<[SKLWriteResGroup28], (instregex "SAR(16|32|64)m1")>;
-def: InstRW<[SKLWriteResGroup28], (instregex "SAR(16|32|64)mi")>;
-def: InstRW<[SKLWriteResGroup28], (instregex "SAR8m1")>;
-def: InstRW<[SKLWriteResGroup28], (instregex "SAR8mi")>;
-def: InstRW<[SKLWriteResGroup28], (instregex "SHL(16|32|64)m1")>;
-def: InstRW<[SKLWriteResGroup28], (instregex "SHL(16|32|64)mi")>;
-def: InstRW<[SKLWriteResGroup28], (instregex "SHL8m1")>;
-def: InstRW<[SKLWriteResGroup28], (instregex "SHL8mi")>;
-def: InstRW<[SKLWriteResGroup28], (instregex "SHR(16|32|64)m1")>;
-def: InstRW<[SKLWriteResGroup28], (instregex "SHR(16|32|64)mi")>;
-def: InstRW<[SKLWriteResGroup28], (instregex "SHR8m1")>;
-def: InstRW<[SKLWriteResGroup28], (instregex "SHR8mi")>;
-
-def SKLWriteResGroup29 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
- let Latency = 1;
- let NumMicroOps = 4;
- let ResourceCycles = [1,1,1,1];
-}
-def: InstRW<[SKLWriteResGroup29], (instregex "ADD(16|32|64)mi8")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "ADD(16|32|64)mr")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "ADD8mi")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "ADD8mr")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "AND(16|32|64)mi8")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "AND(16|32|64)mr")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "AND8mi")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "AND8mr")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "DEC(16|32|64)m")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "DEC8m")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "INC(16|32|64)m")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "INC8m")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "NEG(16|32|64)m")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "NEG8m")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "NOT(16|32|64)m")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "NOT8m")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "OR(16|32|64)mi8")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "OR(16|32|64)mr")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "OR8mi")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "OR8mr")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "POP(16|32|64)rmm")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "PUSH(16|32|64)rmm")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "SUB(16|32|64)mi8")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "SUB(16|32|64)mr")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "SUB8mi")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "SUB8mr")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "XOR(16|32|64)mi8")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "XOR(16|32|64)mr")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "XOR8mi")>;
-def: InstRW<[SKLWriteResGroup29], (instregex "XOR8mr")>;
-
-def SKLWriteResGroup31 : SchedWriteRes<[SKLPort0]> {
- let Latency = 2;
- let NumMicroOps = 1;
- let ResourceCycles = [1];
-}
-def: InstRW<[SKLWriteResGroup31], (instregex "COMISDrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "COMISSrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "MMX_MOVD64from64rr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "MMX_MOVD64grr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "MMX_PMOVMSKBrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "MOVMSKPDrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "MOVMSKPSrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "MOVPDI2DIrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "MOVPQIto64rr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "PMOVMSKBrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "UCOMISDrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "UCOMISSrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "VCOMISDrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "VCOMISSrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "VMOVMSKPDYrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "VMOVMSKPDrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "VMOVMSKPSYrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "VMOVMSKPSrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "VMOVPDI2DIrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "VMOVPQIto64rr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "VPMOVMSKBYrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "VPMOVMSKBrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "VTESTPDYrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "VTESTPDrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "VTESTPSYrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "VTESTPSrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "VUCOMISDrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "VUCOMISSrr")>;
-
-def SKLWriteResGroup32 : SchedWriteRes<[SKLPort5]> {
+def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[SKLWriteResGroup32], (instregex "MMX_MOVQ2DQrr")>;
-def: InstRW<[SKLWriteResGroup32], (instregex "MMX_PINSRWirri")>;
-def: InstRW<[SKLWriteResGroup32], (instregex "PINSRBrr")>;
-def: InstRW<[SKLWriteResGroup32], (instregex "PINSRDrr")>;
-def: InstRW<[SKLWriteResGroup32], (instregex "PINSRQrr")>;
-def: InstRW<[SKLWriteResGroup32], (instregex "PINSRWrri")>;
-def: InstRW<[SKLWriteResGroup32], (instregex "VPINSRBrr")>;
-def: InstRW<[SKLWriteResGroup32], (instregex "VPINSRDrr")>;
-def: InstRW<[SKLWriteResGroup32], (instregex "VPINSRQrr")>;
-def: InstRW<[SKLWriteResGroup32], (instregex "VPINSRWrri")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "MMX_MOVQ2DQrr")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "MMX_PINSRWirri")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "PINSRBrr")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "PINSRDrr")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "PINSRQrr")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "PINSRWrri")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "VPINSRBrr")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "VPINSRDrr")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "VPINSRQrr")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "VPINSRWrri")>;
-def SKLWriteResGroup33 : SchedWriteRes<[SKLPort05]> {
+def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[SKLWriteResGroup33], (instregex "FDECSTP")>;
-def: InstRW<[SKLWriteResGroup33], (instregex "MMX_MOVDQ2Qrr")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "FDECSTP")>;
+def: InstRW<[SKLWriteResGroup14], (instregex "MMX_MOVDQ2Qrr")>;
-def SKLWriteResGroup34 : SchedWriteRes<[SKLPort06]> {
+def SKLWriteResGroup15 : SchedWriteRes<[SKLPort06]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[SKLWriteResGroup34], (instregex "CMOVA(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup34], (instregex "CMOVBE(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup34], (instregex "ROL(16|32|64)r1")>;
-def: InstRW<[SKLWriteResGroup34], (instregex "ROL(16|32|64)ri")>;
-def: InstRW<[SKLWriteResGroup34], (instregex "ROL8r1")>;
-def: InstRW<[SKLWriteResGroup34], (instregex "ROL8ri")>;
-def: InstRW<[SKLWriteResGroup34], (instregex "ROR(16|32|64)r1")>;
-def: InstRW<[SKLWriteResGroup34], (instregex "ROR(16|32|64)ri")>;
-def: InstRW<[SKLWriteResGroup34], (instregex "ROR8r1")>;
-def: InstRW<[SKLWriteResGroup34], (instregex "ROR8ri")>;
-def: InstRW<[SKLWriteResGroup34], (instregex "SETAr")>;
-def: InstRW<[SKLWriteResGroup34], (instregex "SETBEr")>;
+def: InstRW<[SKLWriteResGroup15], (instregex "CMOVA(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup15], (instregex "CMOVBE(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup15], (instregex "ROL(16|32|64)r1")>;
+def: InstRW<[SKLWriteResGroup15], (instregex "ROL(16|32|64)ri")>;
+def: InstRW<[SKLWriteResGroup15], (instregex "ROL8r1")>;
+def: InstRW<[SKLWriteResGroup15], (instregex "ROL8ri")>;
+def: InstRW<[SKLWriteResGroup15], (instregex "ROR(16|32|64)r1")>;
+def: InstRW<[SKLWriteResGroup15], (instregex "ROR(16|32|64)ri")>;
+def: InstRW<[SKLWriteResGroup15], (instregex "ROR8r1")>;
+def: InstRW<[SKLWriteResGroup15], (instregex "ROR8ri")>;
+def: InstRW<[SKLWriteResGroup15], (instregex "SETAr")>;
+def: InstRW<[SKLWriteResGroup15], (instregex "SETBEr")>;
-def SKLWriteResGroup35 : SchedWriteRes<[SKLPort015]> {
+def SKLWriteResGroup16 : SchedWriteRes<[SKLPort015]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[SKLWriteResGroup35], (instregex "BLENDVPDrr0")>;
-def: InstRW<[SKLWriteResGroup35], (instregex "BLENDVPSrr0")>;
-def: InstRW<[SKLWriteResGroup35], (instregex "PBLENDVBrr0")>;
-def: InstRW<[SKLWriteResGroup35], (instregex "VBLENDVPDYrr")>;
-def: InstRW<[SKLWriteResGroup35], (instregex "VBLENDVPDrr")>;
-def: InstRW<[SKLWriteResGroup35], (instregex "VBLENDVPSYrr")>;
-def: InstRW<[SKLWriteResGroup35], (instregex "VBLENDVPSrr")>;
-def: InstRW<[SKLWriteResGroup35], (instregex "VPBLENDVBYrr")>;
-def: InstRW<[SKLWriteResGroup35], (instregex "VPBLENDVBrr")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "BLENDVPDrr0")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "BLENDVPSrr0")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "PBLENDVBrr0")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VBLENDVPDYrr")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VBLENDVPDrr")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VBLENDVPSYrr")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VBLENDVPSrr")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPBLENDVBYrr")>;
+def: InstRW<[SKLWriteResGroup16], (instregex "VPBLENDVBrr")>;
-def SKLWriteResGroup36 : SchedWriteRes<[SKLPort0156]> {
+def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[SKLWriteResGroup36], (instregex "LFENCE")>;
-def: InstRW<[SKLWriteResGroup36], (instregex "WAIT")>;
-def: InstRW<[SKLWriteResGroup36], (instregex "XGETBV")>;
+def: InstRW<[SKLWriteResGroup17], (instregex "LFENCE")>;
+def: InstRW<[SKLWriteResGroup17], (instregex "WAIT")>;
+def: InstRW<[SKLWriteResGroup17], (instregex "XGETBV")>;
-def SKLWriteResGroup37 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+def SKLWriteResGroup18 : SchedWriteRes<[SKLPort0,SKLPort237]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup37], (instregex "COMISDrm")>;
-def: InstRW<[SKLWriteResGroup37], (instregex "COMISSrm")>;
-def: InstRW<[SKLWriteResGroup37], (instregex "UCOMISDrm")>;
-def: InstRW<[SKLWriteResGroup37], (instregex "UCOMISSrm")>;
-def: InstRW<[SKLWriteResGroup37], (instregex "VCOMISDrm")>;
-def: InstRW<[SKLWriteResGroup37], (instregex "VCOMISSrm")>;
-def: InstRW<[SKLWriteResGroup37], (instregex "VTESTPDYrm")>;
-def: InstRW<[SKLWriteResGroup37], (instregex "VTESTPDrm")>;
-def: InstRW<[SKLWriteResGroup37], (instregex "VTESTPSYrm")>;
-def: InstRW<[SKLWriteResGroup37], (instregex "VTESTPSrm")>;
-def: InstRW<[SKLWriteResGroup37], (instregex "VUCOMISDrm")>;
-def: InstRW<[SKLWriteResGroup37], (instregex "VUCOMISSrm")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "MMX_MASKMOVQ64")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVDQU")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVPDYmr")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVPDmr")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVPSYmr")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVPSmr")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "VPMASKMOVDYmr")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "VPMASKMOVDmr")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "VPMASKMOVQYmr")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "VPMASKMOVQmr")>;
-def SKLWriteResGroup38 : SchedWriteRes<[SKLPort5,SKLPort01]> {
+def SKLWriteResGroup19 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup38], (instregex "PSLLDrr")>;
-def: InstRW<[SKLWriteResGroup38], (instregex "PSLLQrr")>;
-def: InstRW<[SKLWriteResGroup38], (instregex "PSLLWrr")>;
-def: InstRW<[SKLWriteResGroup38], (instregex "PSRADrr")>;
-def: InstRW<[SKLWriteResGroup38], (instregex "PSRAWrr")>;
-def: InstRW<[SKLWriteResGroup38], (instregex "PSRLDrr")>;
-def: InstRW<[SKLWriteResGroup38], (instregex "PSRLQrr")>;
-def: InstRW<[SKLWriteResGroup38], (instregex "PSRLWrr")>;
-def: InstRW<[SKLWriteResGroup38], (instregex "VPSLLDrr")>;
-def: InstRW<[SKLWriteResGroup38], (instregex "VPSLLQrr")>;
-def: InstRW<[SKLWriteResGroup38], (instregex "VPSLLWrr")>;
-def: InstRW<[SKLWriteResGroup38], (instregex "VPSRADrr")>;
-def: InstRW<[SKLWriteResGroup38], (instregex "VPSRAWrr")>;
-def: InstRW<[SKLWriteResGroup38], (instregex "VPSRLDrr")>;
-def: InstRW<[SKLWriteResGroup38], (instregex "VPSRLQrr")>;
-def: InstRW<[SKLWriteResGroup38], (instregex "VPSRLWrr")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "PSLLDrr")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "PSLLQrr")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "PSLLWrr")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "PSRADrr")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "PSRAWrr")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "PSRLDrr")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "PSRLQrr")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "PSRLWrr")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "VPSLLDrr")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "VPSLLQrr")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "VPSLLWrr")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "VPSRADrr")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "VPSRAWrr")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "VPSRLDrr")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "VPSRLQrr")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "VPSRLWrr")>;
-def SKLWriteResGroup39 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
+def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup39], (instregex "CLFLUSH")>;
+def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>;
-def SKLWriteResGroup40 : SchedWriteRes<[SKLPort06,SKLPort15]> {
+def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup40], (instregex "BEXTR32rr")>;
-def: InstRW<[SKLWriteResGroup40], (instregex "BEXTR64rr")>;
-def: InstRW<[SKLWriteResGroup40], (instregex "BSWAP(16|32|64)r")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "SFENCE")>;
-def SKLWriteResGroup41 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
+def SKLWriteResGroup22 : SchedWriteRes<[SKLPort06,SKLPort15]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup41], (instregex "ADC8i8")>;
-def: InstRW<[SKLWriteResGroup41], (instregex "ADC8ri")>;
-def: InstRW<[SKLWriteResGroup41], (instregex "CWD")>;
-def: InstRW<[SKLWriteResGroup41], (instregex "JRCXZ")>;
-def: InstRW<[SKLWriteResGroup41], (instregex "SBB8i8")>;
-def: InstRW<[SKLWriteResGroup41], (instregex "SBB8ri")>;
-
-def SKLWriteResGroup42 : SchedWriteRes<[SKLPort5,SKLPort23]> {
- let Latency = 2;
- let NumMicroOps = 3;
- let ResourceCycles = [2,1];
-}
-def: InstRW<[SKLWriteResGroup42], (instregex "MMX_PACKSSDWirm")>;
-def: InstRW<[SKLWriteResGroup42], (instregex "MMX_PACKSSWBirm")>;
-def: InstRW<[SKLWriteResGroup42], (instregex "MMX_PACKUSWBirm")>;
-
-def SKLWriteResGroup43 : SchedWriteRes<[SKLPort23,SKLPort06]> {
- let Latency = 2;
- let NumMicroOps = 3;
- let ResourceCycles = [1,2];
-}
-def: InstRW<[SKLWriteResGroup43], (instregex "CMOVA(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup43], (instregex "CMOVBE(16|32|64)rm")>;
-
-def SKLWriteResGroup44 : SchedWriteRes<[SKLPort23,SKLPort015]> {
- let Latency = 2;
- let NumMicroOps = 3;
- let ResourceCycles = [1,2];
-}
-def: InstRW<[SKLWriteResGroup44], (instregex "BLENDVPDrm0")>;
-def: InstRW<[SKLWriteResGroup44], (instregex "BLENDVPSrm0")>;
-def: InstRW<[SKLWriteResGroup44], (instregex "PBLENDVBrm0")>;
-def: InstRW<[SKLWriteResGroup44], (instregex "VBLENDVPDYrm")>;
-def: InstRW<[SKLWriteResGroup44], (instregex "VBLENDVPDrm")>;
-def: InstRW<[SKLWriteResGroup44], (instregex "VBLENDVPSYrm")>;
-def: InstRW<[SKLWriteResGroup44], (instregex "VBLENDVPSrm")>;
-def: InstRW<[SKLWriteResGroup44], (instregex "VPBLENDVBYrm")>;
-def: InstRW<[SKLWriteResGroup44], (instregex "VPBLENDVBrm")>;
-
-def SKLWriteResGroup45 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
- let Latency = 2;
- let NumMicroOps = 3;
- let ResourceCycles = [1,2];
-}
-def: InstRW<[SKLWriteResGroup45], (instregex "LEAVE64")>;
-def: InstRW<[SKLWriteResGroup45], (instregex "SCASB")>;
-def: InstRW<[SKLWriteResGroup45], (instregex "SCASL")>;
-def: InstRW<[SKLWriteResGroup45], (instregex "SCASQ")>;
-def: InstRW<[SKLWriteResGroup45], (instregex "SCASW")>;
+def: InstRW<[SKLWriteResGroup22], (instregex "BEXTR32rr")>;
+def: InstRW<[SKLWriteResGroup22], (instregex "BEXTR64rr")>;
+def: InstRW<[SKLWriteResGroup22], (instregex "BSWAP(16|32|64)r")>;
-def SKLWriteResGroup46 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
+def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
let Latency = 2;
- let NumMicroOps = 3;
- let ResourceCycles = [1,2];
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup46], (instregex "MFENCE")>;
+def: InstRW<[SKLWriteResGroup23], (instregex "ADC8i8")>;
+def: InstRW<[SKLWriteResGroup23], (instregex "ADC8ri")>;
+def: InstRW<[SKLWriteResGroup23], (instregex "CWD")>;
+def: InstRW<[SKLWriteResGroup23], (instregex "JRCXZ")>;
+def: InstRW<[SKLWriteResGroup23], (instregex "SBB8i8")>;
+def: InstRW<[SKLWriteResGroup23], (instregex "SBB8ri")>;
-def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {
+def SKLWriteResGroup24 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {
let Latency = 2;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup47], (instregex "FNSTSWm")>;
+def: InstRW<[SKLWriteResGroup24], (instregex "EXTRACTPSmr")>;
+def: InstRW<[SKLWriteResGroup24], (instregex "PEXTRBmr")>;
+def: InstRW<[SKLWriteResGroup24], (instregex "PEXTRDmr")>;
+def: InstRW<[SKLWriteResGroup24], (instregex "PEXTRQmr")>;
+def: InstRW<[SKLWriteResGroup24], (instregex "PEXTRWmr")>;
+def: InstRW<[SKLWriteResGroup24], (instregex "STMXCSR")>;
+def: InstRW<[SKLWriteResGroup24], (instregex "VEXTRACTPSmr")>;
+def: InstRW<[SKLWriteResGroup24], (instregex "VPEXTRBmr")>;
+def: InstRW<[SKLWriteResGroup24], (instregex "VPEXTRDmr")>;
+def: InstRW<[SKLWriteResGroup24], (instregex "VPEXTRQmr")>;
+def: InstRW<[SKLWriteResGroup24], (instregex "VPEXTRWmr")>;
+def: InstRW<[SKLWriteResGroup24], (instregex "VSTMXCSR")>;
-def SKLWriteResGroup48 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {
+def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {
let Latency = 2;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup48], (instregex "FLDCW16m")>;
+def: InstRW<[SKLWriteResGroup25], (instregex "FNSTCW16m")>;
-def SKLWriteResGroup49 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort0156]> {
+def SKLWriteResGroup26 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
let Latency = 2;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup49], (instregex "LDMXCSR")>;
-def: InstRW<[SKLWriteResGroup49], (instregex "VLDMXCSR")>;
+def: InstRW<[SKLWriteResGroup26], (instregex "SETAEm")>;
+def: InstRW<[SKLWriteResGroup26], (instregex "SETBm")>;
+def: InstRW<[SKLWriteResGroup26], (instregex "SETEm")>;
+def: InstRW<[SKLWriteResGroup26], (instregex "SETGEm")>;
+def: InstRW<[SKLWriteResGroup26], (instregex "SETGm")>;
+def: InstRW<[SKLWriteResGroup26], (instregex "SETLEm")>;
+def: InstRW<[SKLWriteResGroup26], (instregex "SETLm")>;
+def: InstRW<[SKLWriteResGroup26], (instregex "SETNEm")>;
+def: InstRW<[SKLWriteResGroup26], (instregex "SETNOm")>;
+def: InstRW<[SKLWriteResGroup26], (instregex "SETNPm")>;
+def: InstRW<[SKLWriteResGroup26], (instregex "SETNSm")>;
+def: InstRW<[SKLWriteResGroup26], (instregex "SETOm")>;
+def: InstRW<[SKLWriteResGroup26], (instregex "SETPm")>;
+def: InstRW<[SKLWriteResGroup26], (instregex "SETSm")>;
-def SKLWriteResGroup51 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> {
+def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> {
let Latency = 2;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup51], (instregex "LRETQ")>;
-def: InstRW<[SKLWriteResGroup51], (instregex "RETQ")>;
+def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
-def SKLWriteResGroup52 : SchedWriteRes<[SKLPort23,SKLPort06,SKLPort15]> {
+def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
let Latency = 2;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup52], (instregex "BEXTR32rm")>;
-def: InstRW<[SKLWriteResGroup52], (instregex "BEXTR64rm")>;
-
-def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
- let Latency = 2;
- let NumMicroOps = 4;
- let ResourceCycles = [1,1,2];
-}
-def: InstRW<[SKLWriteResGroup53], (instregex "SETAm")>;
-def: InstRW<[SKLWriteResGroup53], (instregex "SETBEm")>;
-
-def SKLWriteResGroup54 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> {
- let Latency = 2;
- let NumMicroOps = 4;
- let ResourceCycles = [1,1,1,1];
-}
-def: InstRW<[SKLWriteResGroup54], (instregex "CALL(16|32|64)r")>;
-
-def SKLWriteResGroup55 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> {
- let Latency = 2;
- let NumMicroOps = 4;
- let ResourceCycles = [1,1,1,1];
-}
-def: InstRW<[SKLWriteResGroup55], (instregex "CALL64pcrel32")>;
-
-def SKLWriteResGroup56 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
- let Latency = 2;
- let NumMicroOps = 5;
- let ResourceCycles = [1,1,1,2];
-}
-def: InstRW<[SKLWriteResGroup56], (instregex "ROL(16|32|64)m1")>;
-def: InstRW<[SKLWriteResGroup56], (instregex "ROL(16|32|64)mi")>;
-def: InstRW<[SKLWriteResGroup56], (instregex "ROL8m1")>;
-def: InstRW<[SKLWriteResGroup56], (instregex "ROL8mi")>;
-def: InstRW<[SKLWriteResGroup56], (instregex "ROR(16|32|64)m1")>;
-def: InstRW<[SKLWriteResGroup56], (instregex "ROR(16|32|64)mi")>;
-def: InstRW<[SKLWriteResGroup56], (instregex "ROR8m1")>;
-def: InstRW<[SKLWriteResGroup56], (instregex "ROR8mi")>;
-
-def SKLWriteResGroup57 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
- let Latency = 2;
- let NumMicroOps = 5;
- let ResourceCycles = [1,1,1,2];
-}
-def: InstRW<[SKLWriteResGroup57], (instregex "XADD(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup57], (instregex "XADD8rm")>;
-
-def SKLWriteResGroup58 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
- let Latency = 2;
- let NumMicroOps = 5;
- let ResourceCycles = [1,1,1,1,1];
-}
-def: InstRW<[SKLWriteResGroup58], (instregex "CALL(16|32|64)m")>;
-def: InstRW<[SKLWriteResGroup58], (instregex "FARCALL64")>;
+def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)r")>;
+def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
+def: InstRW<[SKLWriteResGroup28], (instregex "PUSH64i8")>;
+def: InstRW<[SKLWriteResGroup28], (instregex "STOSB")>;
+def: InstRW<[SKLWriteResGroup28], (instregex "STOSL")>;
+def: InstRW<[SKLWriteResGroup28], (instregex "STOSQ")>;
+def: InstRW<[SKLWriteResGroup28], (instregex "STOSW")>;
-def SKLWriteResGroup60 : SchedWriteRes<[SKLPort1]> {
+def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> {
let Latency = 3;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup60], (instregex "BSF(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup60], (instregex "BSR(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup60], (instregex "IMUL64rr(i8?)")>;
-def: InstRW<[SKLWriteResGroup60], (instregex "IMUL8r")>;
-def: InstRW<[SKLWriteResGroup60], (instregex "LZCNT(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup60], (instregex "MUL8r")>;
-def: InstRW<[SKLWriteResGroup60], (instregex "PDEP32rr")>;
-def: InstRW<[SKLWriteResGroup60], (instregex "PDEP64rr")>;
-def: InstRW<[SKLWriteResGroup60], (instregex "PEXT32rr")>;
-def: InstRW<[SKLWriteResGroup60], (instregex "PEXT64rr")>;
-def: InstRW<[SKLWriteResGroup60], (instregex "POPCNT(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup60], (instregex "SHLD(16|32|64)rri8")>;
-def: InstRW<[SKLWriteResGroup60], (instregex "SHRD(16|32|64)rri8")>;
-def: InstRW<[SKLWriteResGroup60], (instregex "TZCNT(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "BSF(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "BSR(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "IMUL64rr(i8?)")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "IMUL8r")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "LZCNT(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "MUL8r")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "PDEP32rr")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "PDEP64rr")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "PEXT32rr")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "PEXT64rr")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "POPCNT(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "SHLD(16|32|64)rri8")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "SHRD(16|32|64)rri8")>;
+def: InstRW<[SKLWriteResGroup29], (instregex "TZCNT(16|32|64)rr")>;
-def SKLWriteResGroup60_16 : SchedWriteRes<[SKLPort1, SKLPort0156]> {
+def SKLWriteResGroup29_16 : SchedWriteRes<[SKLPort1, SKLPort0156]> {
let Latency = 3;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup60_16], (instregex "IMUL16rr(i8?)")>;
+def: InstRW<[SKLWriteResGroup29_16], (instregex "IMUL16rr(i8?)")>;
-def SKLWriteResGroup60_32 : SchedWriteRes<[SKLPort1]> {
+def SKLWriteResGroup29_32 : SchedWriteRes<[SKLPort1]> {
let Latency = 3;
let NumMicroOps = 1;
}
-def: InstRW<[SKLWriteResGroup60_32], (instregex "IMUL32rr(i8?)")>;
+def: InstRW<[SKLWriteResGroup29_32], (instregex "IMUL32rr(i8?)")>;
-def SKLWriteResGroup61 : SchedWriteRes<[SKLPort5]> {
+def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> {
let Latency = 3;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup61], (instregex "ADD_FPrST0")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "ADD_FST0r")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "ADD_FrST0")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "MMX_PSADBWirr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "PCMPGTQrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "PSADBWrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "SUBR_FPrST0")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "SUBR_FST0r")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "SUBR_FrST0")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "SUB_FPrST0")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "SUB_FST0r")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "SUB_FrST0")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VBROADCASTSDYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VBROADCASTSSYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VEXTRACTF128rr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VEXTRACTI128rr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VINSERTF128rr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VINSERTI128rr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPBROADCASTBYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPBROADCASTBrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPBROADCASTDYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPBROADCASTQYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPBROADCASTWYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPBROADCASTWrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPCMPGTQYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPCMPGTQrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPERM2F128rr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPERM2I128rr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPERMDYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPERMPDYri")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPERMPSYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPERMQYri")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVSXBDYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVSXBQYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVSXBWYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVSXDQYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVSXWDYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVSXWQYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVZXBDYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVZXBQYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVZXBWYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVZXDQYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVZXWDYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPMOVZXWQYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPSADBWYrr")>;
-def: InstRW<[SKLWriteResGroup61], (instregex "VPSADBWrr")>;
-
-def SKLWriteResGroup62 : SchedWriteRes<[SKLPort0,SKLPort5]> {
- let Latency = 3;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup62], (instregex "EXTRACTPSrr")>;
-def: InstRW<[SKLWriteResGroup62], (instregex "MMX_PEXTRWirri")>;
-def: InstRW<[SKLWriteResGroup62], (instregex "PEXTRBrr")>;
-def: InstRW<[SKLWriteResGroup62], (instregex "PEXTRDrr")>;
-def: InstRW<[SKLWriteResGroup62], (instregex "PEXTRQrr")>;
-def: InstRW<[SKLWriteResGroup62], (instregex "PEXTRWri")>;
-def: InstRW<[SKLWriteResGroup62], (instregex "PEXTRWrr_REV")>;
-def: InstRW<[SKLWriteResGroup62], (instregex "PTESTrr")>;
-def: InstRW<[SKLWriteResGroup62], (instregex "VEXTRACTPSrr")>;
-def: InstRW<[SKLWriteResGroup62], (instregex "VPEXTRBrr")>;
-def: InstRW<[SKLWriteResGroup62], (instregex "VPEXTRDrr")>;
-def: InstRW<[SKLWriteResGroup62], (instregex "VPEXTRQrr")>;
-def: InstRW<[SKLWriteResGroup62], (instregex "VPEXTRWri")>;
-def: InstRW<[SKLWriteResGroup62], (instregex "VPEXTRWrr_REV")>;
-def: InstRW<[SKLWriteResGroup62], (instregex "VPTESTYrr")>;
-def: InstRW<[SKLWriteResGroup62], (instregex "VPTESTrr")>;
-
-def SKLWriteResGroup63 : SchedWriteRes<[SKLPort0,SKLPort0156]> {
- let Latency = 3;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup63], (instregex "FNSTSW16r")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "ADD_FPrST0")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "ADD_FST0r")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "ADD_FrST0")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "MMX_PSADBWirr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "PCMPGTQrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "PSADBWrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "SUBR_FPrST0")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "SUBR_FST0r")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "SUBR_FrST0")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "SUB_FPrST0")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "SUB_FST0r")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "SUB_FrST0")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VBROADCASTSDYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VBROADCASTSSYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VEXTRACTF128rr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VEXTRACTI128rr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VINSERTF128rr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VINSERTI128rr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPBROADCASTBYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPBROADCASTBrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPBROADCASTDYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPBROADCASTQYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPBROADCASTWYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPBROADCASTWrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPCMPGTQYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPCMPGTQrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPERM2F128rr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPERM2I128rr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPERMDYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPERMPDYri")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPERMPSYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPERMQYri")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVSXBDYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVSXBQYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVSXBWYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVSXDQYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVSXWDYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVSXWQYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVZXBDYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVZXBQYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVZXBWYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVZXDQYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVZXWDYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPMOVZXWQYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPSADBWYrr")>;
+def: InstRW<[SKLWriteResGroup30], (instregex "VPSADBWrr")>;
-def SKLWriteResGroup64 : SchedWriteRes<[SKLPort1,SKLPort23]> {
+def SKLWriteResGroup31 : SchedWriteRes<[SKLPort0,SKLPort5]> {
let Latency = 3;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup64], (instregex "BSF(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup64], (instregex "BSR(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup64], (instregex "IMUL64m")>;
-def: InstRW<[SKLWriteResGroup64], (instregex "IMUL(32|64)rm(i8?)")>;
-def: InstRW<[SKLWriteResGroup64], (instregex "IMUL8m")>;
-def: InstRW<[SKLWriteResGroup64], (instregex "LZCNT(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup64], (instregex "MUL64m")>;
-def: InstRW<[SKLWriteResGroup64], (instregex "MUL8m")>;
-def: InstRW<[SKLWriteResGroup64], (instregex "PDEP32rm")>;
-def: InstRW<[SKLWriteResGroup64], (instregex "PDEP64rm")>;
-def: InstRW<[SKLWriteResGroup64], (instregex "PEXT32rm")>;
-def: InstRW<[SKLWriteResGroup64], (instregex "PEXT64rm")>;
-def: InstRW<[SKLWriteResGroup64], (instregex "POPCNT(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup64], (instregex "TZCNT(16|32|64)rm")>;
-
-def SKLWriteResGroup64_16 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {
- let Latency = 3;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SKLWriteResGroup64_16], (instregex "IMUL16rm(i8?)")>;
-
-def SKLWriteResGroup64_16_2 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {
- let Latency = 3;
- let NumMicroOps = 5;
-}
-def: InstRW<[SKLWriteResGroup64_16_2], (instregex "IMUL16m")>;
-def: InstRW<[SKLWriteResGroup64_16_2], (instregex "MUL16m")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "EXTRACTPSrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "MMX_PEXTRWirri")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "PEXTRBrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "PEXTRDrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "PEXTRQrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "PEXTRWri")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "PEXTRWrr_REV")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "PTESTrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VEXTRACTPSrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VPEXTRBrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VPEXTRDrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VPEXTRQrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VPEXTRWri")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VPEXTRWrr_REV")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VPTESTYrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VPTESTrr")>;
-def SKLWriteResGroup64_32 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {
- let Latency = 3;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SKLWriteResGroup64_32], (instregex "IMUL32m")>;
-def: InstRW<[SKLWriteResGroup64_32], (instregex "MUL32m")>;
-
-def SKLWriteResGroup65 : SchedWriteRes<[SKLPort5,SKLPort23]> {
+def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> {
let Latency = 3;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup65], (instregex "ADD_F32m")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "ADD_F64m")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "ILD_F16m")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "ILD_F32m")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "ILD_F64m")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "MMX_PSADBWirm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "PCMPGTQrm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "PSADBWrm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "SUBR_F32m")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "SUBR_F64m")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "SUB_F32m")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "SUB_F64m")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPCMPGTQYrm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPCMPGTQrm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPERM2F128rm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPERM2I128rm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPERMDYrm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPERMPDYmi")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPERMPSYrm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPERMQYmi")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVSXBDYrm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVSXBQYrm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVSXBWYrm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVSXDQYrm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVSXWDYrm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVSXWQYrm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVZXBDYrm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVZXBQYrm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVZXBWYrm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVZXDQYrm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVZXWDYrm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPMOVZXWQYrm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPSADBWYrm")>;
-def: InstRW<[SKLWriteResGroup65], (instregex "VPSADBWrm")>;
+def: InstRW<[SKLWriteResGroup32], (instregex "FNSTSW16r")>;
-def SKLWriteResGroup66 : SchedWriteRes<[SKLPort06]> {
+def SKLWriteResGroup33 : SchedWriteRes<[SKLPort06]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [3];
}
-def: InstRW<[SKLWriteResGroup66], (instregex "ROL(16|32|64)rCL")>;
-def: InstRW<[SKLWriteResGroup66], (instregex "ROL8rCL")>;
-def: InstRW<[SKLWriteResGroup66], (instregex "ROR(16|32|64)rCL")>;
-def: InstRW<[SKLWriteResGroup66], (instregex "ROR8rCL")>;
-def: InstRW<[SKLWriteResGroup66], (instregex "SAR(16|32|64)rCL")>;
-def: InstRW<[SKLWriteResGroup66], (instregex "SAR8rCL")>;
-def: InstRW<[SKLWriteResGroup66], (instregex "SHL(16|32|64)rCL")>;
-def: InstRW<[SKLWriteResGroup66], (instregex "SHL8rCL")>;
-def: InstRW<[SKLWriteResGroup66], (instregex "SHR(16|32|64)rCL")>;
-def: InstRW<[SKLWriteResGroup66], (instregex "SHR8rCL")>;
+def: InstRW<[SKLWriteResGroup33], (instregex "ROL(16|32|64)rCL")>;
+def: InstRW<[SKLWriteResGroup33], (instregex "ROL8rCL")>;
+def: InstRW<[SKLWriteResGroup33], (instregex "ROR(16|32|64)rCL")>;
+def: InstRW<[SKLWriteResGroup33], (instregex "ROR8rCL")>;
+def: InstRW<[SKLWriteResGroup33], (instregex "SAR(16|32|64)rCL")>;
+def: InstRW<[SKLWriteResGroup33], (instregex "SAR8rCL")>;
+def: InstRW<[SKLWriteResGroup33], (instregex "SHL(16|32|64)rCL")>;
+def: InstRW<[SKLWriteResGroup33], (instregex "SHL8rCL")>;
+def: InstRW<[SKLWriteResGroup33], (instregex "SHR(16|32|64)rCL")>;
+def: InstRW<[SKLWriteResGroup33], (instregex "SHR8rCL")>;
-def SKLWriteResGroup67 : SchedWriteRes<[SKLPort0156]> {
+def SKLWriteResGroup34 : SchedWriteRes<[SKLPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [3];
}
-def: InstRW<[SKLWriteResGroup67], (instregex "XADD(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup67], (instregex "XADD8rr")>;
-def: InstRW<[SKLWriteResGroup67], (instregex "XCHG8rr")>;
+def: InstRW<[SKLWriteResGroup34], (instregex "XADD(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup34], (instregex "XADD8rr")>;
+def: InstRW<[SKLWriteResGroup34], (instregex "XCHG8rr")>;
-def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0,SKLPort5]> {
+def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
-def: InstRW<[SKLWriteResGroup68], (instregex "MMX_PHADDSWrr64")>;
-def: InstRW<[SKLWriteResGroup68], (instregex "MMX_PHSUBSWrr64")>;
+def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PHADDSWrr64")>;
+def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PHSUBSWrr64")>;
-def SKLWriteResGroup69 : SchedWriteRes<[SKLPort5,SKLPort01]> {
+def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKLWriteResGroup69], (instregex "PHADDSWrr128")>;
-def: InstRW<[SKLWriteResGroup69], (instregex "PHSUBSWrr128")>;
-def: InstRW<[SKLWriteResGroup69], (instregex "VPHADDSWrr128")>;
-def: InstRW<[SKLWriteResGroup69], (instregex "VPHADDSWrr256")>;
-def: InstRW<[SKLWriteResGroup69], (instregex "VPHSUBSWrr128")>;
-def: InstRW<[SKLWriteResGroup69], (instregex "VPHSUBSWrr256")>;
+def: InstRW<[SKLWriteResGroup36], (instregex "PHADDSWrr128")>;
+def: InstRW<[SKLWriteResGroup36], (instregex "PHSUBSWrr128")>;
+def: InstRW<[SKLWriteResGroup36], (instregex "VPHADDSWrr128")>;
+def: InstRW<[SKLWriteResGroup36], (instregex "VPHADDSWrr256")>;
+def: InstRW<[SKLWriteResGroup36], (instregex "VPHSUBSWrr128")>;
+def: InstRW<[SKLWriteResGroup36], (instregex "VPHSUBSWrr256")>;
-def SKLWriteResGroup70 : SchedWriteRes<[SKLPort5,SKLPort05]> {
+def SKLWriteResGroup37 : SchedWriteRes<[SKLPort5,SKLPort05]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKLWriteResGroup70], (instregex "MMX_PHADDWrr64")>;
-def: InstRW<[SKLWriteResGroup70], (instregex "MMX_PHADDrr64")>;
-def: InstRW<[SKLWriteResGroup70], (instregex "MMX_PHSUBDrr64")>;
-def: InstRW<[SKLWriteResGroup70], (instregex "MMX_PHSUBWrr64")>;
+def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHADDWrr64")>;
+def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHADDrr64")>;
+def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHSUBDrr64")>;
+def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHSUBWrr64")>;
-def SKLWriteResGroup71 : SchedWriteRes<[SKLPort5,SKLPort015]> {
+def SKLWriteResGroup38 : SchedWriteRes<[SKLPort5,SKLPort015]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKLWriteResGroup71], (instregex "PHADDDrr")>;
-def: InstRW<[SKLWriteResGroup71], (instregex "PHADDWrr")>;
-def: InstRW<[SKLWriteResGroup71], (instregex "PHSUBDrr")>;
-def: InstRW<[SKLWriteResGroup71], (instregex "PHSUBWrr")>;
-def: InstRW<[SKLWriteResGroup71], (instregex "VPHADDDYrr")>;
-def: InstRW<[SKLWriteResGroup71], (instregex "VPHADDDrr")>;
-def: InstRW<[SKLWriteResGroup71], (instregex "VPHADDWYrr")>;
-def: InstRW<[SKLWriteResGroup71], (instregex "VPHADDWrr")>;
-def: InstRW<[SKLWriteResGroup71], (instregex "VPHSUBDYrr")>;
-def: InstRW<[SKLWriteResGroup71], (instregex "VPHSUBDrr")>;
-def: InstRW<[SKLWriteResGroup71], (instregex "VPHSUBWYrr")>;
-def: InstRW<[SKLWriteResGroup71], (instregex "VPHSUBWrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "PHADDDrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "PHADDWrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "PHSUBDrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "PHSUBWrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "VPHADDDYrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "VPHADDDrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "VPHADDWYrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "VPHADDWrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "VPHSUBDYrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "VPHSUBDrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "VPHSUBWYrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "VPHSUBWrr")>;
-def SKLWriteResGroup72 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
+def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKLWriteResGroup72], (instregex "MMX_PACKSSDWirr")>;
-def: InstRW<[SKLWriteResGroup72], (instregex "MMX_PACKSSWBirr")>;
-def: InstRW<[SKLWriteResGroup72], (instregex "MMX_PACKUSWBirr")>;
+def: InstRW<[SKLWriteResGroup39], (instregex "MMX_PACKSSDWirr")>;
+def: InstRW<[SKLWriteResGroup39], (instregex "MMX_PACKSSWBirr")>;
+def: InstRW<[SKLWriteResGroup39], (instregex "MMX_PACKUSWBirr")>;
-def SKLWriteResGroup73 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
+def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
-def: InstRW<[SKLWriteResGroup73], (instregex "CLD")>;
+def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>;
-def SKLWriteResGroup74 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
+def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
-def: InstRW<[SKLWriteResGroup74], (instregex "RCL(16|32|64)r1")>;
-def: InstRW<[SKLWriteResGroup74], (instregex "RCL(16|32|64)ri")>;
-def: InstRW<[SKLWriteResGroup74], (instregex "RCL8r1")>;
-def: InstRW<[SKLWriteResGroup74], (instregex "RCL8ri")>;
-def: InstRW<[SKLWriteResGroup74], (instregex "RCR(16|32|64)r1")>;
-def: InstRW<[SKLWriteResGroup74], (instregex "RCR(16|32|64)ri")>;
-def: InstRW<[SKLWriteResGroup74], (instregex "RCR8r1")>;
-def: InstRW<[SKLWriteResGroup74], (instregex "RCR8ri")>;
+def: InstRW<[SKLWriteResGroup41], (instregex "MFENCE")>;
-def SKLWriteResGroup75 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
+def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
+ let ResourceCycles = [1,2];
}
-def: InstRW<[SKLWriteResGroup75], (instregex "PTESTrm")>;
-def: InstRW<[SKLWriteResGroup75], (instregex "VPTESTYrm")>;
-def: InstRW<[SKLWriteResGroup75], (instregex "VPTESTrm")>;
+def: InstRW<[SKLWriteResGroup42], (instregex "RCL(16|32|64)r1")>;
+def: InstRW<[SKLWriteResGroup42], (instregex "RCL(16|32|64)ri")>;
+def: InstRW<[SKLWriteResGroup42], (instregex "RCL8r1")>;
+def: InstRW<[SKLWriteResGroup42], (instregex "RCL8ri")>;
+def: InstRW<[SKLWriteResGroup42], (instregex "RCR(16|32|64)r1")>;
+def: InstRW<[SKLWriteResGroup42], (instregex "RCR(16|32|64)ri")>;
+def: InstRW<[SKLWriteResGroup42], (instregex "RCR8r1")>;
+def: InstRW<[SKLWriteResGroup42], (instregex "RCR8ri")>;
-def SKLWriteResGroup76 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {
+def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup76], (instregex "ISTT_FP16m")>;
-def: InstRW<[SKLWriteResGroup76], (instregex "ISTT_FP32m")>;
-def: InstRW<[SKLWriteResGroup76], (instregex "ISTT_FP64m")>;
-def: InstRW<[SKLWriteResGroup76], (instregex "IST_F16m")>;
-def: InstRW<[SKLWriteResGroup76], (instregex "IST_F32m")>;
-def: InstRW<[SKLWriteResGroup76], (instregex "IST_FP16m")>;
-def: InstRW<[SKLWriteResGroup76], (instregex "IST_FP32m")>;
-def: InstRW<[SKLWriteResGroup76], (instregex "IST_FP64m")>;
-
-def SKLWriteResGroup77 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
- let Latency = 3;
- let NumMicroOps = 4;
- let ResourceCycles = [1,2,1];
-}
-def: InstRW<[SKLWriteResGroup77], (instregex "MMX_PHADDSWrm64")>;
-def: InstRW<[SKLWriteResGroup77], (instregex "MMX_PHSUBSWrm64")>;
+def: InstRW<[SKLWriteResGroup43], (instregex "FNSTSWm")>;
-def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
+def SKLWriteResGroup44 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
let Latency = 3;
let NumMicroOps = 4;
- let ResourceCycles = [2,1,1];
+ let ResourceCycles = [1,1,2];
}
-def: InstRW<[SKLWriteResGroup78], (instregex "PHADDSWrm128")>;
-def: InstRW<[SKLWriteResGroup78], (instregex "PHSUBSWrm128")>;
-def: InstRW<[SKLWriteResGroup78], (instregex "VPHADDSWrm128")>;
-def: InstRW<[SKLWriteResGroup78], (instregex "VPHADDSWrm256")>;
-def: InstRW<[SKLWriteResGroup78], (instregex "VPHSUBSWrm128")>;
-def: InstRW<[SKLWriteResGroup78], (instregex "VPHSUBSWrm256")>;
+def: InstRW<[SKLWriteResGroup44], (instregex "SETAm")>;
+def: InstRW<[SKLWriteResGroup44], (instregex "SETBEm")>;
-def SKLWriteResGroup79 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort05]> {
+def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> {
let Latency = 3;
let NumMicroOps = 4;
- let ResourceCycles = [2,1,1];
+ let ResourceCycles = [1,1,1,1];
}
-def: InstRW<[SKLWriteResGroup79], (instregex "MMX_PHADDWrm64")>;
-def: InstRW<[SKLWriteResGroup79], (instregex "MMX_PHADDrm64")>;
-def: InstRW<[SKLWriteResGroup79], (instregex "MMX_PHSUBDrm64")>;
-def: InstRW<[SKLWriteResGroup79], (instregex "MMX_PHSUBWrm64")>;
+def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>;
-def SKLWriteResGroup80 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
+def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> {
let Latency = 3;
let NumMicroOps = 4;
- let ResourceCycles = [2,1,1];
-}
-def: InstRW<[SKLWriteResGroup80], (instregex "PHADDDrm")>;
-def: InstRW<[SKLWriteResGroup80], (instregex "PHADDWrm")>;
-def: InstRW<[SKLWriteResGroup80], (instregex "PHSUBDrm")>;
-def: InstRW<[SKLWriteResGroup80], (instregex "PHSUBWrm")>;
-def: InstRW<[SKLWriteResGroup80], (instregex "VPHADDDYrm")>;
-def: InstRW<[SKLWriteResGroup80], (instregex "VPHADDDrm")>;
-def: InstRW<[SKLWriteResGroup80], (instregex "VPHADDWYrm")>;
-def: InstRW<[SKLWriteResGroup80], (instregex "VPHADDWrm")>;
-def: InstRW<[SKLWriteResGroup80], (instregex "VPHSUBDYrm")>;
-def: InstRW<[SKLWriteResGroup80], (instregex "VPHSUBDrm")>;
-def: InstRW<[SKLWriteResGroup80], (instregex "VPHSUBWYrm")>;
-def: InstRW<[SKLWriteResGroup80], (instregex "VPHSUBWrm")>;
-
-def SKLWriteResGroup81 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06]> {
- let Latency = 3;
- let NumMicroOps = 5;
- let ResourceCycles = [1,1,3];
-}
-def: InstRW<[SKLWriteResGroup81], (instregex "ROR(16|32|64)mCL")>;
-def: InstRW<[SKLWriteResGroup81], (instregex "ROR8mCL")>;
-
-def SKLWriteResGroup82 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
- let Latency = 3;
- let NumMicroOps = 5;
- let ResourceCycles = [1,1,1,2];
-}
-def: InstRW<[SKLWriteResGroup82], (instregex "RCL(16|32|64)m1")>;
-def: InstRW<[SKLWriteResGroup82], (instregex "RCL(16|32|64)mi")>;
-def: InstRW<[SKLWriteResGroup82], (instregex "RCL8m1")>;
-def: InstRW<[SKLWriteResGroup82], (instregex "RCL8mi")>;
-def: InstRW<[SKLWriteResGroup82], (instregex "RCR(16|32|64)m1")>;
-def: InstRW<[SKLWriteResGroup82], (instregex "RCR(16|32|64)mi")>;
-def: InstRW<[SKLWriteResGroup82], (instregex "RCR8m1")>;
-def: InstRW<[SKLWriteResGroup82], (instregex "RCR8mi")>;
-
-def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
- let Latency = 3;
- let NumMicroOps = 6;
- let ResourceCycles = [1,1,1,3];
-}
-def: InstRW<[SKLWriteResGroup83], (instregex "ROL(16|32|64)mCL")>;
-def: InstRW<[SKLWriteResGroup83], (instregex "ROL8mCL")>;
-def: InstRW<[SKLWriteResGroup83], (instregex "SAR(16|32|64)mCL")>;
-def: InstRW<[SKLWriteResGroup83], (instregex "SAR8mCL")>;
-def: InstRW<[SKLWriteResGroup83], (instregex "SHL(16|32|64)mCL")>;
-def: InstRW<[SKLWriteResGroup83], (instregex "SHL8mCL")>;
-def: InstRW<[SKLWriteResGroup83], (instregex "SHR(16|32|64)mCL")>;
-def: InstRW<[SKLWriteResGroup83], (instregex "SHR8mCL")>;
-
-def SKLWriteResGroup84 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
- let Latency = 3;
- let NumMicroOps = 6;
- let ResourceCycles = [1,1,1,3];
-}
-def: InstRW<[SKLWriteResGroup84], (instregex "ADC(16|32|64)mi8")>;
-def: InstRW<[SKLWriteResGroup84], (instregex "ADC8mi")>;
-
-def SKLWriteResGroup85 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
- let Latency = 3;
- let NumMicroOps = 6;
- let ResourceCycles = [1,1,1,2,1];
+ let ResourceCycles = [1,1,1,1];
}
-def: InstRW<[SKLWriteResGroup85], (instregex "ADC(16|32|64)mr")>;
-def: InstRW<[SKLWriteResGroup85], (instregex "ADC8mr")>;
-def: InstRW<[SKLWriteResGroup85], (instregex "CMPXCHG(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup85], (instregex "CMPXCHG8rm")>;
-def: InstRW<[SKLWriteResGroup85], (instregex "SBB(16|32|64)mi8")>;
-def: InstRW<[SKLWriteResGroup85], (instregex "SBB(16|32|64)mr")>;
-def: InstRW<[SKLWriteResGroup85], (instregex "SBB8mi")>;
-def: InstRW<[SKLWriteResGroup85], (instregex "SBB8mr")>;
+def: InstRW<[SKLWriteResGroup46], (instregex "CALL64pcrel32")>;
-def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0]> {
+def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> {
let Latency = 4;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup86], (instregex "AESDECLASTrr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "AESDECrr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "AESENCLASTrr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "AESENCrr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "MMX_PMADDUBSWrr64")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "MMX_PMADDWDirr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "MMX_PMULHRSWrr64")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "MMX_PMULHUWirr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "MMX_PMULHWirr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "MMX_PMULLWirr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "MMX_PMULUDQirr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "MUL_FPrST0")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "MUL_FST0r")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "MUL_FrST0")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "RCPPSr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "RCPSSr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "RSQRTPSr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "RSQRTSSr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "VAESDECLASTrr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "VAESDECrr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "VAESENCLASTrr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "VAESENCrr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "VRCPPSYr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "VRCPPSr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "VRCPSSr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "VRSQRTPSYr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "VRSQRTPSr")>;
-def: InstRW<[SKLWriteResGroup86], (instregex "VRSQRTSSr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "AESDECLASTrr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "AESDECrr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "AESENCLASTrr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "AESENCrr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMADDUBSWrr64")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMADDWDirr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMULHRSWrr64")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMULHUWirr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMULHWirr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMULLWirr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "MMX_PMULUDQirr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "MUL_FPrST0")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "MUL_FST0r")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "MUL_FrST0")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "RCPPSr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "RCPSSr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "RSQRTPSr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "RSQRTSSr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "VAESDECLASTrr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "VAESDECrr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "VAESENCLASTrr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "VAESENCrr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "VRCPPSYr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "VRCPPSr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "VRCPSSr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "VRSQRTPSYr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "VRSQRTPSr")>;
+def: InstRW<[SKLWriteResGroup47], (instregex "VRSQRTSSr")>;
-def SKLWriteResGroup87 : SchedWriteRes<[SKLPort01]> {
+def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> {
let Latency = 4;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup87], (instregex "ADDPDrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "ADDPSrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "ADDSDrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "ADDSSrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "ADDSUBPDrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "ADDSUBPSrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "MULPDrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "MULPSrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "MULSDrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "MULSSrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "SUBPDrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "SUBPSrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "SUBSDrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "SUBSSrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VADDPDYrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VADDPDrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VADDPSYrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VADDPSrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VADDSDrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VADDSSrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VADDSUBPDYrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VADDSUBPDrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VADDSUBPSYrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VADDSUBPSrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD132PDYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD132PDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD132PSYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD132PSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD132SDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD132SSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD213PDYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD213PDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD213PSYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD213PSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD213SDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD213SSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD231PDYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD231PDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD231PSYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD231PSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD231SDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADD231SSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB132PDYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB132PDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB132PSYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB132PSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB213PDYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB213PDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB213PSYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB213PSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB231PDYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB231PDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB231PSYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMADDSUB231PSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB132PDYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB132PDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB132PSYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB132PSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB132SDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB132SSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB213PDYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB213PDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB213PSYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB213PSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB213SDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB213SSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB231PDYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB231PDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB231PSYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB231PSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB231SDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUB231SSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD132PDYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD132PDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD132PSYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD132PSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD213PDYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD213PDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD213PSYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD213PSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD231PDYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD231PDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD231PSYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFMSUBADD231PSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD132PDYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD132PDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD132PSYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD132PSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD132SDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD132SSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD213PDYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD213PDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD213PSYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD213PSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD213SDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD213SSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD231PDYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD231PDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD231PSYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD231PSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD231SDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMADD231SSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB132PDYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB132PDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB132PSYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB132PSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB132SDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB132SSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB213PDYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB213PDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB213PSYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB213PSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB213SDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB213SSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB231PDYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB231PDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB231PSYr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB231PSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB231SDr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VFNMSUB231SSr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VMULPDYrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VMULPDrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VMULPSYrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VMULPSrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VMULSDrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VMULSSrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VSUBPDYrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VSUBPDrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VSUBPSYrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VSUBPSrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VSUBSDrr")>;
-def: InstRW<[SKLWriteResGroup87], (instregex "VSUBSSrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "ADDPDrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "ADDPSrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "ADDSDrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "ADDSSrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "ADDSUBPDrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "ADDSUBPSrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "MULPDrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "MULPSrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "MULSDrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "MULSSrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "SUBPDrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "SUBPSrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "SUBSDrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "SUBSSrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VADDPDYrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VADDPDrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VADDPSYrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VADDPSrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VADDSDrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VADDSSrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VADDSUBPDYrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VADDSUBPDrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VADDSUBPSYrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VADDSUBPSrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD132PDYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD132PDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD132PSYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD132PSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD132SDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD132SSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD213PDYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD213PDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD213PSYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD213PSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD213SDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD213SSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD231PDYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD231PDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD231PSYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD231PSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD231SDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADD231SSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB132PDYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB132PDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB132PSYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB132PSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB213PDYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB213PDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB213PSYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB213PSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB231PDYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB231PDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB231PSYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMADDSUB231PSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB132PDYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB132PDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB132PSYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB132PSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB132SDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB132SSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB213PDYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB213PDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB213PSYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB213PSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB213SDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB213SSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB231PDYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB231PDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB231PSYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB231PSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB231SDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUB231SSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD132PDYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD132PDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD132PSYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD132PSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD213PDYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD213PDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD213PSYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD213PSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD231PDYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD231PDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD231PSYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFMSUBADD231PSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD132PDYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD132PDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD132PSYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD132PSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD132SDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD132SSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD213PDYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD213PDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD213PSYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD213PSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD213SDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD213SSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD231PDYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD231PDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD231PSYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD231PSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD231SDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMADD231SSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB132PDYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB132PDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB132PSYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB132PSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB132SDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB132SSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB213PDYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB213PDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB213PSYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB213PSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB213SDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB213SSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB231PDYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB231PDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB231PSYr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB231PSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB231SDr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VFNMSUB231SSr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VMULPDYrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VMULPDrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VMULPSYrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VMULPSrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VMULSDrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VMULSSrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VSUBPDYrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VSUBPDrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VSUBPSYrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VSUBPSrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VSUBSDrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "VSUBSSrr")>;
-def SKLWriteResGroup89 : SchedWriteRes<[SKLPort015]> {
+def SKLWriteResGroup49 : SchedWriteRes<[SKLPort015]> {
let Latency = 4;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup89], (instregex "CMPPDrri")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "CMPPSrri")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "CMPSSrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "CVTDQ2PSrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "CVTPS2DQrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "CVTTPS2DQrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "MAXPDrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "MAXPSrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "MAXSDrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "MAXSSrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "MINPDrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "MINPSrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "MINSDrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "MINSSrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "PHMINPOSUWrr128")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "PMADDUBSWrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "PMADDWDrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "PMULDQrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "PMULHRSWrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "PMULHUWrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "PMULHWrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "PMULLWrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "PMULUDQrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VCMPPDYrri")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VCMPPDrri")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VCMPPSYrri")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VCMPPSrri")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VCMPSDrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VCMPSSrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VCVTDQ2PSYrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VCVTDQ2PSrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPS2DQYrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPS2DQrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VCVTTPS2DQYrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VCVTTPS2DQrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VMAXPDYrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VMAXPDrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VMAXPSYrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VMAXPSrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VMAXSDrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VMAXSSrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VMINPDYrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VMINPDrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VMINPSYrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VMINPSrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VMINSDrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VMINSSrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VPHMINPOSUWrr128")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMADDUBSWYrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMADDUBSWrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMADDWDYrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMADDWDrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULDQYrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULDQrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULHRSWYrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULHRSWrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULHUWYrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULHUWrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULHWYrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULHWrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULLWYrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULLWrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULUDQYrr")>;
-def: InstRW<[SKLWriteResGroup89], (instregex "VPMULUDQrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "CMPPDrri")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "CMPPSrri")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "CMPSSrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "CVTDQ2PSrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "CVTPS2DQrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "CVTTPS2DQrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "MAXPDrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "MAXPSrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "MAXSDrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "MAXSSrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "MINPDrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "MINPSrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "MINSDrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "MINSSrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "PHMINPOSUWrr128")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "PMADDUBSWrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "PMADDWDrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "PMULDQrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "PMULHRSWrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "PMULHUWrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "PMULHWrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "PMULLWrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "PMULUDQrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VCMPPDYrri")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VCMPPDrri")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VCMPPSYrri")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VCMPPSrri")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VCMPSDrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VCMPSSrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VCVTDQ2PSYrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VCVTDQ2PSrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VCVTPS2DQYrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VCVTPS2DQrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VCVTTPS2DQYrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VCVTTPS2DQrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VMAXPDYrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VMAXPDrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VMAXPSYrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VMAXPSrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VMAXSDrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VMAXSSrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VMINPDYrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VMINPDrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VMINPSYrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VMINPSrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VMINSDrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VMINSSrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VPHMINPOSUWrr128")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDUBSWYrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDUBSWrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDWDYrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMADDWDrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULDQYrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULDQrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHRSWYrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHRSWrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHUWYrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHUWrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHWYrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULHWrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULLWYrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULLWrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULUDQYrr")>;
+def: InstRW<[SKLWriteResGroup49], (instregex "VPMULUDQrr")>;
-def SKLWriteResGroup90 : SchedWriteRes<[SKLPort5]> {
+def SKLWriteResGroup50 : SchedWriteRes<[SKLPort5]> {
let Latency = 4;
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[SKLWriteResGroup90], (instregex "MPSADBWrri")>;
-def: InstRW<[SKLWriteResGroup90], (instregex "VMPSADBWYrri")>;
-def: InstRW<[SKLWriteResGroup90], (instregex "VMPSADBWrri")>;
-
-def SKLWriteResGroup91 : SchedWriteRes<[SKLPort0,SKLPort23]> {
- let Latency = 4;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup91], (instregex "AESDECLASTrm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "AESDECrm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "AESENCLASTrm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "AESENCrm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "MMX_CVTPI2PSirm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "MMX_PMADDUBSWrm64")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "MMX_PMADDWDirm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "MMX_PMULHRSWrm64")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "MMX_PMULHUWirm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "MMX_PMULHWirm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "MMX_PMULLWirm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "MMX_PMULUDQirm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "MUL_F32m")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "MUL_F64m")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "RCPPSm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "RCPSSm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "RSQRTPSm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "RSQRTSSm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "VAESDECLASTrm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "VAESDECrm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "VAESENCLASTrm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "VAESENCrm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "VRCPPSYm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "VRCPPSm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "VRCPSSm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "VRSQRTPSYm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "VRSQRTPSm")>;
-def: InstRW<[SKLWriteResGroup91], (instregex "VRSQRTSSm")>;
+def: InstRW<[SKLWriteResGroup50], (instregex "MPSADBWrri")>;
+def: InstRW<[SKLWriteResGroup50], (instregex "VMPSADBWYrri")>;
+def: InstRW<[SKLWriteResGroup50], (instregex "VMPSADBWrri")>;
-def SKLWriteResGroup92 : SchedWriteRes<[SKLPort1,SKLPort5]> {
+def SKLWriteResGroup51 : SchedWriteRes<[SKLPort1,SKLPort5]> {
let Latency = 4;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup92], (instregex "IMUL64r")>;
-def: InstRW<[SKLWriteResGroup92], (instregex "MUL64r")>;
-def: InstRW<[SKLWriteResGroup92], (instregex "MULX64rr")>;
+def: InstRW<[SKLWriteResGroup51], (instregex "IMUL64r")>;
+def: InstRW<[SKLWriteResGroup51], (instregex "MUL64r")>;
+def: InstRW<[SKLWriteResGroup51], (instregex "MULX64rr")>;
-def SKLWriteResGroup92_16 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
+def SKLWriteResGroup51_16 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
let Latency = 4;
- let NumMicroOps = 4;
+ let NumMicroOps = 4;
}
-def: InstRW<[SKLWriteResGroup92_16], (instregex "IMUL16r")>;
-def: InstRW<[SKLWriteResGroup92_16], (instregex "MUL16r")>;
+def: InstRW<[SKLWriteResGroup51_16], (instregex "IMUL16r")>;
+def: InstRW<[SKLWriteResGroup51_16], (instregex "MUL16r")>;
-def SKLWriteResGroup93 : SchedWriteRes<[SKLPort5,SKLPort01]> {
+def SKLWriteResGroup52 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let Latency = 4;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup93], (instregex "VPSLLDYrr")>;
-def: InstRW<[SKLWriteResGroup93], (instregex "VPSLLQYrr")>;
-def: InstRW<[SKLWriteResGroup93], (instregex "VPSLLWYrr")>;
-def: InstRW<[SKLWriteResGroup93], (instregex "VPSRADYrr")>;
-def: InstRW<[SKLWriteResGroup93], (instregex "VPSRAWYrr")>;
-def: InstRW<[SKLWriteResGroup93], (instregex "VPSRLDYrr")>;
-def: InstRW<[SKLWriteResGroup93], (instregex "VPSRLQYrr")>;
-def: InstRW<[SKLWriteResGroup93], (instregex "VPSRLWYrr")>;
+def: InstRW<[SKLWriteResGroup52], (instregex "VPSLLDYrr")>;
+def: InstRW<[SKLWriteResGroup52], (instregex "VPSLLQYrr")>;
+def: InstRW<[SKLWriteResGroup52], (instregex "VPSLLWYrr")>;
+def: InstRW<[SKLWriteResGroup52], (instregex "VPSRADYrr")>;
+def: InstRW<[SKLWriteResGroup52], (instregex "VPSRAWYrr")>;
+def: InstRW<[SKLWriteResGroup52], (instregex "VPSRLDYrr")>;
+def: InstRW<[SKLWriteResGroup52], (instregex "VPSRLQYrr")>;
+def: InstRW<[SKLWriteResGroup52], (instregex "VPSRLWYrr")>;
-def SKLWriteResGroup94 : SchedWriteRes<[SKLPort01,SKLPort23]> {
+def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {
let Latency = 4;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup94], (instregex "ADDPDrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "ADDPSrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "ADDSDrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "ADDSSrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "ADDSUBPDrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "ADDSUBPSrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "MULPDrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "MULPSrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "MULSDrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "MULSSrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "SUBPDrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "SUBPSrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "SUBSDrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "SUBSSrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VADDPDYrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VADDPDrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VADDPSYrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VADDPSrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VADDSDrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VADDSSrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VADDSUBPDYrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VADDSUBPDrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VADDSUBPSYrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VADDSUBPSrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD132PDYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD132PDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD132PSYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD132PSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD132SDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD132SSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD213PDYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD213PDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD213PSYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD213PSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD213SDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD213SSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD231PDYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD231PDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD231PSYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD231PSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD231SDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADD231SSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB132PDYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB132PDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB132PSYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB132PSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB213PDYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB213PDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB213PSYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB213PSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB231PDYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB231PDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB231PSYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMADDSUB231PSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB132PDYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB132PDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB132PSYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB132PSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB132SDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB132SSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB213PDYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB213PDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB213PSYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB213PSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB213SDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB213SSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB231PDYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB231PDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB231PSYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB231PSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB231SDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUB231SSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD132PDYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD132PDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD132PSYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD132PSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD213PDYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD213PDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD213PSYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD213PSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD231PDYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD231PDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD231PSYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFMSUBADD231PSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD132PDYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD132PDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD132PSYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD132PSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD132SDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD132SSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD213PDYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD213PDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD213PSYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD213PSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD213SDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD213SSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD231PDYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD231PDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD231PSYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD231PSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD231SDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMADD231SSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB132PDYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB132PDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB132PSYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB132PSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB132SDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB132SSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB213PDYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB213PDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB213PSYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB213PSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB213SDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB213SSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB231PDYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB231PDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB231PSYm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB231PSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB231SDm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VFNMSUB231SSm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VMULPDYrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VMULPDrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VMULPSYrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VMULPSrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VMULSDrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VMULSSrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VSUBPDYrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VSUBPDrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VSUBPSYrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VSUBPSrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VSUBSDrm")>;
-def: InstRW<[SKLWriteResGroup94], (instregex "VSUBSSrm")>;
+def: InstRW<[SKLWriteResGroup53], (instregex "ISTT_FP16m")>;
+def: InstRW<[SKLWriteResGroup53], (instregex "ISTT_FP32m")>;
+def: InstRW<[SKLWriteResGroup53], (instregex "ISTT_FP64m")>;
+def: InstRW<[SKLWriteResGroup53], (instregex "IST_F16m")>;
+def: InstRW<[SKLWriteResGroup53], (instregex "IST_F32m")>;
+def: InstRW<[SKLWriteResGroup53], (instregex "IST_FP16m")>;
+def: InstRW<[SKLWriteResGroup53], (instregex "IST_FP32m")>;
+def: InstRW<[SKLWriteResGroup53], (instregex "IST_FP64m")>;
-def SKLWriteResGroup96 : SchedWriteRes<[SKLPort23,SKLPort015]> {
- let Latency = 4;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup96], (instregex "CMPPDrmi")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "CMPPSrmi")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "CMPSSrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "CVTDQ2PSrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "CVTPS2DQrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "CVTPS2PDrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "CVTSS2SDrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "CVTTPS2DQrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "MAXPDrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "MAXPSrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "MAXSDrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "MAXSSrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "MINPDrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "MINPSrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "MINSDrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "MINSSrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "MMX_CVTPS2PIirm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "MMX_CVTTPS2PIirm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "PHMINPOSUWrm128")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "PMADDUBSWrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "PMADDWDrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "PMULDQrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "PMULHRSWrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "PMULHUWrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "PMULHWrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "PMULLWrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "PMULUDQrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VCMPPDYrmi")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VCMPPDrmi")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VCMPPSYrmi")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VCMPPSrmi")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VCMPSDrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VCMPSSrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTDQ2PSYrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTDQ2PSrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTPH2PSYrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTPH2PSrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTPS2DQYrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTPS2DQrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTPS2PDYrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTPS2PDrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTSS2SDrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTTPS2DQYrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VCVTTPS2DQrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VMAXPDYrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VMAXPDrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VMAXPSYrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VMAXPSrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VMAXSDrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VMAXSSrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VMINPDYrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VMINPDrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VMINPSYrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VMINPSrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VMINSDrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VMINSSrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VPHMINPOSUWrm128")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMADDUBSWYrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMADDUBSWrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMADDWDYrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMADDWDrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULDQYrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULDQrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULHRSWYrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULHRSWrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULHUWYrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULHUWrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULHWYrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULHWrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULLWYrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULLWrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULUDQYrm")>;
-def: InstRW<[SKLWriteResGroup96], (instregex "VPMULUDQrm")>;
-
-def SKLWriteResGroup97 : SchedWriteRes<[SKLPort5,SKLPort23]> {
- let Latency = 4;
- let NumMicroOps = 3;
- let ResourceCycles = [2,1];
-}
-def: InstRW<[SKLWriteResGroup97], (instregex "FICOM16m")>;
-def: InstRW<[SKLWriteResGroup97], (instregex "FICOM32m")>;
-def: InstRW<[SKLWriteResGroup97], (instregex "FICOMP16m")>;
-def: InstRW<[SKLWriteResGroup97], (instregex "FICOMP32m")>;
-def: InstRW<[SKLWriteResGroup97], (instregex "MPSADBWrmi")>;
-def: InstRW<[SKLWriteResGroup97], (instregex "VMPSADBWYrmi")>;
-def: InstRW<[SKLWriteResGroup97], (instregex "VMPSADBWrmi")>;
-
-def SKLWriteResGroup98 : SchedWriteRes<[SKLPort1,SKLPort5,SKLPort23]> {
- let Latency = 4;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SKLWriteResGroup98], (instregex "MULX64rm")>;
-
-def SKLWriteResGroup100 : SchedWriteRes<[SKLPort0156]> {
+def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> {
let Latency = 4;
let NumMicroOps = 4;
let ResourceCycles = [4];
}
-def: InstRW<[SKLWriteResGroup100], (instregex "FNCLEX")>;
+def: InstRW<[SKLWriteResGroup54], (instregex "FNCLEX")>;
-def SKLWriteResGroup101 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
+def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
let Latency = 4;
let NumMicroOps = 4;
let ResourceCycles = [1,3];
}
-def: InstRW<[SKLWriteResGroup101], (instregex "PAUSE")>;
+def: InstRW<[SKLWriteResGroup55], (instregex "PAUSE")>;
-def SKLWriteResGroup102 : SchedWriteRes<[SKLPort015,SKLPort0156]> {
+def SKLWriteResGroup56 : SchedWriteRes<[SKLPort015,SKLPort0156]> {
let Latency = 4;
let NumMicroOps = 4;
let ResourceCycles = [1,3];
}
-def: InstRW<[SKLWriteResGroup102], (instregex "VZEROUPPER")>;
+def: InstRW<[SKLWriteResGroup56], (instregex "VZEROUPPER")>;
-def SKLWriteResGroup103 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> {
+def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> {
let Latency = 4;
let NumMicroOps = 4;
let ResourceCycles = [1,1,2];
}
-def: InstRW<[SKLWriteResGroup103], (instregex "LAR(16|32|64)rr")>;
-
-def SKLWriteResGroup105 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort0156]> {
- let Latency = 4;
- let NumMicroOps = 4;
- let ResourceCycles = [1,1,1,1];
-}
-def: InstRW<[SKLWriteResGroup105], (instregex "SHLD(16|32|64)mri8")>;
-def: InstRW<[SKLWriteResGroup105], (instregex "SHRD(16|32|64)mri8")>;
-
-def SKLWriteResGroup106 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
- let Latency = 4;
- let NumMicroOps = 5;
- let ResourceCycles = [1,2,1,1];
-}
-def: InstRW<[SKLWriteResGroup106], (instregex "LAR(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup106], (instregex "LSL(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
-def SKLWriteResGroup107 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
- let Latency = 4;
- let NumMicroOps = 6;
- let ResourceCycles = [1,1,4];
+def SKLWriteResGroup58 : SchedWriteRes<[SKLPort23]> {
+ let Latency = 5;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup107], (instregex "PUSHF16")>;
-def: InstRW<[SKLWriteResGroup107], (instregex "PUSHF64")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "MMX_MOVD64from64rm")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "MMX_MOVD64rm")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "MMX_MOVD64to64rm")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "MMX_MOVQ64rm")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "MOV(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "MOV64toPQIrm")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "MOV8rm")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "MOVDDUPrm")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "MOVDI2PDIrm")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "MOVSSrm")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm16")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm32")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm8")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "MOVZX(16|32|64)rm16")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "MOVZX(16|32|64)rm8")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "PREFETCHNTA")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "PREFETCHT0")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "PREFETCHT1")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "PREFETCHT2")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "VMOV64toPQIrm")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "VMOVDDUPrm")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "VMOVDI2PDIrm")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "VMOVQI2PQIrm")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "VMOVSDrm")>;
+def: InstRW<[SKLWriteResGroup58], (instregex "VMOVSSrm")>;
-def SKLWriteResGroup109 : SchedWriteRes<[SKLPort0,SKLPort5]> {
+def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> {
let Latency = 5;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup109], (instregex "CVTDQ2PDrr")>;
-def: InstRW<[SKLWriteResGroup109], (instregex "MMX_CVTPI2PDirr")>;
-def: InstRW<[SKLWriteResGroup109], (instregex "VCVTDQ2PDrr")>;
+def: InstRW<[SKLWriteResGroup59], (instregex "CVTDQ2PDrr")>;
+def: InstRW<[SKLWriteResGroup59], (instregex "MMX_CVTPI2PDirr")>;
+def: InstRW<[SKLWriteResGroup59], (instregex "VCVTDQ2PDrr")>;
-def SKLWriteResGroup110 : SchedWriteRes<[SKLPort5,SKLPort015]> {
+def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> {
let Latency = 5;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup110], (instregex "CVTPD2DQrr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "CVTPD2PSrr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "CVTPS2PDrr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "CVTSD2SSrr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "CVTSI2SD64rr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "CVTSI2SDrr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "CVTSI2SSrr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "CVTSS2SDrr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "CVTTPD2DQrr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "MMX_CVTPD2PIirr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "MMX_CVTPS2PIirr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "MMX_CVTTPD2PIirr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "MMX_CVTTPS2PIirr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTPD2DQrr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTPD2PSrr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTPH2PSrr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTPS2PDrr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTPS2PHrr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTSD2SSrr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTSI2SD64rr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTSI2SDrr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTSI2SSrr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTSS2SDrr")>;
-def: InstRW<[SKLWriteResGroup110], (instregex "VCVTTPD2DQrr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "CVTPD2DQrr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "CVTPD2PSrr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "CVTPS2PDrr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "CVTSD2SSrr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "CVTSI2SD64rr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "CVTSI2SDrr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "CVTSI2SSrr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "CVTSS2SDrr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "CVTTPD2DQrr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVTPD2PIirr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVTPS2PIirr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVTTPD2PIirr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVTTPS2PIirr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTPD2DQrr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTPD2PSrr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTPH2PSrr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTPS2PDrr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTPS2PHrr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTSD2SSrr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTSI2SD64rr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTSI2SDrr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTSI2SSrr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTSS2SDrr")>;
+def: InstRW<[SKLWriteResGroup60], (instregex "VCVTTPD2DQrr")>;
-def SKLWriteResGroup113 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
+def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> {
let Latency = 5;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup113], (instregex "CVTDQ2PDrm")>;
-def: InstRW<[SKLWriteResGroup113], (instregex "MMX_CVTPI2PDirm")>;
-def: InstRW<[SKLWriteResGroup113], (instregex "VCVTDQ2PDrm")>;
+def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>;
-def SKLWriteResGroup114 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> {
+def SKLWriteResGroup62 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
let Latency = 5;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup114], (instregex "STR(16|32|64)r")>;
+def: InstRW<[SKLWriteResGroup62], (instregex "IMUL32r")>;
+def: InstRW<[SKLWriteResGroup62], (instregex "MUL32r")>;
+def: InstRW<[SKLWriteResGroup62], (instregex "MULX32rr")>;
-def SKLWriteResGroup115 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
+def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
let Latency = 5;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
+ let NumMicroOps = 5;
+ let ResourceCycles = [1,4];
}
-def: InstRW<[SKLWriteResGroup115], (instregex "IMUL32r")>;
-def: InstRW<[SKLWriteResGroup115], (instregex "MUL32r")>;
-def: InstRW<[SKLWriteResGroup115], (instregex "MULX32rr")>;
+def: InstRW<[SKLWriteResGroup63], (instregex "XSETBV")>;
-def SKLWriteResGroup116 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
+def SKLWriteResGroup64 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
let Latency = 5;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
+ let NumMicroOps = 5;
+ let ResourceCycles = [2,3];
}
-def: InstRW<[SKLWriteResGroup116], (instregex "CVTPD2DQrm")>;
-def: InstRW<[SKLWriteResGroup116], (instregex "CVTPD2PSrm")>;
-def: InstRW<[SKLWriteResGroup116], (instregex "CVTSD2SSrm")>;
-def: InstRW<[SKLWriteResGroup116], (instregex "CVTTPD2DQrm")>;
-def: InstRW<[SKLWriteResGroup116], (instregex "MMX_CVTPD2PIirm")>;
-def: InstRW<[SKLWriteResGroup116], (instregex "MMX_CVTTPD2PIirm")>;
-def: InstRW<[SKLWriteResGroup116], (instregex "VCVTSD2SSrm")>;
+def: InstRW<[SKLWriteResGroup64], (instregex "CMPXCHG(16|32|64)rr")>;
+def: InstRW<[SKLWriteResGroup64], (instregex "CMPXCHG8rr")>;
-def SKLWriteResGroup118 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort06,SKLPort0156]> {
+def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
let Latency = 5;
- let NumMicroOps = 4;
- let ResourceCycles = [1,1,1,1];
+ let NumMicroOps = 6;
+ let ResourceCycles = [1,1,4];
}
-def: InstRW<[SKLWriteResGroup118], (instregex "MULX32rm")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF16")>;
+def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF64")>;
-def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237,SKLPort015]> {
- let Latency = 5;
- let NumMicroOps = 4;
- let ResourceCycles = [1,1,1,1];
+def SKLWriteResGroup66 : SchedWriteRes<[SKLPort5]> {
+ let Latency = 6;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup119], (instregex "VCVTPS2PHmr")>;
+def: InstRW<[SKLWriteResGroup66], (instregex "PCLMULQDQrr")>;
+def: InstRW<[SKLWriteResGroup66], (instregex "VPCLMULQDQrr")>;
-def SKLWriteResGroup120 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
- let Latency = 5;
- let NumMicroOps = 5;
- let ResourceCycles = [1,4];
+def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> {
+ let Latency = 6;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup120], (instregex "XSETBV")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "LDDQUrm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "MOVAPDrm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "MOVAPSrm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "MOVDQArm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "MOVDQUrm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "MOVNTDQArm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "MOVSHDUPrm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "MOVSLDUPrm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "MOVUPDrm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "MOVUPSrm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "VBROADCASTSSrm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "VLDDQUrm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "VMOVAPDrm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "VMOVAPSrm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "VMOVDQArm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "VMOVDQUrm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "VMOVNTDQArm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "VMOVSHDUPrm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "VMOVSLDUPrm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "VMOVUPDrm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "VMOVUPSrm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "VPBROADCASTDrm")>;
+def: InstRW<[SKLWriteResGroup67], (instregex "VPBROADCASTQrm")>;
-def SKLWriteResGroup121 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
- let Latency = 5;
- let NumMicroOps = 5;
- let ResourceCycles = [2,3];
+def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+ let ResourceCycles = [2];
}
-def: InstRW<[SKLWriteResGroup121], (instregex "CMPXCHG(16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup121], (instregex "CMPXCHG8rr")>;
+def: InstRW<[SKLWriteResGroup68], (instregex "MMX_CVTPI2PSirr")>;
-def SKLWriteResGroup122 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
- let Latency = 5;
- let NumMicroOps = 8;
- let ResourceCycles = [1,1,1,1,1,3];
+def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup122], (instregex "ADD8mi")>;
-def: InstRW<[SKLWriteResGroup122], (instregex "AND8mi")>;
-def: InstRW<[SKLWriteResGroup122], (instregex "OR8mi")>;
-def: InstRW<[SKLWriteResGroup122], (instregex "SUB8mi")>;
-def: InstRW<[SKLWriteResGroup122], (instregex "XCHG(16|32|64)rm")>;
-def: InstRW<[SKLWriteResGroup122], (instregex "XCHG8rm")>;
-def: InstRW<[SKLWriteResGroup122], (instregex "XOR8mi")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PADDSBirm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PADDSWirm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PADDUSBirm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PADDUSWirm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PAVGBirm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PAVGWirm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PCMPEQBirm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PCMPEQDirm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PCMPEQWirm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PCMPGTBirm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PCMPGTDirm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PCMPGTWirm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PMAXSWirm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PMAXUBirm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PMINSWirm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PMINUBirm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSLLDrm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSLLQrm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSLLWrm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSRADrm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSRAWrm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSRLDrm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSRLQrm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSRLWrm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSUBSBirm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSUBSWirm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSUBUSBirm")>;
+def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PSUBUSWirm")>;
-def SKLWriteResGroup123 : SchedWriteRes<[SKLPort5]> {
+def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort015]> {
let Latency = 6;
- let NumMicroOps = 1;
- let ResourceCycles = [1];
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup123], (instregex "PCLMULQDQrr")>;
-def: InstRW<[SKLWriteResGroup123], (instregex "VPCLMULQDQrr")>;
+def: InstRW<[SKLWriteResGroup70], (instregex "CVTSD2SI64rr")>;
+def: InstRW<[SKLWriteResGroup70], (instregex "CVTSD2SIrr")>;
+def: InstRW<[SKLWriteResGroup70], (instregex "CVTSS2SI64rr")>;
+def: InstRW<[SKLWriteResGroup70], (instregex "CVTSS2SIrr")>;
+def: InstRW<[SKLWriteResGroup70], (instregex "CVTTSD2SI64rr")>;
+def: InstRW<[SKLWriteResGroup70], (instregex "CVTTSD2SIrr")>;
+def: InstRW<[SKLWriteResGroup70], (instregex "VCVTSD2SI64rr")>;
+def: InstRW<[SKLWriteResGroup70], (instregex "VCVTSD2SIrr")>;
+def: InstRW<[SKLWriteResGroup70], (instregex "VCVTSS2SI64rr")>;
+def: InstRW<[SKLWriteResGroup70], (instregex "VCVTSS2SIrr")>;
+def: InstRW<[SKLWriteResGroup70], (instregex "VCVTTSD2SI64rr")>;
+def: InstRW<[SKLWriteResGroup70], (instregex "VCVTTSD2SIrr")>;
-def SKLWriteResGroup124 : SchedWriteRes<[SKLPort0]> {
+def SKLWriteResGroup71 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 6;
let NumMicroOps = 2;
- let ResourceCycles = [2];
+ let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup124], (instregex "MMX_CVTPI2PSirr")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PALIGNR64irm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PINSRWirmi")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PSHUFBrm64")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PSHUFWmi")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PUNPCKHBWirm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PUNPCKHDQirm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PUNPCKHWDirm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PUNPCKLBWirm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PUNPCKLDQirm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PUNPCKLWDirm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "MOVHPDrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "MOVHPSrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "MOVLPDrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "MOVLPSrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "PINSRBrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "PINSRDrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "PINSRQrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "PINSRWrmi")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVSXBDrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVSXBQrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVSXBWrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVSXDQrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVSXWDrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVSXWQrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVZXBDrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVZXBQrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVZXBWrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVZXDQrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVZXWDrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "PMOVZXWQrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VMOVHPDrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VMOVHPSrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VMOVLPDrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VMOVLPSrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPINSRBrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPINSRDrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPINSRQrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPINSRWrmi")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVSXBDrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVSXBQrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVSXBWrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVSXDQrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVSXWDrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVSXWQrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVZXBDrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVZXBQrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVZXBWrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVZXDQrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVZXWDrm")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVZXWQrm")>;
-def SKLWriteResGroup125 : SchedWriteRes<[SKLPort0,SKLPort015]> {
+def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> {
let Latency = 6;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup125], (instregex "CVTSD2SI64rr")>;
-def: InstRW<[SKLWriteResGroup125], (instregex "CVTSD2SIrr")>;
-def: InstRW<[SKLWriteResGroup125], (instregex "CVTSS2SI64rr")>;
-def: InstRW<[SKLWriteResGroup125], (instregex "CVTSS2SIrr")>;
-def: InstRW<[SKLWriteResGroup125], (instregex "CVTTSD2SI64rr")>;
-def: InstRW<[SKLWriteResGroup125], (instregex "CVTTSD2SIrr")>;
-def: InstRW<[SKLWriteResGroup125], (instregex "VCVTSD2SI64rr")>;
-def: InstRW<[SKLWriteResGroup125], (instregex "VCVTSD2SIrr")>;
-def: InstRW<[SKLWriteResGroup125], (instregex "VCVTSS2SI64rr")>;
-def: InstRW<[SKLWriteResGroup125], (instregex "VCVTSS2SIrr")>;
-def: InstRW<[SKLWriteResGroup125], (instregex "VCVTTSD2SI64rr")>;
-def: InstRW<[SKLWriteResGroup125], (instregex "VCVTTSD2SIrr")>;
+def: InstRW<[SKLWriteResGroup72], (instregex "FARJMP64")>;
+def: InstRW<[SKLWriteResGroup72], (instregex "JMP(16|32|64)m")>;
-def SKLWriteResGroup126 : SchedWriteRes<[SKLPort5,SKLPort23]> {
+def SKLWriteResGroup73 : SchedWriteRes<[SKLPort23,SKLPort05]> {
let Latency = 6;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup126], (instregex "PCLMULQDQrm")>;
-def: InstRW<[SKLWriteResGroup126], (instregex "VPCLMULQDQrm")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PABSBrm64")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PABSDrm64")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PABSWrm64")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PADDBirm")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PADDDirm")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PADDQirm")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PADDWirm")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PANDNirm")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PANDirm")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PORirm")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSIGNBrm64")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSIGNDrm64")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSIGNWrm64")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSUBBirm")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSUBDirm")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSUBQirm")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PSUBWirm")>;
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PXORirm")>;
-def SKLWriteResGroup127 : SchedWriteRes<[SKLPort5,SKLPort01]> {
+def SKLWriteResGroup74 : SchedWriteRes<[SKLPort23,SKLPort06]> {
let Latency = 6;
- let NumMicroOps = 3;
- let ResourceCycles = [2,1];
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup127], (instregex "HADDPDrr")>;
-def: InstRW<[SKLWriteResGroup127], (instregex "HADDPSrr")>;
-def: InstRW<[SKLWriteResGroup127], (instregex "HSUBPDrr")>;
-def: InstRW<[SKLWriteResGroup127], (instregex "HSUBPSrr")>;
-def: InstRW<[SKLWriteResGroup127], (instregex "VHADDPDYrr")>;
-def: InstRW<[SKLWriteResGroup127], (instregex "VHADDPDrr")>;
-def: InstRW<[SKLWriteResGroup127], (instregex "VHADDPSYrr")>;
-def: InstRW<[SKLWriteResGroup127], (instregex "VHADDPSrr")>;
-def: InstRW<[SKLWriteResGroup127], (instregex "VHSUBPDYrr")>;
-def: InstRW<[SKLWriteResGroup127], (instregex "VHSUBPDrr")>;
-def: InstRW<[SKLWriteResGroup127], (instregex "VHSUBPSYrr")>;
-def: InstRW<[SKLWriteResGroup127], (instregex "VHSUBPSrr")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "ADC(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "ADC8rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "ADCX32rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "ADCX64rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "ADOX32rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "ADOX64rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVAE(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVB(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVE(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVG(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVGE(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVL(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVLE(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVNE(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVNO(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVNP(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVNS(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVO(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVP(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "CMOVS(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "RORX32mi")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "RORX64mi")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "SARX32rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "SARX64rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "SBB(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "SBB8rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "SHLX32rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "SHLX64rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "SHRX32rm")>;
+def: InstRW<[SKLWriteResGroup74], (instregex "SHRX64rm")>;
-def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort23]> {
+def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> {
let Latency = 6;
- let NumMicroOps = 3;
- let ResourceCycles = [2,1];
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup75], (instregex "ANDN32rm")>;
+def: InstRW<[SKLWriteResGroup75], (instregex "ANDN64rm")>;
+def: InstRW<[SKLWriteResGroup75], (instregex "BLSI32rm")>;
+def: InstRW<[SKLWriteResGroup75], (instregex "BLSI64rm")>;
+def: InstRW<[SKLWriteResGroup75], (instregex "BLSMSK32rm")>;
+def: InstRW<[SKLWriteResGroup75], (instregex "BLSMSK64rm")>;
+def: InstRW<[SKLWriteResGroup75], (instregex "BLSR32rm")>;
+def: InstRW<[SKLWriteResGroup75], (instregex "BLSR64rm")>;
+def: InstRW<[SKLWriteResGroup75], (instregex "BZHI32rm")>;
+def: InstRW<[SKLWriteResGroup75], (instregex "BZHI64rm")>;
+def: InstRW<[SKLWriteResGroup75], (instregex "MOVBE(16|32|64)rm")>;
+
+def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup128], (instregex "ADD_FI16m")>;
-def: InstRW<[SKLWriteResGroup128], (instregex "ADD_FI32m")>;
-def: InstRW<[SKLWriteResGroup128], (instregex "SUBR_FI16m")>;
-def: InstRW<[SKLWriteResGroup128], (instregex "SUBR_FI32m")>;
-def: InstRW<[SKLWriteResGroup128], (instregex "SUB_FI16m")>;
-def: InstRW<[SKLWriteResGroup128], (instregex "SUB_FI32m")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "ADD(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "ADD8rm")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "AND(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "AND8rm")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "CMP(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "CMP(16|32|64)mr")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "CMP(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "CMP8mi")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "CMP8mr")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "CMP8rm")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "OR(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "OR8rm")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)r")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "SUB(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "SUB8rm")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "TEST(16|32|64)mr")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "TEST8mi")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "TEST8mr")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "XOR(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup76], (instregex "XOR8rm")>;
-def SKLWriteResGroup129 : SchedWriteRes<[SKLPort5,SKLPort015]> {
+def SKLWriteResGroup77 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let Latency = 6;
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKLWriteResGroup129], (instregex "CVTSI2SS64rr")>;
-def: InstRW<[SKLWriteResGroup129], (instregex "VCVTSI2SS64rr")>;
+def: InstRW<[SKLWriteResGroup77], (instregex "HADDPDrr")>;
+def: InstRW<[SKLWriteResGroup77], (instregex "HADDPSrr")>;
+def: InstRW<[SKLWriteResGroup77], (instregex "HSUBPDrr")>;
+def: InstRW<[SKLWriteResGroup77], (instregex "HSUBPSrr")>;
+def: InstRW<[SKLWriteResGroup77], (instregex "VHADDPDYrr")>;
+def: InstRW<[SKLWriteResGroup77], (instregex "VHADDPDrr")>;
+def: InstRW<[SKLWriteResGroup77], (instregex "VHADDPSYrr")>;
+def: InstRW<[SKLWriteResGroup77], (instregex "VHADDPSrr")>;
+def: InstRW<[SKLWriteResGroup77], (instregex "VHSUBPDYrr")>;
+def: InstRW<[SKLWriteResGroup77], (instregex "VHSUBPDrr")>;
+def: InstRW<[SKLWriteResGroup77], (instregex "VHSUBPSYrr")>;
+def: InstRW<[SKLWriteResGroup77], (instregex "VHSUBPSrr")>;
-def SKLWriteResGroup130 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort015]> {
+def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort015]> {
let Latency = 6;
let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
+ let ResourceCycles = [2,1];
}
-def: InstRW<[SKLWriteResGroup130], (instregex "CVTSD2SI64rm")>;
-def: InstRW<[SKLWriteResGroup130], (instregex "CVTSD2SIrm")>;
-def: InstRW<[SKLWriteResGroup130], (instregex "CVTSS2SI64rm")>;
-def: InstRW<[SKLWriteResGroup130], (instregex "CVTSS2SIrm")>;
-def: InstRW<[SKLWriteResGroup130], (instregex "CVTTSD2SI64rm")>;
-def: InstRW<[SKLWriteResGroup130], (instregex "CVTTSD2SIrm")>;
-def: InstRW<[SKLWriteResGroup130], (instregex "CVTTSS2SIrm")>;
-def: InstRW<[SKLWriteResGroup130], (instregex "VCVTSD2SI64rm")>;
-def: InstRW<[SKLWriteResGroup130], (instregex "VCVTSD2SIrm")>;
-def: InstRW<[SKLWriteResGroup130], (instregex "VCVTSS2SI64rm")>;
-def: InstRW<[SKLWriteResGroup130], (instregex "VCVTSS2SIrm")>;
-def: InstRW<[SKLWriteResGroup130], (instregex "VCVTTSD2SI64rm")>;
-def: InstRW<[SKLWriteResGroup130], (instregex "VCVTTSD2SIrm")>;
-def: InstRW<[SKLWriteResGroup130], (instregex "VCVTTSS2SI64rm")>;
-def: InstRW<[SKLWriteResGroup130], (instregex "VCVTTSS2SIrm")>;
+def: InstRW<[SKLWriteResGroup78], (instregex "CVTSI2SS64rr")>;
+def: InstRW<[SKLWriteResGroup78], (instregex "VCVTSI2SS64rr")>;
-def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
+def SKLWriteResGroup79 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
let Latency = 6;
let NumMicroOps = 4;
let ResourceCycles = [1,2,1];
}
-def: InstRW<[SKLWriteResGroup131], (instregex "SHLD(16|32|64)rrCL")>;
-def: InstRW<[SKLWriteResGroup131], (instregex "SHRD(16|32|64)rrCL")>;
+def: InstRW<[SKLWriteResGroup79], (instregex "SHLD(16|32|64)rrCL")>;
+def: InstRW<[SKLWriteResGroup79], (instregex "SHRD(16|32|64)rrCL")>;
-def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
+def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> {
let Latency = 6;
let NumMicroOps = 4;
- let ResourceCycles = [2,1,1];
+ let ResourceCycles = [1,1,1,1];
}
-def: InstRW<[SKLWriteResGroup133], (instregex "HADDPDrm")>;
-def: InstRW<[SKLWriteResGroup133], (instregex "HADDPSrm")>;
-def: InstRW<[SKLWriteResGroup133], (instregex "HSUBPDrm")>;
-def: InstRW<[SKLWriteResGroup133], (instregex "HSUBPSrm")>;
-def: InstRW<[SKLWriteResGroup133], (instregex "VHADDPDYrm")>;
-def: InstRW<[SKLWriteResGroup133], (instregex "VHADDPDrm")>;
-def: InstRW<[SKLWriteResGroup133], (instregex "VHADDPSYrm")>;
-def: InstRW<[SKLWriteResGroup133], (instregex "VHADDPSrm")>;
-def: InstRW<[SKLWriteResGroup133], (instregex "VHSUBPDYrm")>;
-def: InstRW<[SKLWriteResGroup133], (instregex "VHSUBPDrm")>;
-def: InstRW<[SKLWriteResGroup133], (instregex "VHSUBPSYrm")>;
-def: InstRW<[SKLWriteResGroup133], (instregex "VHSUBPSrm")>;
+def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>;
-def SKLWriteResGroup134 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> {
+def SKLWriteResGroup81 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237,SKLPort015]> {
let Latency = 6;
let NumMicroOps = 4;
let ResourceCycles = [1,1,1,1];
}
-def: InstRW<[SKLWriteResGroup134], (instregex "SLDT(16|32|64)r")>;
+def: InstRW<[SKLWriteResGroup81], (instregex "VCVTPS2PHmr")>;
-def SKLWriteResGroup136 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
+def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
let Latency = 6;
- let NumMicroOps = 6;
- let ResourceCycles = [1,5];
+ let NumMicroOps = 4;
+ let ResourceCycles = [1,1,1,1];
}
-def: InstRW<[SKLWriteResGroup136], (instregex "STD")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "BTC(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "BTR(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "BTS(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "SAR(16|32|64)m1")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "SAR(16|32|64)mi")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "SAR8m1")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "SAR8mi")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "SHL(16|32|64)m1")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "SHL(16|32|64)mi")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "SHL8m1")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "SHL8mi")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "SHR(16|32|64)m1")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "SHR(16|32|64)mi")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "SHR8m1")>;
+def: InstRW<[SKLWriteResGroup82], (instregex "SHR8mi")>;
-def SKLWriteResGroup137 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
+def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
+ let Latency = 6;
+ let NumMicroOps = 4;
+ let ResourceCycles = [1,1,1,1];
+}
+def: InstRW<[SKLWriteResGroup83], (instregex "ADD(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "ADD(16|32|64)mr")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "ADD8mi")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "ADD8mr")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "AND(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "AND(16|32|64)mr")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "AND8mi")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "AND8mr")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "DEC(16|32|64)m")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "DEC8m")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "INC(16|32|64)m")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "INC8m")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "NEG(16|32|64)m")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "NEG8m")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "NOT(16|32|64)m")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "NOT8m")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "OR(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "OR(16|32|64)mr")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "OR8mi")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "OR8mr")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "PUSH(16|32|64)rmm")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "SUB(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "SUB(16|32|64)mr")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "SUB8mi")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "SUB8mr")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "XOR(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "XOR(16|32|64)mr")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "XOR8mi")>;
+def: InstRW<[SKLWriteResGroup83], (instregex "XOR8mr")>;
+
+def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
let Latency = 6;
let NumMicroOps = 6;
- let ResourceCycles = [1,1,1,2,1];
+ let ResourceCycles = [1,5];
+}
+def: InstRW<[SKLWriteResGroup84], (instregex "STD")>;
+
+def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> {
+ let Latency = 7;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup137], (instregex "SHLD(16|32|64)mrCL")>;
-def: InstRW<[SKLWriteResGroup137], (instregex "SHRD(16|32|64)mrCL")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "LD_F32m")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "LD_F64m")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "LD_F80m")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "VBROADCASTF128")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "VBROADCASTI128")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "VBROADCASTSDYrm")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "VBROADCASTSSYrm")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "VLDDQUYrm")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "VMOVAPDYrm")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "VMOVAPSYrm")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "VMOVDDUPYrm")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "VMOVDQAYrm")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "VMOVDQUYrm")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "VMOVNTDQAYrm")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "VMOVSHDUPYrm")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "VMOVSLDUPYrm")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "VMOVUPDYrm")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "VMOVUPSYrm")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "VPBROADCASTDYrm")>;
+def: InstRW<[SKLWriteResGroup85], (instregex "VPBROADCASTQYrm")>;
-def SKLWriteResGroup142 : SchedWriteRes<[SKLPort0,SKLPort5]> {
+def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0,SKLPort5]> {
let Latency = 7;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup142], (instregex "VCVTDQ2PDYrr")>;
+def: InstRW<[SKLWriteResGroup86], (instregex "VCVTDQ2PDYrr")>;
-def SKLWriteResGroup143 : SchedWriteRes<[SKLPort5,SKLPort015]> {
+def SKLWriteResGroup87 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 7;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup143], (instregex "VCVTPD2DQYrr")>;
-def: InstRW<[SKLWriteResGroup143], (instregex "VCVTPD2PSYrr")>;
-def: InstRW<[SKLWriteResGroup143], (instregex "VCVTPH2PSYrr")>;
-def: InstRW<[SKLWriteResGroup143], (instregex "VCVTPS2PDYrr")>;
-def: InstRW<[SKLWriteResGroup143], (instregex "VCVTPS2PHYrr")>;
-def: InstRW<[SKLWriteResGroup143], (instregex "VCVTTPD2DQYrr")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "COMISDrm")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "COMISSrm")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "UCOMISDrm")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "UCOMISSrm")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VCOMISDrm")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VCOMISSrm")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VUCOMISDrm")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "VUCOMISSrm")>;
+
+def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> {
+ let Latency = 7;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup88], (instregex "INSERTPSrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "PACKSSDWrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "PACKSSWBrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "PACKUSDWrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "PACKUSWBrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "PALIGNRrmi")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "PBLENDWrmi")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "PSHUFBrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "PSHUFDmi")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "PSHUFHWmi")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "PSHUFLWmi")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "PUNPCKHBWrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "PUNPCKHDQrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "PUNPCKHQDQrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "PUNPCKHWDrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "PUNPCKLBWrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "PUNPCKLDQrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "PUNPCKLQDQrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "PUNPCKLWDrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "SHUFPDrmi")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "SHUFPSrmi")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "UNPCKHPDrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "UNPCKHPSrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "UNPCKLPDrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "UNPCKLPSrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VINSERTPSrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPACKSSDWrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPACKSSWBrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPACKUSDWrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPACKUSWBrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPALIGNRrmi")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPBLENDWrmi")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPBROADCASTBrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPBROADCASTWrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPERMILPDmi")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPERMILPDrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPERMILPSmi")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPERMILPSrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPSHUFBrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPSHUFDmi")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPSHUFHWmi")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPSHUFLWmi")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPUNPCKHBWrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPUNPCKHDQrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPUNPCKHQDQrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPUNPCKHWDrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPUNPCKLBWrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPUNPCKLDQrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPUNPCKLQDQrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VPUNPCKLWDrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VSHUFPDrmi")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VSHUFPSrmi")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VUNPCKHPDrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VUNPCKHPSrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VUNPCKLPDrm")>;
+def: InstRW<[SKLWriteResGroup88], (instregex "VUNPCKLPSrm")>;
+
+def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort015]> {
+ let Latency = 7;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPD2DQYrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPD2PSYrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPH2PSYrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPS2PDYrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPS2PHYrr")>;
+def: InstRW<[SKLWriteResGroup89], (instregex "VCVTTPD2DQYrr")>;
+
+def SKLWriteResGroup90 : SchedWriteRes<[SKLPort01,SKLPort23]> {
+ let Latency = 7;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup90], (instregex "PABSBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PABSDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PABSWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PADDSBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PADDSWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PADDUSBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PADDUSWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PAVGBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PAVGWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PCMPEQBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PCMPEQDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PCMPEQQrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PCMPEQWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PCMPGTBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PCMPGTDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PCMPGTWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PMAXSBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PMAXSDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PMAXSWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PMAXUBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PMAXUDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PMAXUWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PMINSBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PMINSDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PMINSWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PMINUBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PMINUDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PMINUWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PSIGNBrm128")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PSIGNDrm128")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PSIGNWrm128")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PSLLDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PSLLQrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PSLLWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PSRADrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PSRAWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PSRLDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PSRLQrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PSRLWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PSUBSBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PSUBSWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PSUBUSBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "PSUBUSWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPABSBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPABSDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPABSWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPADDSBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPADDSWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPADDUSBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPADDUSWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPAVGBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPAVGWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPCMPEQBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPCMPEQDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPCMPEQQrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPCMPEQWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPCMPGTBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPCMPGTDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPCMPGTWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMAXSBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMAXSDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMAXSWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMAXUBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMAXUDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMAXUWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMINSBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMINSDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMINSWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMINUBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMINUDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPMINUWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSIGNBrm128")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSIGNDrm128")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSIGNWrm128")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSLLDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSLLQrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSLLVDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSLLVQrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSLLWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSRADrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSRAVDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSRAWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSRLDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSRLQrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSRLVDrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSRLVQrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSRLWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSUBSBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSUBSWrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSUBUSBrm")>;
+def: InstRW<[SKLWriteResGroup90], (instregex "VPSUBUSWrm")>;
+
+def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> {
+ let Latency = 7;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup91], (instregex "ANDNPDrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "ANDNPSrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "ANDPDrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "ANDPSrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "BLENDPDrmi")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "BLENDPSrmi")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "ORPDrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "ORPSrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "PADDBrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "PADDDrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "PADDQrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "PADDWrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "PANDNrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "PANDrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "PORrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "PSUBBrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "PSUBDrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "PSUBQrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "PSUBWrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "PXORrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VANDNPDrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VANDNPSrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VANDPDrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VANDPSrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VBLENDPDrmi")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VBLENDPSrmi")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VINSERTF128rm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VINSERTI128rm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VMASKMOVPDrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VMASKMOVPSrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VORPDrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VORPSrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VPADDBrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VPADDDrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VPADDQrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VPADDWrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VPANDNrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VPANDrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VPBLENDDrmi")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VPMASKMOVDrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VPMASKMOVQrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VPORrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VPSUBBrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VPSUBDrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VPSUBQrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VPSUBWrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VPXORrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VXORPDrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "VXORPSrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "XORPDrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "XORPSrm")>;
+
+def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> {
+ let Latency = 7;
+ let NumMicroOps = 3;
+ let ResourceCycles = [2,1];
+}
+def: InstRW<[SKLWriteResGroup92], (instregex "MMX_PACKSSDWirm")>;
+def: InstRW<[SKLWriteResGroup92], (instregex "MMX_PACKSSWBirm")>;
+def: InstRW<[SKLWriteResGroup92], (instregex "MMX_PACKUSWBirm")>;
-def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
+def SKLWriteResGroup93 : SchedWriteRes<[SKLPort23,SKLPort06]> {
+ let Latency = 7;
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,2];
+}
+def: InstRW<[SKLWriteResGroup93], (instregex "CMOVA(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup93], (instregex "CMOVBE(16|32|64)rm")>;
+
+def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
+ let Latency = 7;
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,2];
+}
+def: InstRW<[SKLWriteResGroup94], (instregex "LEAVE64")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "SCASB")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "SCASL")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "SCASQ")>;
+def: InstRW<[SKLWriteResGroup94], (instregex "SCASW")>;
+
+def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort015]> {
let Latency = 7;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup145], (instregex "MUL_FI16m")>;
-def: InstRW<[SKLWriteResGroup145], (instregex "MUL_FI32m")>;
-def: InstRW<[SKLWriteResGroup145], (instregex "VCVTDQ2PDYrm")>;
+def: InstRW<[SKLWriteResGroup95], (instregex "CVTTSS2SI64rr")>;
+def: InstRW<[SKLWriteResGroup95], (instregex "CVTTSS2SIrr")>;
+def: InstRW<[SKLWriteResGroup95], (instregex "VCVTTSS2SI64rr")>;
+def: InstRW<[SKLWriteResGroup95], (instregex "VCVTTSS2SIrr")>;
-def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort015]> {
+def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {
let Latency = 7;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup146], (instregex "CVTTSS2SI64rr")>;
-def: InstRW<[SKLWriteResGroup146], (instregex "CVTTSS2SIrr")>;
-def: InstRW<[SKLWriteResGroup146], (instregex "VCVTTSS2SI64rr")>;
-def: InstRW<[SKLWriteResGroup146], (instregex "VCVTTSS2SIrr")>;
+def: InstRW<[SKLWriteResGroup96], (instregex "FLDCW16m")>;
-def SKLWriteResGroup149 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort015]> {
+def SKLWriteResGroup97 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort0156]> {
let Latency = 7;
- let NumMicroOps = 4;
- let ResourceCycles = [1,1,1,1];
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup149], (instregex "CVTTSS2SI64rm")>;
+def: InstRW<[SKLWriteResGroup97], (instregex "LDMXCSR")>;
+def: InstRW<[SKLWriteResGroup97], (instregex "VLDMXCSR")>;
-def SKLWriteResGroup150 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237,SKLPort015]> {
+def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> {
let Latency = 7;
- let NumMicroOps = 4;
- let ResourceCycles = [1,1,1,1];
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup98], (instregex "LRETQ")>;
+def: InstRW<[SKLWriteResGroup98], (instregex "RETQ")>;
+
+def SKLWriteResGroup99 : SchedWriteRes<[SKLPort23,SKLPort06,SKLPort15]> {
+ let Latency = 7;
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup99], (instregex "BEXTR32rm")>;
+def: InstRW<[SKLWriteResGroup99], (instregex "BEXTR64rm")>;
+
+def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
+ let Latency = 7;
+ let NumMicroOps = 5;
+ let ResourceCycles = [1,1,1,2];
+}
+def: InstRW<[SKLWriteResGroup100], (instregex "ROL(16|32|64)m1")>;
+def: InstRW<[SKLWriteResGroup100], (instregex "ROL(16|32|64)mi")>;
+def: InstRW<[SKLWriteResGroup100], (instregex "ROL8m1")>;
+def: InstRW<[SKLWriteResGroup100], (instregex "ROL8mi")>;
+def: InstRW<[SKLWriteResGroup100], (instregex "ROR(16|32|64)m1")>;
+def: InstRW<[SKLWriteResGroup100], (instregex "ROR(16|32|64)mi")>;
+def: InstRW<[SKLWriteResGroup100], (instregex "ROR8m1")>;
+def: InstRW<[SKLWriteResGroup100], (instregex "ROR8mi")>;
+
+def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
+ let Latency = 7;
+ let NumMicroOps = 5;
+ let ResourceCycles = [1,1,1,2];
+}
+def: InstRW<[SKLWriteResGroup101], (instregex "XADD(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup101], (instregex "XADD8rm")>;
+
+def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
+ let Latency = 7;
+ let NumMicroOps = 5;
+ let ResourceCycles = [1,1,1,1,1];
}
-def: InstRW<[SKLWriteResGroup150], (instregex "VCVTPS2PHYmr")>;
+def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m")>;
+def: InstRW<[SKLWriteResGroup102], (instregex "FARCALL64")>;
-def SKLWriteResGroup151 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> {
+def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> {
let Latency = 7;
let NumMicroOps = 7;
let ResourceCycles = [1,3,1,2];
}
-def: InstRW<[SKLWriteResGroup151], (instregex "LOOP")>;
+def: InstRW<[SKLWriteResGroup103], (instregex "LOOP")>;
-def SKLWriteResGroup156 : SchedWriteRes<[SKLPort0]> {
+def SKLWriteResGroup104 : SchedWriteRes<[SKLPort0]> {
let Latency = 8;
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[SKLWriteResGroup156], (instregex "AESIMCrr")>;
-def: InstRW<[SKLWriteResGroup156], (instregex "VAESIMCrr")>;
+def: InstRW<[SKLWriteResGroup104], (instregex "AESIMCrr")>;
+def: InstRW<[SKLWriteResGroup104], (instregex "VAESIMCrr")>;
-def SKLWriteResGroup157 : SchedWriteRes<[SKLPort015]> {
+def SKLWriteResGroup105 : SchedWriteRes<[SKLPort015]> {
let Latency = 8;
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[SKLWriteResGroup157], (instregex "PMULLDrr")>;
-def: InstRW<[SKLWriteResGroup157], (instregex "ROUNDPDr")>;
-def: InstRW<[SKLWriteResGroup157], (instregex "ROUNDPSr")>;
-def: InstRW<[SKLWriteResGroup157], (instregex "ROUNDSDr")>;
-def: InstRW<[SKLWriteResGroup157], (instregex "ROUNDSSr")>;
-def: InstRW<[SKLWriteResGroup157], (instregex "VPMULLDYrr")>;
-def: InstRW<[SKLWriteResGroup157], (instregex "VPMULLDrr")>;
-def: InstRW<[SKLWriteResGroup157], (instregex "VROUNDPDr")>;
-def: InstRW<[SKLWriteResGroup157], (instregex "VROUNDPSr")>;
-def: InstRW<[SKLWriteResGroup157], (instregex "VROUNDSDr")>;
-def: InstRW<[SKLWriteResGroup157], (instregex "VROUNDSSr")>;
-def: InstRW<[SKLWriteResGroup157], (instregex "VROUNDYPDr")>;
-def: InstRW<[SKLWriteResGroup157], (instregex "VROUNDYPSr")>;
+def: InstRW<[SKLWriteResGroup105], (instregex "PMULLDrr")>;
+def: InstRW<[SKLWriteResGroup105], (instregex "ROUNDPDr")>;
+def: InstRW<[SKLWriteResGroup105], (instregex "ROUNDPSr")>;
+def: InstRW<[SKLWriteResGroup105], (instregex "ROUNDSDr")>;
+def: InstRW<[SKLWriteResGroup105], (instregex "ROUNDSSr")>;
+def: InstRW<[SKLWriteResGroup105], (instregex "VPMULLDYrr")>;
+def: InstRW<[SKLWriteResGroup105], (instregex "VPMULLDrr")>;
+def: InstRW<[SKLWriteResGroup105], (instregex "VROUNDPDr")>;
+def: InstRW<[SKLWriteResGroup105], (instregex "VROUNDPSr")>;
+def: InstRW<[SKLWriteResGroup105], (instregex "VROUNDSDr")>;
+def: InstRW<[SKLWriteResGroup105], (instregex "VROUNDSSr")>;
+def: InstRW<[SKLWriteResGroup105], (instregex "VROUNDYPDr")>;
+def: InstRW<[SKLWriteResGroup105], (instregex "VROUNDYPSr")>;
+
+def SKLWriteResGroup106 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+ let Latency = 8;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup106], (instregex "VTESTPDrm")>;
+def: InstRW<[SKLWriteResGroup106], (instregex "VTESTPSrm")>;
+
+def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> {
+ let Latency = 8;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup107], (instregex "BSF(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup107], (instregex "BSR(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup107], (instregex "IMUL64m")>;
+def: InstRW<[SKLWriteResGroup107], (instregex "IMUL(32|64)rm(i8?)")>;
+def: InstRW<[SKLWriteResGroup107], (instregex "IMUL8m")>;
+def: InstRW<[SKLWriteResGroup107], (instregex "LZCNT(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup107], (instregex "MUL(16|32|64)m")>;
+def: InstRW<[SKLWriteResGroup107], (instregex "MUL8m")>;
+def: InstRW<[SKLWriteResGroup107], (instregex "PDEP32rm")>;
+def: InstRW<[SKLWriteResGroup107], (instregex "PDEP64rm")>;
+def: InstRW<[SKLWriteResGroup107], (instregex "PEXT32rm")>;
+def: InstRW<[SKLWriteResGroup107], (instregex "PEXT64rm")>;
+def: InstRW<[SKLWriteResGroup107], (instregex "POPCNT(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup107], (instregex "TZCNT(16|32|64)rm")>;
+
+def SKLWriteResGroup107_16 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {
+ let Latency = 3;
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup107_16], (instregex "IMUL16rm(i8?)")>;
+
+def SKLWriteResGroup107_16_2 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {
+ let Latency = 3;
+ let NumMicroOps = 5;
+}
+def: InstRW<[SKLWriteResGroup107_16_2], (instregex "IMUL16m")>;
+def: InstRW<[SKLWriteResGroup107_16_2], (instregex "MUL16m")>;
+
+def SKLWriteResGroup107_32 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {
+ let Latency = 3;
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup107_32], (instregex "IMUL32m")>;
+def: InstRW<[SKLWriteResGroup107_32], (instregex "MUL32m")>;
+
+def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> {
+ let Latency = 8;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup108], (instregex "FCOM32m")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "FCOM64m")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "FCOMP32m")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "FCOMP64m")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "MMX_PSADBWirm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPACKSSDWYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPACKSSWBYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPACKUSDWYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPACKUSWBYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPALIGNRYrmi")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPBLENDWYrmi")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPBROADCASTBYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPBROADCASTWYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPERMILPDYmi")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPERMILPDYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPERMILPSYmi")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPERMILPSYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPMOVSXBDYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPMOVSXBQYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPMOVSXWQYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPSHUFBYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPSHUFDYmi")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPSHUFHWYmi")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPSHUFLWYmi")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPUNPCKHBWYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPUNPCKHDQYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPUNPCKHQDQYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPUNPCKHWDYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPUNPCKLBWYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPUNPCKLDQYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPUNPCKLQDQYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VPUNPCKLWDYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VSHUFPDYrmi")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VSHUFPSYrmi")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VUNPCKHPDYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VUNPCKHPSYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VUNPCKLPDYrm")>;
+def: InstRW<[SKLWriteResGroup108], (instregex "VUNPCKLPSYrm")>;
+
+def SKLWriteResGroup109 : SchedWriteRes<[SKLPort01,SKLPort23]> {
+ let Latency = 8;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup109], (instregex "VPABSBYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPABSDYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPABSWYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPADDSBYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPADDSWYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPADDUSBYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPADDUSWYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPAVGBYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPAVGWYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPCMPEQBYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPCMPEQDYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPCMPEQQYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPCMPEQWYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPCMPGTBYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPCMPGTDYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPCMPGTWYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMAXSBYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMAXSDYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMAXSWYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMAXUBYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMAXUDYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMAXUWYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMINSBYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMINSDYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMINSWYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMINUBYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMINUDYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPMINUWYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSIGNBYrm256")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSIGNDYrm256")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSIGNWYrm256")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSLLDYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSLLQYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSLLVDYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSLLVQYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSLLWYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSRADYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSRAVDYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSRAWYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSRLDYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSRLQYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSRLVDYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSRLVQYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSRLWYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSUBSBYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSUBSWYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSUBUSBYrm")>;
+def: InstRW<[SKLWriteResGroup109], (instregex "VPSUBUSWYrm")>;
+
+def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> {
+ let Latency = 8;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup110], (instregex "VANDNPDYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VANDNPSYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VANDPDYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VANDPSYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VBLENDPDYrmi")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VBLENDPSYrmi")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VMASKMOVPDYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VMASKMOVPSYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VORPDYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VORPSYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VPADDBYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VPADDDYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VPADDQYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VPADDWYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VPANDNYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VPANDYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VPBLENDDYrmi")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VPMASKMOVDYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VPMASKMOVQYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VPORYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VPSUBBYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VPSUBDYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VPSUBQYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VPSUBWYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VPXORYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VXORPDYrm")>;
+def: InstRW<[SKLWriteResGroup110], (instregex "VXORPSYrm")>;
+
+def SKLWriteResGroup111 : SchedWriteRes<[SKLPort23,SKLPort015]> {
+ let Latency = 8;
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,2];
+}
+def: InstRW<[SKLWriteResGroup111], (instregex "BLENDVPDrm0")>;
+def: InstRW<[SKLWriteResGroup111], (instregex "BLENDVPSrm0")>;
+def: InstRW<[SKLWriteResGroup111], (instregex "PBLENDVBrm0")>;
+def: InstRW<[SKLWriteResGroup111], (instregex "VBLENDVPDrm")>;
+def: InstRW<[SKLWriteResGroup111], (instregex "VBLENDVPSrm")>;
+def: InstRW<[SKLWriteResGroup111], (instregex "VPBLENDVBYrm")>;
+def: InstRW<[SKLWriteResGroup111], (instregex "VPBLENDVBrm")>;
+
+def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
+ let Latency = 8;
+ let NumMicroOps = 4;
+ let ResourceCycles = [1,2,1];
+}
+def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PHADDSWrm64")>;
+def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PHSUBSWrm64")>;
+
+def SKLWriteResGroup113 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort05]> {
+ let Latency = 8;
+ let NumMicroOps = 4;
+ let ResourceCycles = [2,1,1];
+}
+def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHADDWrm64")>;
+def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHADDrm64")>;
+def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHSUBDrm64")>;
+def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHSUBWrm64")>;
+
+def SKLWriteResGroup114 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237,SKLPort015]> {
+ let Latency = 8;
+ let NumMicroOps = 4;
+ let ResourceCycles = [1,1,1,1];
+}
+def: InstRW<[SKLWriteResGroup114], (instregex "VCVTPS2PHYmr")>;
+
+def SKLWriteResGroup115 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06]> {
+ let Latency = 8;
+ let NumMicroOps = 5;
+ let ResourceCycles = [1,1,3];
+}
+def: InstRW<[SKLWriteResGroup115], (instregex "ROR(16|32|64)mCL")>;
+def: InstRW<[SKLWriteResGroup115], (instregex "ROR8mCL")>;
+
+def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
+ let Latency = 8;
+ let NumMicroOps = 5;
+ let ResourceCycles = [1,1,1,2];
+}
+def: InstRW<[SKLWriteResGroup116], (instregex "RCL(16|32|64)m1")>;
+def: InstRW<[SKLWriteResGroup116], (instregex "RCL(16|32|64)mi")>;
+def: InstRW<[SKLWriteResGroup116], (instregex "RCL8m1")>;
+def: InstRW<[SKLWriteResGroup116], (instregex "RCL8mi")>;
+def: InstRW<[SKLWriteResGroup116], (instregex "RCR(16|32|64)m1")>;
+def: InstRW<[SKLWriteResGroup116], (instregex "RCR(16|32|64)mi")>;
+def: InstRW<[SKLWriteResGroup116], (instregex "RCR8m1")>;
+def: InstRW<[SKLWriteResGroup116], (instregex "RCR8mi")>;
+
+def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
+ let Latency = 8;
+ let NumMicroOps = 6;
+ let ResourceCycles = [1,1,1,3];
+}
+def: InstRW<[SKLWriteResGroup117], (instregex "ROL(16|32|64)mCL")>;
+def: InstRW<[SKLWriteResGroup117], (instregex "ROL8mCL")>;
+def: InstRW<[SKLWriteResGroup117], (instregex "SAR(16|32|64)mCL")>;
+def: InstRW<[SKLWriteResGroup117], (instregex "SAR8mCL")>;
+def: InstRW<[SKLWriteResGroup117], (instregex "SHL(16|32|64)mCL")>;
+def: InstRW<[SKLWriteResGroup117], (instregex "SHL8mCL")>;
+def: InstRW<[SKLWriteResGroup117], (instregex "SHR(16|32|64)mCL")>;
+def: InstRW<[SKLWriteResGroup117], (instregex "SHR8mCL")>;
+
+def SKLWriteResGroup118 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
+ let Latency = 8;
+ let NumMicroOps = 6;
+ let ResourceCycles = [1,1,1,3];
+}
+def: InstRW<[SKLWriteResGroup118], (instregex "ADC(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup118], (instregex "ADC8mi")>;
+
+def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
+ let Latency = 8;
+ let NumMicroOps = 6;
+ let ResourceCycles = [1,1,1,2,1];
+}
+def: InstRW<[SKLWriteResGroup119], (instregex "ADC(16|32|64)mr")>;
+def: InstRW<[SKLWriteResGroup119], (instregex "ADC8mr")>;
+def: InstRW<[SKLWriteResGroup119], (instregex "CMPXCHG(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup119], (instregex "CMPXCHG8rm")>;
+def: InstRW<[SKLWriteResGroup119], (instregex "SBB(16|32|64)mi8")>;
+def: InstRW<[SKLWriteResGroup119], (instregex "SBB(16|32|64)mr")>;
+def: InstRW<[SKLWriteResGroup119], (instregex "SBB8mi")>;
+def: InstRW<[SKLWriteResGroup119], (instregex "SBB8mr")>;
+
+def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+ let Latency = 9;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup120], (instregex "MMX_CVTPI2PSirm")>;
+def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMADDUBSWrm64")>;
+def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMADDWDirm")>;
+def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMULHRSWrm64")>;
+def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMULHUWirm")>;
+def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMULHWirm")>;
+def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMULLWirm")>;
+def: InstRW<[SKLWriteResGroup120], (instregex "MMX_PMULUDQirm")>;
+def: InstRW<[SKLWriteResGroup120], (instregex "RCPSSm")>;
+def: InstRW<[SKLWriteResGroup120], (instregex "RSQRTSSm")>;
+def: InstRW<[SKLWriteResGroup120], (instregex "VRCPSSm")>;
+def: InstRW<[SKLWriteResGroup120], (instregex "VRSQRTSSm")>;
+def: InstRW<[SKLWriteResGroup120], (instregex "VTESTPDYrm")>;
+def: InstRW<[SKLWriteResGroup120], (instregex "VTESTPSYrm")>;
+
+def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> {
+ let Latency = 9;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup121], (instregex "PCMPGTQrm")>;
+def: InstRW<[SKLWriteResGroup121], (instregex "PSADBWrm")>;
+def: InstRW<[SKLWriteResGroup121], (instregex "VPCMPGTQrm")>;
+def: InstRW<[SKLWriteResGroup121], (instregex "VPMOVSXBWYrm")>;
+def: InstRW<[SKLWriteResGroup121], (instregex "VPMOVSXDQYrm")>;
+def: InstRW<[SKLWriteResGroup121], (instregex "VPMOVSXWDYrm")>;
+def: InstRW<[SKLWriteResGroup121], (instregex "VPMOVZXWDYrm")>;
+def: InstRW<[SKLWriteResGroup121], (instregex "VPSADBWrm")>;
+
+def SKLWriteResGroup122 : SchedWriteRes<[SKLPort01,SKLPort23]> {
+ let Latency = 9;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup122], (instregex "ADDSDrm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "ADDSSrm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "MULSDrm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "MULSSrm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "SUBSDrm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "SUBSSrm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VADDSDrm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VADDSSrm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMADD132SDm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMADD132SSm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMADD213SDm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMADD213SSm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMADD231SDm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMADD231SSm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMSUB132SDm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMSUB132SSm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMSUB213SDm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMSUB213SSm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMSUB231SDm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFMSUB231SSm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMADD132SDm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMADD132SSm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMADD213SDm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMADD213SSm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMADD231SDm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMADD231SSm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMSUB132SDm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMSUB132SSm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMSUB213SDm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMSUB213SSm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMSUB231SDm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VFNMSUB231SSm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VMULSDrm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VMULSSrm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VSUBSDrm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "VSUBSSrm")>;
+
+def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort015]> {
+ let Latency = 9;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup123], (instregex "CMPSSrm")>;
+def: InstRW<[SKLWriteResGroup123], (instregex "CVTPS2PDrm")>;
+def: InstRW<[SKLWriteResGroup123], (instregex "MAXSDrm")>;
+def: InstRW<[SKLWriteResGroup123], (instregex "MAXSSrm")>;
+def: InstRW<[SKLWriteResGroup123], (instregex "MINSDrm")>;
+def: InstRW<[SKLWriteResGroup123], (instregex "MINSSrm")>;
+def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVTPS2PIirm")>;
+def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVTTPS2PIirm")>;
+def: InstRW<[SKLWriteResGroup123], (instregex "VCMPSDrm")>;
+def: InstRW<[SKLWriteResGroup123], (instregex "VCMPSSrm")>;
+def: InstRW<[SKLWriteResGroup123], (instregex "VCVTPH2PSrm")>;
+def: InstRW<[SKLWriteResGroup123], (instregex "VCVTPS2PDrm")>;
+def: InstRW<[SKLWriteResGroup123], (instregex "VMAXSDrm")>;
+def: InstRW<[SKLWriteResGroup123], (instregex "VMAXSSrm")>;
+def: InstRW<[SKLWriteResGroup123], (instregex "VMINSDrm")>;
+def: InstRW<[SKLWriteResGroup123], (instregex "VMINSSrm")>;
+
+def SKLWriteResGroup124 : SchedWriteRes<[SKLPort5,SKLPort015]> {
+ let Latency = 9;
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,2];
+}
+def: InstRW<[SKLWriteResGroup124], (instregex "DPPDrri")>;
+def: InstRW<[SKLWriteResGroup124], (instregex "VDPPDrri")>;
+
+def SKLWriteResGroup125 : SchedWriteRes<[SKLPort23,SKLPort015]> {
+ let Latency = 9;
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,2];
+}
+def: InstRW<[SKLWriteResGroup125], (instregex "VBLENDVPDYrm")>;
+def: InstRW<[SKLWriteResGroup125], (instregex "VBLENDVPSYrm")>;
+
+def SKLWriteResGroup126 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
+ let Latency = 9;
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup126], (instregex "PTESTrm")>;
+def: InstRW<[SKLWriteResGroup126], (instregex "VPTESTrm")>;
+
+def SKLWriteResGroup127 : SchedWriteRes<[SKLPort1,SKLPort5,SKLPort23]> {
+ let Latency = 9;
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup127], (instregex "MULX64rm")>;
+
+def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
+ let Latency = 9;
+ let NumMicroOps = 4;
+ let ResourceCycles = [2,1,1];
+}
+def: InstRW<[SKLWriteResGroup128], (instregex "PHADDSWrm128")>;
+def: InstRW<[SKLWriteResGroup128], (instregex "PHSUBSWrm128")>;
+def: InstRW<[SKLWriteResGroup128], (instregex "VPHADDSWrm128")>;
+def: InstRW<[SKLWriteResGroup128], (instregex "VPHSUBSWrm128")>;
+
+def SKLWriteResGroup129 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
+ let Latency = 9;
+ let NumMicroOps = 4;
+ let ResourceCycles = [2,1,1];
+}
+def: InstRW<[SKLWriteResGroup129], (instregex "PHADDDrm")>;
+def: InstRW<[SKLWriteResGroup129], (instregex "PHADDWrm")>;
+def: InstRW<[SKLWriteResGroup129], (instregex "PHSUBDrm")>;
+def: InstRW<[SKLWriteResGroup129], (instregex "PHSUBWrm")>;
+def: InstRW<[SKLWriteResGroup129], (instregex "VPHADDDrm")>;
+def: InstRW<[SKLWriteResGroup129], (instregex "VPHADDWrm")>;
+def: InstRW<[SKLWriteResGroup129], (instregex "VPHSUBDrm")>;
+def: InstRW<[SKLWriteResGroup129], (instregex "VPHSUBWrm")>;
+
+def SKLWriteResGroup130 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort0156]> {
+ let Latency = 9;
+ let NumMicroOps = 4;
+ let ResourceCycles = [1,1,1,1];
+}
+def: InstRW<[SKLWriteResGroup130], (instregex "SHLD(16|32|64)mri8")>;
+def: InstRW<[SKLWriteResGroup130], (instregex "SHRD(16|32|64)mri8")>;
+
+def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
+ let Latency = 9;
+ let NumMicroOps = 5;
+ let ResourceCycles = [1,2,1,1];
+}
+def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup131], (instregex "LSL(16|32|64)rm")>;
+
+def SKLWriteResGroup132 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+ let Latency = 10;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup132], (instregex "AESDECLASTrm")>;
+def: InstRW<[SKLWriteResGroup132], (instregex "AESDECrm")>;
+def: InstRW<[SKLWriteResGroup132], (instregex "AESENCLASTrm")>;
+def: InstRW<[SKLWriteResGroup132], (instregex "AESENCrm")>;
+def: InstRW<[SKLWriteResGroup132], (instregex "RCPPSm")>;
+def: InstRW<[SKLWriteResGroup132], (instregex "RSQRTPSm")>;
+def: InstRW<[SKLWriteResGroup132], (instregex "VAESDECLASTrm")>;
+def: InstRW<[SKLWriteResGroup132], (instregex "VAESDECrm")>;
+def: InstRW<[SKLWriteResGroup132], (instregex "VAESENCLASTrm")>;
+def: InstRW<[SKLWriteResGroup132], (instregex "VAESENCrm")>;
+def: InstRW<[SKLWriteResGroup132], (instregex "VRCPPSm")>;
+def: InstRW<[SKLWriteResGroup132], (instregex "VRSQRTPSm")>;
+
+def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> {
+ let Latency = 10;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup133], (instregex "ADD_F32m")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "ADD_F64m")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "ILD_F16m")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "ILD_F32m")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "ILD_F64m")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "SUBR_F32m")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "SUBR_F64m")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "SUB_F32m")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "SUB_F64m")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "VPCMPGTQYrm")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "VPERM2F128rm")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "VPERM2I128rm")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "VPERMDYrm")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "VPERMPDYmi")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "VPERMPSYrm")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "VPERMQYmi")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "VPMOVZXBDYrm")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "VPMOVZXBQYrm")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "VPMOVZXBWYrm")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "VPMOVZXDQYrm")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "VPMOVZXWQYrm")>;
+def: InstRW<[SKLWriteResGroup133], (instregex "VPSADBWYrm")>;
+
+def SKLWriteResGroup134 : SchedWriteRes<[SKLPort01,SKLPort23]> {
+ let Latency = 10;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup134], (instregex "ADDPDrm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "ADDPSrm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "ADDSUBPDrm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "ADDSUBPSrm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "MULPDrm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "MULPSrm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "SUBPDrm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "SUBPSrm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VADDPDrm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VADDPSrm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VADDSUBPDrm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VADDSUBPSrm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADD132PDm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADD132PSm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADD213PDm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADD213PSm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADD231PDm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADD231PSm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADDSUB132PDm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADDSUB132PSm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADDSUB213PDm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADDSUB213PSm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADDSUB231PDm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMADDSUB231PSm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUB132PDm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUB132PSm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUB213PDm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUB213PSm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUB231PDm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUB231PSm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUBADD132PDm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUBADD132PSm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUBADD213PDm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUBADD213PSm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUBADD231PDm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFMSUBADD231PSm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMADD132PDm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMADD132PSm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMADD213PDm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMADD213PSm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMADD231PDm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMADD231PSm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMSUB132PDm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMSUB132PSm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMSUB213PDm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMSUB213PSm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMSUB231PDm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VFNMSUB231PSm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VMULPDrm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VMULPSrm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VSUBPDrm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "VSUBPSrm")>;
+
+def SKLWriteResGroup135 : SchedWriteRes<[SKLPort23,SKLPort015]> {
+ let Latency = 10;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup135], (instregex "CMPPDrmi")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "CMPPSrmi")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "CVTDQ2PSrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "CVTPS2DQrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "CVTSS2SDrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "CVTTPS2DQrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "MAXPDrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "MAXPSrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "MINPDrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "MINPSrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "PHMINPOSUWrm128")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "PMADDUBSWrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "PMADDWDrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "PMULDQrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "PMULHRSWrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "PMULHUWrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "PMULHWrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "PMULLWrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "PMULUDQrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "VCMPPDrmi")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "VCMPPSrmi")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "VCVTDQ2PSrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "VCVTPH2PSYrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "VCVTPS2DQrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "VCVTSS2SDrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "VCVTTPS2DQrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "VMAXPDrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "VMAXPSrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "VMINPDrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "VMINPSrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "VPHMINPOSUWrm128")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "VPMADDUBSWrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "VPMADDWDrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "VPMULDQrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "VPMULHRSWrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "VPMULHUWrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "VPMULHWrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "VPMULLWrm")>;
+def: InstRW<[SKLWriteResGroup135], (instregex "VPMULUDQrm")>;
+
+def SKLWriteResGroup136 : SchedWriteRes<[SKLPort0]> {
+ let Latency = 10;
+ let NumMicroOps = 3;
+ let ResourceCycles = [3];
+}
+def: InstRW<[SKLWriteResGroup136], (instregex "PCMPISTRIrr")>;
+def: InstRW<[SKLWriteResGroup136], (instregex "PCMPISTRM128rr")>;
+def: InstRW<[SKLWriteResGroup136], (instregex "VPCMPISTRIrr")>;
+def: InstRW<[SKLWriteResGroup136], (instregex "VPCMPISTRM128rr")>;
-def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort23]> {
- let Latency = 8;
+def SKLWriteResGroup137 : SchedWriteRes<[SKLPort5,SKLPort23]> {
+ let Latency = 10;
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKLWriteResGroup160], (instregex "AESIMCrm")>;
-def: InstRW<[SKLWriteResGroup160], (instregex "VAESIMCrm")>;
+def: InstRW<[SKLWriteResGroup137], (instregex "MPSADBWrmi")>;
+def: InstRW<[SKLWriteResGroup137], (instregex "VMPSADBWrmi")>;
-def SKLWriteResGroup161 : SchedWriteRes<[SKLPort23,SKLPort015]> {
- let Latency = 8;
+def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
+ let Latency = 10;
let NumMicroOps = 3;
- let ResourceCycles = [1,2];
+ let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup161], (instregex "PMULLDrm")>;
-def: InstRW<[SKLWriteResGroup161], (instregex "ROUNDPDm")>;
-def: InstRW<[SKLWriteResGroup161], (instregex "ROUNDPSm")>;
-def: InstRW<[SKLWriteResGroup161], (instregex "ROUNDSDm")>;
-def: InstRW<[SKLWriteResGroup161], (instregex "ROUNDSSm")>;
-def: InstRW<[SKLWriteResGroup161], (instregex "VPMULLDYrm")>;
-def: InstRW<[SKLWriteResGroup161], (instregex "VPMULLDrm")>;
-def: InstRW<[SKLWriteResGroup161], (instregex "VROUNDPDm")>;
-def: InstRW<[SKLWriteResGroup161], (instregex "VROUNDPSm")>;
-def: InstRW<[SKLWriteResGroup161], (instregex "VROUNDSDm")>;
-def: InstRW<[SKLWriteResGroup161], (instregex "VROUNDSSm")>;
-def: InstRW<[SKLWriteResGroup161], (instregex "VROUNDYPDm")>;
-def: InstRW<[SKLWriteResGroup161], (instregex "VROUNDYPSm")>;
+def: InstRW<[SKLWriteResGroup138], (instregex "MMX_CVTPI2PDirm")>;
+def: InstRW<[SKLWriteResGroup138], (instregex "VPTESTYrm")>;
-def SKLWriteResGroup165 : SchedWriteRes<[SKLPort5,SKLPort015]> {
- let Latency = 9;
+def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
+ let Latency = 10;
let NumMicroOps = 3;
- let ResourceCycles = [1,2];
+ let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup165], (instregex "DPPDrri")>;
-def: InstRW<[SKLWriteResGroup165], (instregex "VDPPDrri")>;
+def: InstRW<[SKLWriteResGroup139], (instregex "CVTSD2SSrm")>;
+def: InstRW<[SKLWriteResGroup139], (instregex "VCVTSD2SSrm")>;
-def SKLWriteResGroup167 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
- let Latency = 9;
+def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
+ let Latency = 10;
let NumMicroOps = 4;
- let ResourceCycles = [1,1,2];
+ let ResourceCycles = [2,1,1];
}
-def: InstRW<[SKLWriteResGroup167], (instregex "DPPDrmi")>;
-def: InstRW<[SKLWriteResGroup167], (instregex "VDPPDrmi")>;
+def: InstRW<[SKLWriteResGroup140], (instregex "VPHADDSWrm256")>;
+def: InstRW<[SKLWriteResGroup140], (instregex "VPHSUBSWrm256")>;
-def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0]> {
+def SKLWriteResGroup141 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
let Latency = 10;
- let NumMicroOps = 3;
- let ResourceCycles = [3];
+ let NumMicroOps = 4;
+ let ResourceCycles = [2,1,1];
}
-def: InstRW<[SKLWriteResGroup169], (instregex "PCMPISTRIrr")>;
-def: InstRW<[SKLWriteResGroup169], (instregex "PCMPISTRM128rr")>;
-def: InstRW<[SKLWriteResGroup169], (instregex "VPCMPISTRIrr")>;
-def: InstRW<[SKLWriteResGroup169], (instregex "VPCMPISTRM128rr")>;
+def: InstRW<[SKLWriteResGroup141], (instregex "VPHADDDYrm")>;
+def: InstRW<[SKLWriteResGroup141], (instregex "VPHADDWYrm")>;
+def: InstRW<[SKLWriteResGroup141], (instregex "VPHSUBDYrm")>;
+def: InstRW<[SKLWriteResGroup141], (instregex "VPHSUBWYrm")>;
-def SKLWriteResGroup170 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+def SKLWriteResGroup142 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort06,SKLPort0156]> {
let Latency = 10;
let NumMicroOps = 4;
- let ResourceCycles = [3,1];
+ let ResourceCycles = [1,1,1,1];
}
-def: InstRW<[SKLWriteResGroup170], (instregex "PCMPISTRIrm")>;
-def: InstRW<[SKLWriteResGroup170], (instregex "PCMPISTRM128rm")>;
-def: InstRW<[SKLWriteResGroup170], (instregex "VPCMPISTRIrm")>;
-def: InstRW<[SKLWriteResGroup170], (instregex "VPCMPISTRM128rm")>;
+def: InstRW<[SKLWriteResGroup142], (instregex "MULX32rm")>;
-def SKLWriteResGroup171 : SchedWriteRes<[SKLPort05,SKLPort0156]> {
+def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
let Latency = 10;
- let NumMicroOps = 10;
- let ResourceCycles = [9,1];
+ let NumMicroOps = 8;
+ let ResourceCycles = [1,1,1,1,1,3];
}
-def: InstRW<[SKLWriteResGroup171], (instregex "MMX_EMMS")>;
+def: InstRW<[SKLWriteResGroup143], (instregex "ADD8mi")>;
+def: InstRW<[SKLWriteResGroup143], (instregex "AND8mi")>;
+def: InstRW<[SKLWriteResGroup143], (instregex "OR8mi")>;
+def: InstRW<[SKLWriteResGroup143], (instregex "SUB8mi")>;
+def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup143], (instregex "XCHG8rm")>;
+def: InstRW<[SKLWriteResGroup143], (instregex "XOR8mi")>;
-def SKLWriteResGroup172 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
+def SKLWriteResGroup144 : SchedWriteRes<[SKLPort05,SKLPort0156]> {
let Latency = 10;
let NumMicroOps = 10;
- let ResourceCycles = [1,1,1,5,1,1];
+ let ResourceCycles = [9,1];
}
-def: InstRW<[SKLWriteResGroup172], (instregex "RCL(16|32|64)mCL")>;
-def: InstRW<[SKLWriteResGroup172], (instregex "RCL8mCL")>;
+def: InstRW<[SKLWriteResGroup144], (instregex "MMX_EMMS")>;
-def SKLWriteResGroup173 : SchedWriteRes<[SKLPort0]> {
+def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0]> {
let Latency = 11;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup173], (instregex "DIVPSrr")>;
-def: InstRW<[SKLWriteResGroup173], (instregex "DIVSSrr")>;
-def: InstRW<[SKLWriteResGroup173], (instregex "VDIVPSYrr")>;
-def: InstRW<[SKLWriteResGroup173], (instregex "VDIVPSrr")>;
-def: InstRW<[SKLWriteResGroup173], (instregex "VDIVSSrr")>;
+def: InstRW<[SKLWriteResGroup145], (instregex "DIVPSrr")>;
+def: InstRW<[SKLWriteResGroup145], (instregex "DIVSSrr")>;
+def: InstRW<[SKLWriteResGroup145], (instregex "VDIVPSYrr")>;
+def: InstRW<[SKLWriteResGroup145], (instregex "VDIVPSrr")>;
+def: InstRW<[SKLWriteResGroup145], (instregex "VDIVSSrr")>;
+
+def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+ let Latency = 11;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F32m")>;
+def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F64m")>;
+def: InstRW<[SKLWriteResGroup146], (instregex "VRCPPSYm")>;
+def: InstRW<[SKLWriteResGroup146], (instregex "VRSQRTPSYm")>;
+
+def SKLWriteResGroup147 : SchedWriteRes<[SKLPort01,SKLPort23]> {
+ let Latency = 11;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup147], (instregex "VADDPDYrm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VADDPSYrm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VADDSUBPDYrm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VADDSUBPSYrm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADD132PDYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADD132PSYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADD213PDYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADD213PSYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADD231PDYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADD231PSYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADDSUB132PDYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADDSUB132PSYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADDSUB213PDYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADDSUB213PSYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADDSUB231PDYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMADDSUB231PSYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUB132PDYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUB132PSYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUB213PDYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUB213PSYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUB231PDYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUB231PSYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUBADD132PDYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUBADD132PSYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUBADD213PDYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUBADD213PSYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUBADD231PDYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFMSUBADD231PSYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMADD132PDYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMADD132PSYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMADD213PDYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMADD213PSYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMADD231PDYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMADD231PSYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMSUB132PDYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMSUB132PSYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMSUB213PDYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMSUB213PSYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMSUB231PDYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VFNMSUB231PSYm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VMULPDYrm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VMULPSYrm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VSUBPDYrm")>;
+def: InstRW<[SKLWriteResGroup147], (instregex "VSUBPSYrm")>;
-def SKLWriteResGroup174 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+def SKLWriteResGroup148 : SchedWriteRes<[SKLPort23,SKLPort015]> {
let Latency = 11;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup174], (instregex "DIVPSrm")>;
-def: InstRW<[SKLWriteResGroup174], (instregex "DIVSSrm")>;
-def: InstRW<[SKLWriteResGroup174], (instregex "VDIVPSYrm")>;
-def: InstRW<[SKLWriteResGroup174], (instregex "VDIVPSrm")>;
-def: InstRW<[SKLWriteResGroup174], (instregex "VDIVSSrm")>;
+def: InstRW<[SKLWriteResGroup148], (instregex "VCMPPDYrmi")>;
+def: InstRW<[SKLWriteResGroup148], (instregex "VCMPPSYrmi")>;
+def: InstRW<[SKLWriteResGroup148], (instregex "VCVTDQ2PSYrm")>;
+def: InstRW<[SKLWriteResGroup148], (instregex "VCVTPS2DQYrm")>;
+def: InstRW<[SKLWriteResGroup148], (instregex "VCVTPS2PDYrm")>;
+def: InstRW<[SKLWriteResGroup148], (instregex "VCVTTPS2DQYrm")>;
+def: InstRW<[SKLWriteResGroup148], (instregex "VMAXPDYrm")>;
+def: InstRW<[SKLWriteResGroup148], (instregex "VMAXPSYrm")>;
+def: InstRW<[SKLWriteResGroup148], (instregex "VMINPDYrm")>;
+def: InstRW<[SKLWriteResGroup148], (instregex "VMINPSYrm")>;
+def: InstRW<[SKLWriteResGroup148], (instregex "VPMADDUBSWYrm")>;
+def: InstRW<[SKLWriteResGroup148], (instregex "VPMADDWDYrm")>;
+def: InstRW<[SKLWriteResGroup148], (instregex "VPMULDQYrm")>;
+def: InstRW<[SKLWriteResGroup148], (instregex "VPMULHRSWYrm")>;
+def: InstRW<[SKLWriteResGroup148], (instregex "VPMULHUWYrm")>;
+def: InstRW<[SKLWriteResGroup148], (instregex "VPMULHWYrm")>;
+def: InstRW<[SKLWriteResGroup148], (instregex "VPMULLWYrm")>;
+def: InstRW<[SKLWriteResGroup148], (instregex "VPMULUDQYrm")>;
+
+def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> {
+ let Latency = 11;
+ let NumMicroOps = 3;
+ let ResourceCycles = [2,1];
+}
+def: InstRW<[SKLWriteResGroup149], (instregex "FICOM16m")>;
+def: InstRW<[SKLWriteResGroup149], (instregex "FICOM32m")>;
+def: InstRW<[SKLWriteResGroup149], (instregex "FICOMP16m")>;
+def: InstRW<[SKLWriteResGroup149], (instregex "FICOMP32m")>;
+def: InstRW<[SKLWriteResGroup149], (instregex "VMPSADBWYrmi")>;
+
+def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
+ let Latency = 11;
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup150], (instregex "CVTDQ2PDrm")>;
+def: InstRW<[SKLWriteResGroup150], (instregex "VCVTDQ2PDrm")>;
-def SKLWriteResGroup175 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
+def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort015]> {
+ let Latency = 11;
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup151], (instregex "CVTSD2SI64rm")>;
+def: InstRW<[SKLWriteResGroup151], (instregex "CVTSD2SIrm")>;
+def: InstRW<[SKLWriteResGroup151], (instregex "CVTSS2SI64rm")>;
+def: InstRW<[SKLWriteResGroup151], (instregex "CVTSS2SIrm")>;
+def: InstRW<[SKLWriteResGroup151], (instregex "CVTTSD2SI64rm")>;
+def: InstRW<[SKLWriteResGroup151], (instregex "CVTTSD2SIrm")>;
+def: InstRW<[SKLWriteResGroup151], (instregex "CVTTSS2SIrm")>;
+def: InstRW<[SKLWriteResGroup151], (instregex "VCVTSD2SI64rm")>;
+def: InstRW<[SKLWriteResGroup151], (instregex "VCVTSD2SIrm")>;
+def: InstRW<[SKLWriteResGroup151], (instregex "VCVTSS2SI64rm")>;
+def: InstRW<[SKLWriteResGroup151], (instregex "VCVTSS2SIrm")>;
+def: InstRW<[SKLWriteResGroup151], (instregex "VCVTTSD2SI64rm")>;
+def: InstRW<[SKLWriteResGroup151], (instregex "VCVTTSD2SIrm")>;
+def: InstRW<[SKLWriteResGroup151], (instregex "VCVTTSS2SI64rm")>;
+def: InstRW<[SKLWriteResGroup151], (instregex "VCVTTSS2SIrm")>;
+
+def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
+ let Latency = 11;
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup152], (instregex "CVTPD2DQrm")>;
+def: InstRW<[SKLWriteResGroup152], (instregex "CVTPD2PSrm")>;
+def: InstRW<[SKLWriteResGroup152], (instregex "CVTTPD2DQrm")>;
+def: InstRW<[SKLWriteResGroup152], (instregex "MMX_CVTPD2PIirm")>;
+def: InstRW<[SKLWriteResGroup152], (instregex "MMX_CVTTPD2PIirm")>;
+
+def SKLWriteResGroup153 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
+ let Latency = 11;
+ let NumMicroOps = 6;
+ let ResourceCycles = [1,1,1,2,1];
+}
+def: InstRW<[SKLWriteResGroup153], (instregex "SHLD(16|32|64)mrCL")>;
+def: InstRW<[SKLWriteResGroup153], (instregex "SHRD(16|32|64)mrCL")>;
+
+def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
let Latency = 11;
let NumMicroOps = 7;
let ResourceCycles = [2,3,2];
}
-def: InstRW<[SKLWriteResGroup175], (instregex "RCL(16|32|64)rCL")>;
-def: InstRW<[SKLWriteResGroup175], (instregex "RCR(16|32|64)rCL")>;
+def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL")>;
+def: InstRW<[SKLWriteResGroup154], (instregex "RCR(16|32|64)rCL")>;
-def SKLWriteResGroup176 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
+def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
let Latency = 11;
let NumMicroOps = 9;
let ResourceCycles = [1,5,1,2];
}
-def: InstRW<[SKLWriteResGroup176], (instregex "RCL8rCL")>;
+def: InstRW<[SKLWriteResGroup155], (instregex "RCL8rCL")>;
-def SKLWriteResGroup177 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
+def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
let Latency = 11;
let NumMicroOps = 11;
let ResourceCycles = [2,9];
}
-def: InstRW<[SKLWriteResGroup177], (instregex "LOOPE")>;
-def: InstRW<[SKLWriteResGroup177], (instregex "LOOPNE")>;
-
-def SKLWriteResGroup178 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
- let Latency = 11;
- let NumMicroOps = 14;
- let ResourceCycles = [1,1,1,4,2,5];
-}
-def: InstRW<[SKLWriteResGroup178], (instregex "CMPXCHG8B")>;
+def: InstRW<[SKLWriteResGroup156], (instregex "LOOPE")>;
+def: InstRW<[SKLWriteResGroup156], (instregex "LOOPNE")>;
-def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0]> {
+def SKLWriteResGroup157 : SchedWriteRes<[SKLPort0]> {
let Latency = 12;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup179], (instregex "VSQRTPSYr")>;
-def: InstRW<[SKLWriteResGroup179], (instregex "VSQRTPSr")>;
-def: InstRW<[SKLWriteResGroup179], (instregex "VSQRTSSr")>;
+def: InstRW<[SKLWriteResGroup157], (instregex "VSQRTPSYr")>;
+def: InstRW<[SKLWriteResGroup157], (instregex "VSQRTPSr")>;
+def: InstRW<[SKLWriteResGroup157], (instregex "VSQRTSSr")>;
-def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+def SKLWriteResGroup158 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 12;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup180], (instregex "VSQRTPSYm")>;
-def: InstRW<[SKLWriteResGroup180], (instregex "VSQRTPSm")>;
-def: InstRW<[SKLWriteResGroup180], (instregex "VSQRTSSm")>;
+def: InstRW<[SKLWriteResGroup158], (instregex "PCLMULQDQrm")>;
+def: InstRW<[SKLWriteResGroup158], (instregex "VPCLMULQDQrm")>;
-def SKLWriteResGroup181 : SchedWriteRes<[SKLPort0]> {
+def SKLWriteResGroup159 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
+ let Latency = 12;
+ let NumMicroOps = 4;
+ let ResourceCycles = [2,1,1];
+}
+def: InstRW<[SKLWriteResGroup159], (instregex "HADDPDrm")>;
+def: InstRW<[SKLWriteResGroup159], (instregex "HADDPSrm")>;
+def: InstRW<[SKLWriteResGroup159], (instregex "HSUBPDrm")>;
+def: InstRW<[SKLWriteResGroup159], (instregex "HSUBPSrm")>;
+def: InstRW<[SKLWriteResGroup159], (instregex "VHADDPDrm")>;
+def: InstRW<[SKLWriteResGroup159], (instregex "VHADDPSrm")>;
+def: InstRW<[SKLWriteResGroup159], (instregex "VHSUBPDrm")>;
+def: InstRW<[SKLWriteResGroup159], (instregex "VHSUBPSrm")>;
+
+def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort015]> {
+ let Latency = 12;
+ let NumMicroOps = 4;
+ let ResourceCycles = [1,1,1,1];
+}
+def: InstRW<[SKLWriteResGroup160], (instregex "CVTTSS2SI64rm")>;
+
+def SKLWriteResGroup161 : SchedWriteRes<[SKLPort0]> {
let Latency = 13;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup181], (instregex "SQRTPSr")>;
-def: InstRW<[SKLWriteResGroup181], (instregex "SQRTSSr")>;
+def: InstRW<[SKLWriteResGroup161], (instregex "SQRTPSr")>;
+def: InstRW<[SKLWriteResGroup161], (instregex "SQRTSSr")>;
-def SKLWriteResGroup182 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 13;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let NumMicroOps = 3;
+ let ResourceCycles = [2,1];
}
-def: InstRW<[SKLWriteResGroup182], (instregex "SQRTPSm")>;
-def: InstRW<[SKLWriteResGroup182], (instregex "SQRTSSm")>;
+def: InstRW<[SKLWriteResGroup162], (instregex "ADD_FI16m")>;
+def: InstRW<[SKLWriteResGroup162], (instregex "ADD_FI32m")>;
+def: InstRW<[SKLWriteResGroup162], (instregex "SUBR_FI16m")>;
+def: InstRW<[SKLWriteResGroup162], (instregex "SUBR_FI32m")>;
+def: InstRW<[SKLWriteResGroup162], (instregex "SUB_FI16m")>;
+def: InstRW<[SKLWriteResGroup162], (instregex "SUB_FI32m")>;
-def SKLWriteResGroup187 : SchedWriteRes<[SKLPort5,SKLPort015]> {
+def SKLWriteResGroup163 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
let Latency = 13;
- let NumMicroOps = 4;
- let ResourceCycles = [1,3];
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup187], (instregex "DPPSrri")>;
-def: InstRW<[SKLWriteResGroup187], (instregex "VDPPSYrri")>;
-def: InstRW<[SKLWriteResGroup187], (instregex "VDPPSrri")>;
+def: InstRW<[SKLWriteResGroup163], (instregex "VCVTDQ2PDYrm")>;
-def SKLWriteResGroup188 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
+def SKLWriteResGroup164 : SchedWriteRes<[SKLPort5,SKLPort015]> {
let Latency = 13;
- let NumMicroOps = 5;
- let ResourceCycles = [1,1,3];
+ let NumMicroOps = 4;
+ let ResourceCycles = [1,3];
}
-def: InstRW<[SKLWriteResGroup188], (instregex "DPPSrmi")>;
-def: InstRW<[SKLWriteResGroup188], (instregex "VDPPSYrmi")>;
-def: InstRW<[SKLWriteResGroup188], (instregex "VDPPSrmi")>;
+def: InstRW<[SKLWriteResGroup164], (instregex "DPPSrri")>;
+def: InstRW<[SKLWriteResGroup164], (instregex "VDPPSYrri")>;
+def: InstRW<[SKLWriteResGroup164], (instregex "VDPPSrri")>;
-def SKLWriteResGroup189 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
+def SKLWriteResGroup165 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
let Latency = 13;
- let NumMicroOps = 11;
- let ResourceCycles = [2,1,1,4,1,2];
+ let NumMicroOps = 4;
+ let ResourceCycles = [2,1,1];
}
-def: InstRW<[SKLWriteResGroup189], (instregex "RCR(16|32|64)mCL")>;
-def: InstRW<[SKLWriteResGroup189], (instregex "RCR8mCL")>;
+def: InstRW<[SKLWriteResGroup165], (instregex "VHADDPDYrm")>;
+def: InstRW<[SKLWriteResGroup165], (instregex "VHADDPSYrm")>;
+def: InstRW<[SKLWriteResGroup165], (instregex "VHSUBPDYrm")>;
+def: InstRW<[SKLWriteResGroup165], (instregex "VHSUBPSYrm")>;
-def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0]> {
+def SKLWriteResGroup166 : SchedWriteRes<[SKLPort0]> {
let Latency = 14;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup190], (instregex "DIVPDrr")>;
-def: InstRW<[SKLWriteResGroup190], (instregex "DIVSDrr")>;
-def: InstRW<[SKLWriteResGroup190], (instregex "VDIVPDYrr")>;
-def: InstRW<[SKLWriteResGroup190], (instregex "VDIVPDrr")>;
-def: InstRW<[SKLWriteResGroup190], (instregex "VDIVSDrr")>;
+def: InstRW<[SKLWriteResGroup166], (instregex "DIVPDrr")>;
+def: InstRW<[SKLWriteResGroup166], (instregex "DIVSDrr")>;
+def: InstRW<[SKLWriteResGroup166], (instregex "VDIVPDYrr")>;
+def: InstRW<[SKLWriteResGroup166], (instregex "VDIVPDrr")>;
+def: InstRW<[SKLWriteResGroup166], (instregex "VDIVSDrr")>;
-def SKLWriteResGroup191 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+def SKLWriteResGroup167 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 14;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
+ let NumMicroOps = 3;
+ let ResourceCycles = [2,1];
+}
+def: InstRW<[SKLWriteResGroup167], (instregex "AESIMCrm")>;
+def: InstRW<[SKLWriteResGroup167], (instregex "VAESIMCrm")>;
+
+def SKLWriteResGroup168 : SchedWriteRes<[SKLPort23,SKLPort015]> {
+ let Latency = 14;
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,2];
+}
+def: InstRW<[SKLWriteResGroup168], (instregex "PMULLDrm")>;
+def: InstRW<[SKLWriteResGroup168], (instregex "ROUNDPDm")>;
+def: InstRW<[SKLWriteResGroup168], (instregex "ROUNDPSm")>;
+def: InstRW<[SKLWriteResGroup168], (instregex "ROUNDSDm")>;
+def: InstRW<[SKLWriteResGroup168], (instregex "ROUNDSSm")>;
+def: InstRW<[SKLWriteResGroup168], (instregex "VPMULLDrm")>;
+def: InstRW<[SKLWriteResGroup168], (instregex "VROUNDPDm")>;
+def: InstRW<[SKLWriteResGroup168], (instregex "VROUNDPSm")>;
+def: InstRW<[SKLWriteResGroup168], (instregex "VROUNDSDm")>;
+def: InstRW<[SKLWriteResGroup168], (instregex "VROUNDSSm")>;
+
+def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
+ let Latency = 14;
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup191], (instregex "DIVPDrm")>;
-def: InstRW<[SKLWriteResGroup191], (instregex "DIVSDrm")>;
-def: InstRW<[SKLWriteResGroup191], (instregex "VDIVPDYrm")>;
-def: InstRW<[SKLWriteResGroup191], (instregex "VDIVPDrm")>;
-def: InstRW<[SKLWriteResGroup191], (instregex "VDIVSDrm")>;
+def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI16m")>;
+def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI32m")>;
-def SKLWriteResGroup192 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
+def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
let Latency = 14;
let NumMicroOps = 10;
let ResourceCycles = [2,4,1,3];
}
-def: InstRW<[SKLWriteResGroup192], (instregex "RCR8rCL")>;
+def: InstRW<[SKLWriteResGroup170], (instregex "RCR8rCL")>;
-def SKLWriteResGroup193 : SchedWriteRes<[SKLPort0]> {
+def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> {
let Latency = 15;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup193], (instregex "DIVR_FPrST0")>;
-def: InstRW<[SKLWriteResGroup193], (instregex "DIVR_FST0r")>;
-def: InstRW<[SKLWriteResGroup193], (instregex "DIVR_FrST0")>;
+def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_FPrST0")>;
+def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_FST0r")>;
+def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_FrST0")>;
+
+def SKLWriteResGroup172 : SchedWriteRes<[SKLPort23,SKLPort015]> {
+ let Latency = 15;
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,2];
+}
+def: InstRW<[SKLWriteResGroup172], (instregex "VPMULLDYrm")>;
+def: InstRW<[SKLWriteResGroup172], (instregex "VROUNDYPDm")>;
+def: InstRW<[SKLWriteResGroup172], (instregex "VROUNDYPSm")>;
+
+def SKLWriteResGroup173 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
+ let Latency = 15;
+ let NumMicroOps = 4;
+ let ResourceCycles = [1,1,2];
+}
+def: InstRW<[SKLWriteResGroup173], (instregex "DPPDrmi")>;
+def: InstRW<[SKLWriteResGroup173], (instregex "VDPPDrmi")>;
-def SKLWriteResGroup194 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
let Latency = 15;
+ let NumMicroOps = 10;
+ let ResourceCycles = [1,1,1,5,1,1];
+}
+def: InstRW<[SKLWriteResGroup174], (instregex "RCL(16|32|64)mCL")>;
+def: InstRW<[SKLWriteResGroup174], (instregex "RCL8mCL")>;
+
+def SKLWriteResGroup175 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+ let Latency = 16;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup194], (instregex "DIV_F32m")>;
-def: InstRW<[SKLWriteResGroup194], (instregex "DIV_F64m")>;
+def: InstRW<[SKLWriteResGroup175], (instregex "DIVSSrm")>;
+def: InstRW<[SKLWriteResGroup175], (instregex "VDIVSSrm")>;
-def SKLWriteResGroup195 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
- let Latency = 15;
- let NumMicroOps = 8;
- let ResourceCycles = [1,1,1,1,1,1,2];
+def SKLWriteResGroup176 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+ let Latency = 16;
+ let NumMicroOps = 4;
+ let ResourceCycles = [3,1];
+}
+def: InstRW<[SKLWriteResGroup176], (instregex "PCMPISTRIrm")>;
+def: InstRW<[SKLWriteResGroup176], (instregex "PCMPISTRM128rm")>;
+def: InstRW<[SKLWriteResGroup176], (instregex "VPCMPISTRIrm")>;
+def: InstRW<[SKLWriteResGroup176], (instregex "VPCMPISTRM128rm")>;
+
+def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
+ let Latency = 16;
+ let NumMicroOps = 14;
+ let ResourceCycles = [1,1,1,4,2,5];
}
-def: InstRW<[SKLWriteResGroup195], (instregex "INSB")>;
-def: InstRW<[SKLWriteResGroup195], (instregex "INSL")>;
-def: InstRW<[SKLWriteResGroup195], (instregex "INSW")>;
+def: InstRW<[SKLWriteResGroup177], (instregex "CMPXCHG8B")>;
-def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0156]> {
+def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> {
let Latency = 16;
let NumMicroOps = 16;
let ResourceCycles = [16];
}
-def: InstRW<[SKLWriteResGroup196], (instregex "VZEROALL")>;
+def: InstRW<[SKLWriteResGroup178], (instregex "VZEROALL")>;
+
+def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+ let Latency = 17;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup179], (instregex "DIVPSrm")>;
+def: InstRW<[SKLWriteResGroup179], (instregex "VDIVPSrm")>;
+def: InstRW<[SKLWriteResGroup179], (instregex "VSQRTSSm")>;
-def SKLWriteResGroup197 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
+def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
let Latency = 17;
let NumMicroOps = 15;
let ResourceCycles = [2,1,2,4,2,4];
}
-def: InstRW<[SKLWriteResGroup197], (instregex "XCH_F")>;
+def: InstRW<[SKLWriteResGroup180], (instregex "XCH_F")>;
-def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0]> {
+def SKLWriteResGroup181 : SchedWriteRes<[SKLPort0]> {
let Latency = 18;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup198], (instregex "VSQRTPDYr")>;
-def: InstRW<[SKLWriteResGroup198], (instregex "VSQRTPDr")>;
-def: InstRW<[SKLWriteResGroup198], (instregex "VSQRTSDr")>;
+def: InstRW<[SKLWriteResGroup181], (instregex "VSQRTPDYr")>;
+def: InstRW<[SKLWriteResGroup181], (instregex "VSQRTPDr")>;
+def: InstRW<[SKLWriteResGroup181], (instregex "VSQRTSDr")>;
-def SKLWriteResGroup199 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+def SKLWriteResGroup182 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 18;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup199], (instregex "VSQRTPDYm")>;
-def: InstRW<[SKLWriteResGroup199], (instregex "VSQRTPDm")>;
-def: InstRW<[SKLWriteResGroup199], (instregex "VSQRTSDm")>;
-
-def SKLWriteResGroup200 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
- let Latency = 18;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SKLWriteResGroup200], (instregex "DIV_FI16m")>;
-def: InstRW<[SKLWriteResGroup200], (instregex "DIV_FI32m")>;
+def: InstRW<[SKLWriteResGroup182], (instregex "SQRTSSm")>;
+def: InstRW<[SKLWriteResGroup182], (instregex "VDIVPSYrm")>;
+def: InstRW<[SKLWriteResGroup182], (instregex "VSQRTPSm")>;
-def SKLWriteResGroup201 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort0156]> {
+def SKLWriteResGroup183 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort0156]> {
let Latency = 18;
let NumMicroOps = 8;
let ResourceCycles = [4,3,1];
}
-def: InstRW<[SKLWriteResGroup201], (instregex "PCMPESTRIrr")>;
-def: InstRW<[SKLWriteResGroup201], (instregex "VPCMPESTRIrr")>;
+def: InstRW<[SKLWriteResGroup183], (instregex "PCMPESTRIrr")>;
+def: InstRW<[SKLWriteResGroup183], (instregex "VPCMPESTRIrr")>;
-def SKLWriteResGroup202 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
+def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
let Latency = 18;
let NumMicroOps = 8;
let ResourceCycles = [1,1,1,5];
}
-def: InstRW<[SKLWriteResGroup202], (instregex "CPUID")>;
-def: InstRW<[SKLWriteResGroup202], (instregex "RDTSC")>;
+def: InstRW<[SKLWriteResGroup184], (instregex "CPUID")>;
+def: InstRW<[SKLWriteResGroup184], (instregex "RDTSC")>;
-def SKLWriteResGroup203 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort0156]> {
+def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
let Latency = 18;
- let NumMicroOps = 9;
- let ResourceCycles = [4,3,1,1];
-}
-def: InstRW<[SKLWriteResGroup203], (instregex "PCMPESTRIrm")>;
-def: InstRW<[SKLWriteResGroup203], (instregex "VPCMPESTRIrm")>;
-
-def SKLWriteResGroup204 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
- let Latency = 18;
- let NumMicroOps = 19;
- let ResourceCycles = [2,1,4,1,1,4,6];
+ let NumMicroOps = 11;
+ let ResourceCycles = [2,1,1,4,1,2];
}
-def: InstRW<[SKLWriteResGroup204], (instregex "CMPXCHG16B")>;
+def: InstRW<[SKLWriteResGroup185], (instregex "RCR(16|32|64)mCL")>;
+def: InstRW<[SKLWriteResGroup185], (instregex "RCR8mCL")>;
-def SKLWriteResGroup205 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort015,SKLPort0156]> {
+def SKLWriteResGroup186 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 19;
- let NumMicroOps = 9;
- let ResourceCycles = [4,3,1,1];
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup205], (instregex "PCMPESTRM128rr")>;
-def: InstRW<[SKLWriteResGroup205], (instregex "VPCMPESTRM128rr")>;
+def: InstRW<[SKLWriteResGroup186], (instregex "DIVSDrm")>;
+def: InstRW<[SKLWriteResGroup186], (instregex "SQRTPSm")>;
+def: InstRW<[SKLWriteResGroup186], (instregex "VDIVSDrm")>;
+def: InstRW<[SKLWriteResGroup186], (instregex "VSQRTPSYm")>;
-def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort015,SKLPort0156]> {
+def SKLWriteResGroup187 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
let Latency = 19;
- let NumMicroOps = 10;
- let ResourceCycles = [4,3,1,1,1];
+ let NumMicroOps = 5;
+ let ResourceCycles = [1,1,3];
}
-def: InstRW<[SKLWriteResGroup206], (instregex "PCMPESTRM128rm")>;
-def: InstRW<[SKLWriteResGroup206], (instregex "VPCMPESTRM128rm")>;
+def: InstRW<[SKLWriteResGroup187], (instregex "DPPSrmi")>;
+def: InstRW<[SKLWriteResGroup187], (instregex "VDPPSrmi")>;
-def SKLWriteResGroup207 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort015]> {
+def SKLWriteResGroup188 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort015,SKLPort0156]> {
let Latency = 19;
- let NumMicroOps = 11;
- let ResourceCycles = [3,6,1,1];
+ let NumMicroOps = 9;
+ let ResourceCycles = [4,3,1,1];
}
-def: InstRW<[SKLWriteResGroup207], (instregex "AESKEYGENASSIST128rm")>;
-def: InstRW<[SKLWriteResGroup207], (instregex "VAESKEYGENASSIST128rm")>;
+def: InstRW<[SKLWriteResGroup188], (instregex "PCMPESTRM128rr")>;
+def: InstRW<[SKLWriteResGroup188], (instregex "VPCMPESTRM128rr")>;
-def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0]> {
+def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> {
let Latency = 20;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup208], (instregex "DIV_FPrST0")>;
-def: InstRW<[SKLWriteResGroup208], (instregex "DIV_FST0r")>;
-def: InstRW<[SKLWriteResGroup208], (instregex "DIV_FrST0")>;
-def: InstRW<[SKLWriteResGroup208], (instregex "SQRTPDr")>;
-def: InstRW<[SKLWriteResGroup208], (instregex "SQRTSDr")>;
+def: InstRW<[SKLWriteResGroup189], (instregex "DIV_FPrST0")>;
+def: InstRW<[SKLWriteResGroup189], (instregex "DIV_FST0r")>;
+def: InstRW<[SKLWriteResGroup189], (instregex "DIV_FrST0")>;
+def: InstRW<[SKLWriteResGroup189], (instregex "SQRTPDr")>;
+def: InstRW<[SKLWriteResGroup189], (instregex "SQRTSDr")>;
-def SKLWriteResGroup209 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 20;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup209], (instregex "DIVR_F32m")>;
-def: InstRW<[SKLWriteResGroup209], (instregex "DIVR_F64m")>;
-def: InstRW<[SKLWriteResGroup209], (instregex "SQRTPDm")>;
-def: InstRW<[SKLWriteResGroup209], (instregex "SQRTSDm")>;
+def: InstRW<[SKLWriteResGroup190], (instregex "DIVPDrm")>;
+def: InstRW<[SKLWriteResGroup190], (instregex "VDIVPDrm")>;
+
+def SKLWriteResGroup191 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
+ let Latency = 20;
+ let NumMicroOps = 5;
+ let ResourceCycles = [1,1,3];
+}
+def: InstRW<[SKLWriteResGroup191], (instregex "VDPPSYrmi")>;
+
+def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
+ let Latency = 20;
+ let NumMicroOps = 8;
+ let ResourceCycles = [1,1,1,1,1,1,2];
+}
+def: InstRW<[SKLWriteResGroup192], (instregex "INSB")>;
+def: InstRW<[SKLWriteResGroup192], (instregex "INSL")>;
+def: InstRW<[SKLWriteResGroup192], (instregex "INSW")>;
-def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> {
+def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> {
let Latency = 20;
let NumMicroOps = 10;
let ResourceCycles = [1,2,7];
}
-def: InstRW<[SKLWriteResGroup210], (instregex "MWAITrr")>;
+def: InstRW<[SKLWriteResGroup193], (instregex "MWAITrr")>;
-def SKLWriteResGroup211 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort015]> {
+def SKLWriteResGroup194 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort015]> {
let Latency = 20;
let NumMicroOps = 11;
let ResourceCycles = [3,6,2];
}
-def: InstRW<[SKLWriteResGroup211], (instregex "AESKEYGENASSIST128rr")>;
-def: InstRW<[SKLWriteResGroup211], (instregex "VAESKEYGENASSIST128rr")>;
+def: InstRW<[SKLWriteResGroup194], (instregex "AESKEYGENASSIST128rr")>;
+def: InstRW<[SKLWriteResGroup194], (instregex "VAESKEYGENASSIST128rr")>;
-def SKLWriteResGroup212 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
- let Latency = 17;
+def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+ let Latency = 21;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup195], (instregex "VDIVPDYrm")>;
+
+def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+ let Latency = 22;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F32m")>;
+def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F64m")>;
+
+def SKLWriteResGroup196_1 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
+ let Latency = 22;
let NumMicroOps = 5;
let ResourceCycles = [1,2,1,1];
}
-def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERDPSrm")>;
-def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERDPDrm")>;
-def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERQPDrm")>;
-def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERQPSrm")>;
-def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERDDrm")>;
-def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERDQrm")>;
-def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERQDrm")>;
-def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERQQrm")>;
-def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERDDrm")>;
-def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERQDrm")>;
-def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERDQrm")>;
-def: InstRW<[SKLWriteResGroup212], (instregex "VPGATHERQQrm")>;
-def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERDPSrm")>;
-def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERQPSrm")>;
-def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERDPDrm")>;
-def: InstRW<[SKLWriteResGroup212], (instregex "VGATHERQPDrm")>;
+def: InstRW<[SKLWriteResGroup196_1], (instregex "VGATHERDPSrm")>;
+def: InstRW<[SKLWriteResGroup196_1], (instregex "VGATHERDPDrm")>;
+def: InstRW<[SKLWriteResGroup196_1], (instregex "VGATHERQPDrm")>;
+def: InstRW<[SKLWriteResGroup196_1], (instregex "VGATHERQPSrm")>;
+def: InstRW<[SKLWriteResGroup196_1], (instregex "VPGATHERDDrm")>;
+def: InstRW<[SKLWriteResGroup196_1], (instregex "VPGATHERDQrm")>;
+def: InstRW<[SKLWriteResGroup196_1], (instregex "VPGATHERQDrm")>;
+def: InstRW<[SKLWriteResGroup196_1], (instregex "VPGATHERQQrm")>;
+def: InstRW<[SKLWriteResGroup196_1], (instregex "VPGATHERDDrm")>;
+def: InstRW<[SKLWriteResGroup196_1], (instregex "VPGATHERQDrm")>;
+def: InstRW<[SKLWriteResGroup196_1], (instregex "VPGATHERDQrm")>;
+def: InstRW<[SKLWriteResGroup196_1], (instregex "VPGATHERQQrm")>;
+def: InstRW<[SKLWriteResGroup196_1], (instregex "VGATHERDPSrm")>;
+def: InstRW<[SKLWriteResGroup196_1], (instregex "VGATHERQPSrm")>;
+def: InstRW<[SKLWriteResGroup196_1], (instregex "VGATHERDPDrm")>;
+def: InstRW<[SKLWriteResGroup196_1], (instregex "VGATHERQPDrm")>;
-def SKLWriteResGroup213 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
- let Latency = 20;
+def SKLWriteResGroup196_2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
+ let Latency = 25;
let NumMicroOps = 5;
let ResourceCycles = [1,2,1,1];
}
-def: InstRW<[SKLWriteResGroup213], (instregex "VGATHERDPSYrm")>;
-def: InstRW<[SKLWriteResGroup213], (instregex "VGATHERQPDYrm")>;
-def: InstRW<[SKLWriteResGroup213], (instregex "VGATHERQPSYrm")>;
-def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERDDYrm")>;
-def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERDQYrm")>;
-def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERQDYrm")>;
-def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERQQYrm")>;
-def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERDDYrm")>;
-def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERQDYrm")>;
-def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERDQYrm")>;
-def: InstRW<[SKLWriteResGroup213], (instregex "VPGATHERQQYrm")>;
-def: InstRW<[SKLWriteResGroup213], (instregex "VGATHERDPSYrm")>;
-def: InstRW<[SKLWriteResGroup213], (instregex "VGATHERQPSYrm")>;
-def: InstRW<[SKLWriteResGroup213], (instregex "VGATHERDPDYrm")>;
+def: InstRW<[SKLWriteResGroup196_2], (instregex "VGATHERDPSYrm")>;
+def: InstRW<[SKLWriteResGroup196_2], (instregex "VGATHERQPDYrm")>;
+def: InstRW<[SKLWriteResGroup196_2], (instregex "VGATHERQPSYrm")>;
+def: InstRW<[SKLWriteResGroup196_2], (instregex "VPGATHERDDYrm")>;
+def: InstRW<[SKLWriteResGroup196_2], (instregex "VPGATHERDQYrm")>;
+def: InstRW<[SKLWriteResGroup196_2], (instregex "VPGATHERQDYrm")>;
+def: InstRW<[SKLWriteResGroup196_2], (instregex "VPGATHERQQYrm")>;
+def: InstRW<[SKLWriteResGroup196_2], (instregex "VPGATHERDDYrm")>;
+def: InstRW<[SKLWriteResGroup196_2], (instregex "VPGATHERQDYrm")>;
+def: InstRW<[SKLWriteResGroup196_2], (instregex "VPGATHERDQYrm")>;
+def: InstRW<[SKLWriteResGroup196_2], (instregex "VPGATHERQQYrm")>;
+def: InstRW<[SKLWriteResGroup196_2], (instregex "VGATHERDPSYrm")>;
+def: InstRW<[SKLWriteResGroup196_2], (instregex "VGATHERQPSYrm")>;
+def: InstRW<[SKLWriteResGroup196_2], (instregex "VGATHERDPDYrm")>;
+
+def SKLWriteResGroup197 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+ let Latency = 23;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup197], (instregex "VSQRTSDm")>;
-def SKLWriteResGroup215 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
+def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
let Latency = 23;
+ let NumMicroOps = 19;
+ let ResourceCycles = [2,1,4,1,1,4,6];
+}
+def: InstRW<[SKLWriteResGroup198], (instregex "CMPXCHG16B")>;
+
+def SKLWriteResGroup199 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+ let Latency = 24;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup199], (instregex "VSQRTPDm")>;
+
+def SKLWriteResGroup200 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort0156]> {
+ let Latency = 24;
+ let NumMicroOps = 9;
+ let ResourceCycles = [4,3,1,1];
+}
+def: InstRW<[SKLWriteResGroup200], (instregex "PCMPESTRIrm")>;
+def: InstRW<[SKLWriteResGroup200], (instregex "VPCMPESTRIrm")>;
+
+def SKLWriteResGroup201 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+ let Latency = 25;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup201], (instregex "SQRTSDm")>;
+def: InstRW<[SKLWriteResGroup201], (instregex "VSQRTPDYm")>;
+
+def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
+ let Latency = 25;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup215], (instregex "DIVR_FI16m")>;
-def: InstRW<[SKLWriteResGroup215], (instregex "DIVR_FI32m")>;
+def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI16m")>;
+def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI32m")>;
-def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort0156]> {
- let Latency = 23;
+def SKLWriteResGroup203 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort015,SKLPort0156]> {
+ let Latency = 25;
+ let NumMicroOps = 10;
+ let ResourceCycles = [4,3,1,1,1];
+}
+def: InstRW<[SKLWriteResGroup203], (instregex "PCMPESTRM128rm")>;
+def: InstRW<[SKLWriteResGroup203], (instregex "VPCMPESTRM128rm")>;
+
+def SKLWriteResGroup204 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort015]> {
+ let Latency = 25;
+ let NumMicroOps = 11;
+ let ResourceCycles = [3,6,1,1];
+}
+def: InstRW<[SKLWriteResGroup204], (instregex "AESKEYGENASSIST128rm")>;
+def: InstRW<[SKLWriteResGroup204], (instregex "VAESKEYGENASSIST128rm")>;
+
+def SKLWriteResGroup205 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+ let Latency = 26;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup205], (instregex "SQRTPDm")>;
+
+def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> {
+ let Latency = 27;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F32m")>;
+def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F64m")>;
+
+def SKLWriteResGroup207 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort0156]> {
+ let Latency = 28;
let NumMicroOps = 8;
let ResourceCycles = [2,4,1,1];
}
-def: InstRW<[SKLWriteResGroup217], (instregex "IDIV(16|32|64)m")>;
-def: InstRW<[SKLWriteResGroup217], (instregex "IDIV8m")>;
+def: InstRW<[SKLWriteResGroup207], (instregex "IDIV(16|32|64)m")>;
+def: InstRW<[SKLWriteResGroup207], (instregex "IDIV8m")>;
-def SKLWriteResGroup222 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> {
+def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
let Latency = 30;
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,1,1];
+}
+def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI16m")>;
+def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI32m")>;
+
+def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> {
+ let Latency = 35;
let NumMicroOps = 23;
let ResourceCycles = [1,5,3,4,10];
}
-def: InstRW<[SKLWriteResGroup222], (instregex "IN32ri")>;
-def: InstRW<[SKLWriteResGroup222], (instregex "IN32rr")>;
-def: InstRW<[SKLWriteResGroup222], (instregex "IN8ri")>;
-def: InstRW<[SKLWriteResGroup222], (instregex "IN8rr")>;
+def: InstRW<[SKLWriteResGroup209], (instregex "IN32ri")>;
+def: InstRW<[SKLWriteResGroup209], (instregex "IN32rr")>;
+def: InstRW<[SKLWriteResGroup209], (instregex "IN8ri")>;
+def: InstRW<[SKLWriteResGroup209], (instregex "IN8rr")>;
-def SKLWriteResGroup223 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
- let Latency = 30;
+def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
+ let Latency = 35;
let NumMicroOps = 23;
let ResourceCycles = [1,5,2,1,4,10];
}
-def: InstRW<[SKLWriteResGroup223], (instregex "OUT32ir")>;
-def: InstRW<[SKLWriteResGroup223], (instregex "OUT32rr")>;
-def: InstRW<[SKLWriteResGroup223], (instregex "OUT8ir")>;
-def: InstRW<[SKLWriteResGroup223], (instregex "OUT8rr")>;
+def: InstRW<[SKLWriteResGroup210], (instregex "OUT32ir")>;
+def: InstRW<[SKLWriteResGroup210], (instregex "OUT32rr")>;
+def: InstRW<[SKLWriteResGroup210], (instregex "OUT8ir")>;
+def: InstRW<[SKLWriteResGroup210], (instregex "OUT8rr")>;
-def SKLWriteResGroup224 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
- let Latency = 32;
+def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
+ let Latency = 37;
let NumMicroOps = 31;
let ResourceCycles = [1,8,1,21];
}
-def: InstRW<[SKLWriteResGroup224], (instregex "XRSTOR(64?)")>;
+def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64?)")>;
-def SKLWriteResGroup225 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> {
- let Latency = 35;
+def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> {
+ let Latency = 40;
let NumMicroOps = 18;
let ResourceCycles = [1,1,2,3,1,1,1,8];
}
-def: InstRW<[SKLWriteResGroup225], (instregex "VMCLEARm")>;
+def: InstRW<[SKLWriteResGroup212], (instregex "VMCLEARm")>;
-def SKLWriteResGroup226 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
- let Latency = 36;
+def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
+ let Latency = 41;
let NumMicroOps = 39;
let ResourceCycles = [1,10,1,1,26];
}
-def: InstRW<[SKLWriteResGroup226], (instregex "XSAVE64")>;
+def: InstRW<[SKLWriteResGroup213], (instregex "XSAVE64")>;
-def SKLWriteResGroup231 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
- let Latency = 37;
+def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
+ let Latency = 42;
+ let NumMicroOps = 22;
+ let ResourceCycles = [2,20];
+}
+def: InstRW<[SKLWriteResGroup214], (instregex "RDTSCP")>;
+
+def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
+ let Latency = 42;
let NumMicroOps = 40;
let ResourceCycles = [1,11,1,1,26];
}
-def: InstRW<[SKLWriteResGroup231], (instregex "XSAVE")>;
+def: InstRW<[SKLWriteResGroup215], (instregex "XSAVE")>;
-def SKLWriteResGroup232 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
- let Latency = 41;
+def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
+ let Latency = 46;
let NumMicroOps = 44;
let ResourceCycles = [1,11,1,1,30];
}
-def: InstRW<[SKLWriteResGroup232], (instregex "XSAVEOPT")>;
-
-def SKLWriteResGroup233 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
- let Latency = 42;
- let NumMicroOps = 22;
- let ResourceCycles = [2,20];
-}
-def: InstRW<[SKLWriteResGroup233], (instregex "RDTSCP")>;
+def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>;
-def SKLWriteResGroup234 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> {
- let Latency = 57;
+def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> {
+ let Latency = 62;
let NumMicroOps = 64;
let ResourceCycles = [2,8,5,10,39];
}
-def: InstRW<[SKLWriteResGroup234], (instregex "FLDENVm")>;
-def: InstRW<[SKLWriteResGroup234], (instregex "FLDENVm")>;
+def: InstRW<[SKLWriteResGroup217], (instregex "FLDENVm")>;
+def: InstRW<[SKLWriteResGroup217], (instregex "FLDENVm")>;
-def SKLWriteResGroup235 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
- let Latency = 58;
+def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
+ let Latency = 63;
let NumMicroOps = 88;
let ResourceCycles = [4,4,31,1,2,1,45];
}
-def: InstRW<[SKLWriteResGroup235], (instregex "FXRSTOR64")>;
+def: InstRW<[SKLWriteResGroup218], (instregex "FXRSTOR64")>;
-def SKLWriteResGroup236 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
- let Latency = 58;
+def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
+ let Latency = 63;
let NumMicroOps = 90;
let ResourceCycles = [4,2,33,1,2,1,47];
}
-def: InstRW<[SKLWriteResGroup236], (instregex "FXRSTOR")>;
+def: InstRW<[SKLWriteResGroup219], (instregex "FXRSTOR")>;
-def SKLWriteResGroup239 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> {
+def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> {
let Latency = 75;
let NumMicroOps = 15;
let ResourceCycles = [6,3,6];
}
-def: InstRW<[SKLWriteResGroup239], (instregex "FNINIT")>;
+def: InstRW<[SKLWriteResGroup220], (instregex "FNINIT")>;
-def SKLWriteResGroup240 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
+def SKLWriteResGroup221 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
let Latency = 76;
let NumMicroOps = 32;
let ResourceCycles = [7,2,8,3,1,11];
}
-def: InstRW<[SKLWriteResGroup240], (instregex "DIV(16|32|64)r")>;
+def: InstRW<[SKLWriteResGroup221], (instregex "DIV(16|32|64)r")>;
-def SKLWriteResGroup241 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
+def SKLWriteResGroup222 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
let Latency = 102;
let NumMicroOps = 66;
let ResourceCycles = [4,2,4,8,14,34];
}
-def: InstRW<[SKLWriteResGroup241], (instregex "IDIV(16|32|64)r")>;
+def: InstRW<[SKLWriteResGroup222], (instregex "IDIV(16|32|64)r")>;
-def SKLWriteResGroup242 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> {
- let Latency = 105;
+def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> {
+ let Latency = 106;
let NumMicroOps = 100;
let ResourceCycles = [9,1,11,16,1,11,21,30];
}
-def: InstRW<[SKLWriteResGroup242], (instregex "FSTENVm")>;
-def: InstRW<[SKLWriteResGroup242], (instregex "FSTENVm")>;
+def: InstRW<[SKLWriteResGroup223], (instregex "FSTENVm")>;
+def: InstRW<[SKLWriteResGroup223], (instregex "FSTENVm")>;
} // SchedModel
Modified: llvm/trunk/test/CodeGen/X86/aes-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/aes-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/aes-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/aes-schedule.ll Mon Oct 16 23:47:04 2017
@@ -37,8 +37,8 @@ define <2 x i64> @test_aesdec(<2 x i64>
; SKYLAKE-LABEL: test_aesdec:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vaesdec %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: vaesdec (%rdi), %xmm0, %xmm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vaesdec (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_aesdec:
; BTVER2: # BB#0:
@@ -86,8 +86,8 @@ define <2 x i64> @test_aesdeclast(<2 x i
; SKYLAKE-LABEL: test_aesdeclast:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vaesdeclast %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: vaesdeclast (%rdi), %xmm0, %xmm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vaesdeclast (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_aesdeclast:
; BTVER2: # BB#0:
@@ -135,8 +135,8 @@ define <2 x i64> @test_aesenc(<2 x i64>
; SKYLAKE-LABEL: test_aesenc:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vaesenc %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: vaesenc (%rdi), %xmm0, %xmm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vaesenc (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_aesenc:
; BTVER2: # BB#0:
@@ -184,8 +184,8 @@ define <2 x i64> @test_aesenclast(<2 x i
; SKYLAKE-LABEL: test_aesenclast:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vaesenclast %xmm1, %xmm0, %xmm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: vaesenclast (%rdi), %xmm0, %xmm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vaesenclast (%rdi), %xmm0, %xmm0 # sched: [10:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_aesenclast:
; BTVER2: # BB#0:
@@ -237,9 +237,9 @@ define <2 x i64> @test_aesimc(<2 x i64>
; SKYLAKE-LABEL: test_aesimc:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vaesimc %xmm0, %xmm0 # sched: [8:2.00]
-; SKYLAKE-NEXT: vaesimc (%rdi), %xmm1 # sched: [8:2.00]
-; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vaesimc (%rdi), %xmm1 # sched: [14:2.00]
+; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_aesimc:
; BTVER2: # BB#0:
@@ -294,9 +294,9 @@ define <2 x i64> @test_aeskeygenassist(<
; SKYLAKE-LABEL: test_aeskeygenassist:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vaeskeygenassist $7, %xmm0, %xmm0 # sched: [20:6.00]
-; SKYLAKE-NEXT: vaeskeygenassist $7, (%rdi), %xmm1 # sched: [19:6.00]
-; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vaeskeygenassist $7, (%rdi), %xmm1 # sched: [25:6.00]
+; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_aeskeygenassist:
; BTVER2: # BB#0:
Modified: llvm/trunk/test/CodeGen/X86/avx-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-schedule.ll Mon Oct 16 23:47:04 2017
@@ -30,8 +30,8 @@ define <4 x double> @test_addpd(<4 x dou
; SKYLAKE-LABEL: test_addpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vaddpd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vaddpd (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_addpd:
; SKX: # BB#0:
@@ -78,8 +78,8 @@ define <8 x float> @test_addps(<8 x floa
; SKYLAKE-LABEL: test_addps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vaddps (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vaddps (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_addps:
; SKX: # BB#0:
@@ -126,8 +126,8 @@ define <4 x double> @test_addsubpd(<4 x
; SKYLAKE-LABEL: test_addsubpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vaddsubpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vaddsubpd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vaddsubpd (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_addsubpd:
; SKX: # BB#0:
@@ -175,8 +175,8 @@ define <8 x float> @test_addsubps(<8 x f
; SKYLAKE-LABEL: test_addsubps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vaddsubps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vaddsubps (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vaddsubps (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_addsubps:
; SKX: # BB#0:
@@ -226,10 +226,10 @@ define <4 x double> @test_andnotpd(<4 x
;
; SKYLAKE-LABEL: test_andnotpd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vandnpd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vandnpd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vandnpd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vandnpd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
; SKYLAKE-NEXT: vaddpd %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_andnotpd:
; SKX: # BB#0:
@@ -288,10 +288,10 @@ define <8 x float> @test_andnotps(<8 x f
;
; SKYLAKE-LABEL: test_andnotps:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vandnps %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vandnps (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vandnps %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vandnps (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
; SKYLAKE-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_andnotps:
; SKX: # BB#0:
@@ -350,10 +350,10 @@ define <4 x double> @test_andpd(<4 x dou
;
; SKYLAKE-LABEL: test_andpd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vandpd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vandpd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vandpd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vandpd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
; SKYLAKE-NEXT: vaddpd %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_andpd:
; SKX: # BB#0:
@@ -410,10 +410,10 @@ define <8 x float> @test_andps(<8 x floa
;
; SKYLAKE-LABEL: test_andps:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vandps %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vandps (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vandps %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vandps (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
; SKYLAKE-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_andps:
; SKX: # BB#0:
@@ -470,10 +470,10 @@ define <4 x double> @test_blendpd(<4 x d
;
; SKYLAKE-LABEL: test_blendpd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3] sched: [1:0.50]
+; SKYLAKE-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3] sched: [1:0.33]
; SKYLAKE-NEXT: vaddpd %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],mem[1,2],ymm0[3] sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],mem[1,2],ymm0[3] sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_blendpd:
; SKX: # BB#0:
@@ -523,9 +523,9 @@ define <8 x float> @test_blendps(<8 x fl
;
; SKYLAKE-LABEL: test_blendps:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3,4,5,6,7] sched: [1:0.50]
-; SKYLAKE-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],mem[2],ymm0[3],mem[4,5,6],ymm0[7] sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3,4,5,6,7] sched: [1:0.33]
+; SKYLAKE-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],mem[2],ymm0[3],mem[4,5,6],ymm0[7] sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_blendps:
; SKX: # BB#0:
@@ -572,8 +572,8 @@ define <4 x double> @test_blendvpd(<4 x
; SKYLAKE-LABEL: test_blendvpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vblendvpd %ymm2, %ymm1, %ymm0, %ymm0 # sched: [2:0.67]
-; SKYLAKE-NEXT: vblendvpd %ymm2, (%rdi), %ymm0, %ymm0 # sched: [2:0.67]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vblendvpd %ymm2, (%rdi), %ymm0, %ymm0 # sched: [9:0.67]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_blendvpd:
; SKX: # BB#0:
@@ -621,8 +621,8 @@ define <8 x float> @test_blendvps(<8 x f
; SKYLAKE-LABEL: test_blendvps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vblendvps %ymm2, %ymm1, %ymm0, %ymm0 # sched: [2:0.67]
-; SKYLAKE-NEXT: vblendvps %ymm2, (%rdi), %ymm0, %ymm0 # sched: [2:0.67]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vblendvps %ymm2, (%rdi), %ymm0, %ymm0 # sched: [9:0.67]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_blendvps:
; SKX: # BB#0:
@@ -666,8 +666,8 @@ define <8 x float> @test_broadcastf128(<
;
; SKYLAKE-LABEL: test_broadcastf128:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1] sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1] sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_broadcastf128:
; SKX: # BB#0:
@@ -706,8 +706,8 @@ define <4 x double> @test_broadcastsd_ym
;
; SKYLAKE-LABEL: test_broadcastsd_ymm:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vbroadcastsd (%rdi), %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vbroadcastsd (%rdi), %ymm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_broadcastsd_ymm:
; SKX: # BB#0:
@@ -747,8 +747,8 @@ define <4 x float> @test_broadcastss(flo
;
; SKYLAKE-LABEL: test_broadcastss:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vbroadcastss (%rdi), %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vbroadcastss (%rdi), %xmm0 # sched: [6:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_broadcastss:
; SKX: # BB#0:
@@ -788,8 +788,8 @@ define <8 x float> @test_broadcastss_ymm
;
; SKYLAKE-LABEL: test_broadcastss_ymm:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vbroadcastss (%rdi), %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vbroadcastss (%rdi), %ymm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_broadcastss_ymm:
; SKX: # BB#0:
@@ -836,9 +836,9 @@ define <4 x double> @test_cmppd(<4 x dou
; SKYLAKE-LABEL: test_cmppd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm1 # sched: [4:0.33]
-; SKYLAKE-NEXT: vcmpeqpd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vorpd %ymm0, %ymm1, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vcmpeqpd (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: vorpd %ymm0, %ymm1, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cmppd:
; SKX: # BB#0:
@@ -897,9 +897,9 @@ define <8 x float> @test_cmpps(<8 x floa
; SKYLAKE-LABEL: test_cmpps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcmpeqps %ymm1, %ymm0, %ymm1 # sched: [4:0.33]
-; SKYLAKE-NEXT: vcmpeqps (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vorps %ymm0, %ymm1, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vcmpeqps (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: vorps %ymm0, %ymm1, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cmpps:
; SKX: # BB#0:
@@ -958,9 +958,9 @@ define <4 x double> @test_cvtdq2pd(<4 x
; SKYLAKE-LABEL: test_cvtdq2pd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvtdq2pd %xmm0, %ymm0 # sched: [7:1.00]
-; SKYLAKE-NEXT: vcvtdq2pd (%rdi), %ymm1 # sched: [7:1.00]
+; SKYLAKE-NEXT: vcvtdq2pd (%rdi), %ymm1 # sched: [13:1.00]
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvtdq2pd:
; SKX: # BB#0:
@@ -1016,9 +1016,9 @@ define <8 x float> @test_cvtdq2ps(<8 x i
; SKYLAKE-LABEL: test_cvtdq2ps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvtdq2ps %ymm0, %ymm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vcvtdq2ps (%rdi), %ymm1 # sched: [4:0.50]
+; SKYLAKE-NEXT: vcvtdq2ps (%rdi), %ymm1 # sched: [11:0.50]
; SKYLAKE-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvtdq2ps:
; SKX: # BB#0:
@@ -1074,7 +1074,7 @@ define <8 x i32> @test_cvtpd2dq(<4 x dou
; SKYLAKE-NEXT: vcvttpd2dq %ymm0, %xmm0 # sched: [7:1.00]
; SKYLAKE-NEXT: vcvttpd2dqy (%rdi), %xmm1 # sched: [8:1.00]
; SKYLAKE-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvtpd2dq:
; SKX: # BB#0:
@@ -1130,7 +1130,7 @@ define <8 x float> @test_cvtpd2ps(<4 x d
; SKYLAKE-NEXT: vcvtpd2ps %ymm0, %xmm0 # sched: [7:1.00]
; SKYLAKE-NEXT: vcvtpd2psy (%rdi), %xmm1 # sched: [8:1.00]
; SKYLAKE-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvtpd2ps:
; SKX: # BB#0:
@@ -1184,9 +1184,9 @@ define <8 x i32> @test_cvtps2dq(<8 x flo
; SKYLAKE-LABEL: test_cvtps2dq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvttps2dq %ymm0, %ymm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vcvttps2dq (%rdi), %ymm1 # sched: [4:0.50]
-; SKYLAKE-NEXT: vorps %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vcvttps2dq (%rdi), %ymm1 # sched: [11:0.50]
+; SKYLAKE-NEXT: vorps %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvtps2dq:
; SKX: # BB#0:
@@ -1237,8 +1237,8 @@ define <4 x double> @test_divpd(<4 x dou
; SKYLAKE-LABEL: test_divpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vdivpd %ymm1, %ymm0, %ymm0 # sched: [14:1.00]
-; SKYLAKE-NEXT: vdivpd (%rdi), %ymm0, %ymm0 # sched: [14:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vdivpd (%rdi), %ymm0, %ymm0 # sched: [21:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_divpd:
; SKX: # BB#0:
@@ -1285,8 +1285,8 @@ define <8 x float> @test_divps(<8 x floa
; SKYLAKE-LABEL: test_divps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vdivps %ymm1, %ymm0, %ymm0 # sched: [11:1.00]
-; SKYLAKE-NEXT: vdivps (%rdi), %ymm0, %ymm0 # sched: [11:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vdivps (%rdi), %ymm0, %ymm0 # sched: [18:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_divps:
; SKX: # BB#0:
@@ -1333,8 +1333,8 @@ define <8 x float> @test_dpps(<8 x float
; SKYLAKE-LABEL: test_dpps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vdpps $7, %ymm1, %ymm0, %ymm0 # sched: [13:1.33]
-; SKYLAKE-NEXT: vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [13:1.33]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [20:1.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_dpps:
; SKX: # BB#0:
@@ -1387,7 +1387,7 @@ define <4 x float> @test_extractf128(<8
; SKYLAKE-NEXT: vextractf128 $1, %ymm0, %xmm0 # sched: [3:1.00]
; SKYLAKE-NEXT: vextractf128 $1, %ymm1, (%rdi) # sched: [1:1.00]
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_extractf128:
; SKX: # BB#0:
@@ -1436,8 +1436,8 @@ define <4 x double> @test_haddpd(<4 x do
; SKYLAKE-LABEL: test_haddpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vhaddpd %ymm1, %ymm0, %ymm0 # sched: [6:2.00]
-; SKYLAKE-NEXT: vhaddpd (%rdi), %ymm0, %ymm0 # sched: [6:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vhaddpd (%rdi), %ymm0, %ymm0 # sched: [13:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_haddpd:
; SKX: # BB#0:
@@ -1485,8 +1485,8 @@ define <8 x float> @test_haddps(<8 x flo
; SKYLAKE-LABEL: test_haddps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vhaddps %ymm1, %ymm0, %ymm0 # sched: [6:2.00]
-; SKYLAKE-NEXT: vhaddps (%rdi), %ymm0, %ymm0 # sched: [6:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vhaddps (%rdi), %ymm0, %ymm0 # sched: [13:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_haddps:
; SKX: # BB#0:
@@ -1534,8 +1534,8 @@ define <4 x double> @test_hsubpd(<4 x do
; SKYLAKE-LABEL: test_hsubpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vhsubpd %ymm1, %ymm0, %ymm0 # sched: [6:2.00]
-; SKYLAKE-NEXT: vhsubpd (%rdi), %ymm0, %ymm0 # sched: [6:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vhsubpd (%rdi), %ymm0, %ymm0 # sched: [13:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_hsubpd:
; SKX: # BB#0:
@@ -1583,8 +1583,8 @@ define <8 x float> @test_hsubps(<8 x flo
; SKYLAKE-LABEL: test_hsubps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vhsubps %ymm1, %ymm0, %ymm0 # sched: [6:2.00]
-; SKYLAKE-NEXT: vhsubps (%rdi), %ymm0, %ymm0 # sched: [6:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vhsubps (%rdi), %ymm0, %ymm0 # sched: [13:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_hsubps:
; SKX: # BB#0:
@@ -1635,9 +1635,9 @@ define <8 x float> @test_insertf128(<8 x
; SKYLAKE-LABEL: test_insertf128:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1 # sched: [3:1.00]
-; SKYLAKE-NEXT: vinsertf128 $1, (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vinsertf128 $1, (%rdi), %ymm0, %ymm0 # sched: [7:0.50]
; SKYLAKE-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_insertf128:
; SKX: # BB#0:
@@ -1686,8 +1686,8 @@ define <32 x i8> @test_lddqu(i8* %a0) {
;
; SKYLAKE-LABEL: test_lddqu:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vlddqu (%rdi), %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vlddqu (%rdi), %ymm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_lddqu:
; SKX: # BB#0:
@@ -1732,10 +1732,10 @@ define <2 x double> @test_maskmovpd(i8*
;
; SKYLAKE-LABEL: test_maskmovpd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmaskmovpd (%rdi), %xmm0, %xmm2 # sched: [1:0.50]
-; SKYLAKE-NEXT: vmaskmovpd %xmm1, %xmm0, (%rdi) # sched: [1:1.00]
+; SKYLAKE-NEXT: vmaskmovpd (%rdi), %xmm0, %xmm2 # sched: [7:0.50]
+; SKYLAKE-NEXT: vmaskmovpd %xmm1, %xmm0, (%rdi) # sched: [2:1.00]
; SKYLAKE-NEXT: vmovapd %xmm2, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_maskmovpd:
; SKX: # BB#0:
@@ -1788,10 +1788,10 @@ define <4 x double> @test_maskmovpd_ymm(
;
; SKYLAKE-LABEL: test_maskmovpd_ymm:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmaskmovpd (%rdi), %ymm0, %ymm2 # sched: [1:0.50]
-; SKYLAKE-NEXT: vmaskmovpd %ymm1, %ymm0, (%rdi) # sched: [1:1.00]
+; SKYLAKE-NEXT: vmaskmovpd (%rdi), %ymm0, %ymm2 # sched: [8:0.50]
+; SKYLAKE-NEXT: vmaskmovpd %ymm1, %ymm0, (%rdi) # sched: [2:1.00]
; SKYLAKE-NEXT: vmovapd %ymm2, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_maskmovpd_ymm:
; SKX: # BB#0:
@@ -1844,10 +1844,10 @@ define <4 x float> @test_maskmovps(i8* %
;
; SKYLAKE-LABEL: test_maskmovps:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmaskmovps (%rdi), %xmm0, %xmm2 # sched: [1:0.50]
-; SKYLAKE-NEXT: vmaskmovps %xmm1, %xmm0, (%rdi) # sched: [1:1.00]
+; SKYLAKE-NEXT: vmaskmovps (%rdi), %xmm0, %xmm2 # sched: [7:0.50]
+; SKYLAKE-NEXT: vmaskmovps %xmm1, %xmm0, (%rdi) # sched: [2:1.00]
; SKYLAKE-NEXT: vmovaps %xmm2, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_maskmovps:
; SKX: # BB#0:
@@ -1900,10 +1900,10 @@ define <8 x float> @test_maskmovps_ymm(i
;
; SKYLAKE-LABEL: test_maskmovps_ymm:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmaskmovps (%rdi), %ymm0, %ymm2 # sched: [1:0.50]
-; SKYLAKE-NEXT: vmaskmovps %ymm1, %ymm0, (%rdi) # sched: [1:1.00]
+; SKYLAKE-NEXT: vmaskmovps (%rdi), %ymm0, %ymm2 # sched: [8:0.50]
+; SKYLAKE-NEXT: vmaskmovps %ymm1, %ymm0, (%rdi) # sched: [2:1.00]
; SKYLAKE-NEXT: vmovaps %ymm2, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_maskmovps_ymm:
; SKX: # BB#0:
@@ -1954,8 +1954,8 @@ define <4 x double> @test_maxpd(<4 x dou
; SKYLAKE-LABEL: test_maxpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmaxpd %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vmaxpd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vmaxpd (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_maxpd:
; SKX: # BB#0:
@@ -2003,8 +2003,8 @@ define <8 x float> @test_maxps(<8 x floa
; SKYLAKE-LABEL: test_maxps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmaxps %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vmaxps (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vmaxps (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_maxps:
; SKX: # BB#0:
@@ -2052,8 +2052,8 @@ define <4 x double> @test_minpd(<4 x dou
; SKYLAKE-LABEL: test_minpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vminpd %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vminpd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vminpd (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_minpd:
; SKX: # BB#0:
@@ -2101,8 +2101,8 @@ define <8 x float> @test_minps(<8 x floa
; SKYLAKE-LABEL: test_minps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vminps %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vminps (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vminps (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_minps:
; SKX: # BB#0:
@@ -2152,10 +2152,10 @@ define <4 x double> @test_movapd(<4 x do
;
; SKYLAKE-LABEL: test_movapd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmovapd (%rdi), %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vmovapd (%rdi), %ymm0 # sched: [7:0.50]
; SKYLAKE-NEXT: vaddpd %ymm0, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmovapd %ymm0, (%rsi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movapd:
; SKX: # BB#0:
@@ -2207,10 +2207,10 @@ define <8 x float> @test_movaps(<8 x flo
;
; SKYLAKE-LABEL: test_movaps:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmovaps (%rdi), %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vmovaps (%rdi), %ymm0 # sched: [7:0.50]
; SKYLAKE-NEXT: vaddps %ymm0, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmovaps %ymm0, (%rsi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movaps:
; SKX: # BB#0:
@@ -2263,9 +2263,9 @@ define <4 x double> @test_movddup(<4 x d
; SKYLAKE-LABEL: test_movddup:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2] sched: [1:1.00]
-; SKYLAKE-NEXT: vmovddup {{.*#+}} ymm1 = mem[0,0,2,2] sched: [1:0.50]
+; SKYLAKE-NEXT: vmovddup {{.*#+}} ymm1 = mem[0,0,2,2] sched: [7:0.50]
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movddup:
; SKX: # BB#0:
@@ -2317,7 +2317,7 @@ define i32 @test_movmskpd(<4 x double> %
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmovmskpd %ymm0, %eax # sched: [2:1.00]
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movmskpd:
; SKX: # BB#0:
@@ -2363,7 +2363,7 @@ define i32 @test_movmskps(<8 x float> %a
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmovmskps %ymm0, %eax # sched: [2:1.00]
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movmskps:
; SKX: # BB#0:
@@ -2409,7 +2409,7 @@ define <4 x double> @test_movntpd(<4 x d
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vaddpd %ymm0, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmovntpd %ymm0, (%rdi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movntpd:
; SKX: # BB#0:
@@ -2456,7 +2456,7 @@ define <8 x float> @test_movntps(<8 x fl
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vaddps %ymm0, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmovntps %ymm0, (%rdi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movntps:
; SKX: # BB#0:
@@ -2505,9 +2505,9 @@ define <8 x float> @test_movshdup(<8 x f
; SKYLAKE-LABEL: test_movshdup:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7] sched: [1:1.00]
-; SKYLAKE-NEXT: vmovshdup {{.*#+}} ymm1 = mem[1,1,3,3,5,5,7,7] sched: [1:0.50]
+; SKYLAKE-NEXT: vmovshdup {{.*#+}} ymm1 = mem[1,1,3,3,5,5,7,7] sched: [7:0.50]
; SKYLAKE-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movshdup:
; SKX: # BB#0:
@@ -2561,9 +2561,9 @@ define <8 x float> @test_movsldup(<8 x f
; SKYLAKE-LABEL: test_movsldup:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6] sched: [1:1.00]
-; SKYLAKE-NEXT: vmovsldup {{.*#+}} ymm1 = mem[0,0,2,2,4,4,6,6] sched: [1:0.50]
+; SKYLAKE-NEXT: vmovsldup {{.*#+}} ymm1 = mem[0,0,2,2,4,4,6,6] sched: [7:0.50]
; SKYLAKE-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movsldup:
; SKX: # BB#0:
@@ -2618,10 +2618,10 @@ define <4 x double> @test_movupd(<4 x do
;
; SKYLAKE-LABEL: test_movupd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmovupd (%rdi), %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vmovupd (%rdi), %ymm0 # sched: [7:0.50]
; SKYLAKE-NEXT: vaddpd %ymm0, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmovupd %ymm0, (%rsi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movupd:
; SKX: # BB#0:
@@ -2675,10 +2675,10 @@ define <8 x float> @test_movups(<8 x flo
;
; SKYLAKE-LABEL: test_movups:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmovups (%rdi), %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vmovups (%rdi), %ymm0 # sched: [7:0.50]
; SKYLAKE-NEXT: vaddps %ymm0, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmovups %ymm0, (%rsi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movups:
; SKX: # BB#0:
@@ -2728,8 +2728,8 @@ define <4 x double> @test_mulpd(<4 x dou
; SKYLAKE-LABEL: test_mulpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmulpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vmulpd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vmulpd (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_mulpd:
; SKX: # BB#0:
@@ -2776,8 +2776,8 @@ define <8 x float> @test_mulps(<8 x floa
; SKYLAKE-LABEL: test_mulps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmulps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vmulps (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vmulps (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_mulps:
; SKX: # BB#0:
@@ -2826,10 +2826,10 @@ define <4 x double> @orpd(<4 x double> %
;
; SKYLAKE-LABEL: orpd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vorpd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vorpd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vorpd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vorpd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
; SKYLAKE-NEXT: vaddpd %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: orpd:
; SKX: # BB#0:
@@ -2886,10 +2886,10 @@ define <8 x float> @test_orps(<8 x float
;
; SKYLAKE-LABEL: test_orps:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vorps %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vorps (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vorps %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vorps (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
; SKYLAKE-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_orps:
; SKX: # BB#0:
@@ -2947,9 +2947,9 @@ define <4 x double> @test_perm2f128(<4 x
; SKYLAKE-LABEL: test_perm2f128:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[0,1] sched: [3:1.00]
-; SKYLAKE-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],mem[0,1] sched: [3:1.00]
+; SKYLAKE-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],mem[0,1] sched: [10:1.00]
; SKYLAKE-NEXT: vaddpd %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_perm2f128:
; SKX: # BB#0:
@@ -3003,9 +3003,9 @@ define <2 x double> @test_permilpd(<2 x
; SKYLAKE-LABEL: test_permilpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] sched: [1:1.00]
-; SKYLAKE-NEXT: vpermilpd {{.*#+}} xmm1 = mem[1,0] sched: [1:1.00]
+; SKYLAKE-NEXT: vpermilpd {{.*#+}} xmm1 = mem[1,0] sched: [7:1.00]
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_permilpd:
; SKX: # BB#0:
@@ -3059,9 +3059,9 @@ define <4 x double> @test_permilpd_ymm(<
; SKYLAKE-LABEL: test_permilpd_ymm:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,0,2,3] sched: [1:1.00]
-; SKYLAKE-NEXT: vpermilpd {{.*#+}} ymm1 = mem[1,0,2,3] sched: [1:1.00]
+; SKYLAKE-NEXT: vpermilpd {{.*#+}} ymm1 = mem[1,0,2,3] sched: [8:1.00]
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_permilpd_ymm:
; SKX: # BB#0:
@@ -3115,9 +3115,9 @@ define <4 x float> @test_permilps(<4 x f
; SKYLAKE-LABEL: test_permilps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0] sched: [1:1.00]
-; SKYLAKE-NEXT: vpermilps {{.*#+}} xmm1 = mem[3,2,1,0] sched: [1:1.00]
+; SKYLAKE-NEXT: vpermilps {{.*#+}} xmm1 = mem[3,2,1,0] sched: [7:1.00]
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_permilps:
; SKX: # BB#0:
@@ -3171,9 +3171,9 @@ define <8 x float> @test_permilps_ymm(<8
; SKYLAKE-LABEL: test_permilps_ymm:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4] sched: [1:1.00]
-; SKYLAKE-NEXT: vpermilps {{.*#+}} ymm1 = mem[3,2,1,0,7,6,5,4] sched: [1:1.00]
+; SKYLAKE-NEXT: vpermilps {{.*#+}} ymm1 = mem[3,2,1,0,7,6,5,4] sched: [8:1.00]
; SKYLAKE-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_permilps_ymm:
; SKX: # BB#0:
@@ -3224,8 +3224,8 @@ define <2 x double> @test_permilvarpd(<2
; SKYLAKE-LABEL: test_permilvarpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpermilpd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpermilpd (%rdi), %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpermilpd (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_permilvarpd:
; SKX: # BB#0:
@@ -3273,8 +3273,8 @@ define <4 x double> @test_permilvarpd_ym
; SKYLAKE-LABEL: test_permilvarpd_ymm:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpermilpd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpermilpd (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpermilpd (%rdi), %ymm0, %ymm0 # sched: [8:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_permilvarpd_ymm:
; SKX: # BB#0:
@@ -3322,8 +3322,8 @@ define <4 x float> @test_permilvarps(<4
; SKYLAKE-LABEL: test_permilvarps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpermilps %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpermilps (%rdi), %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpermilps (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_permilvarps:
; SKX: # BB#0:
@@ -3371,8 +3371,8 @@ define <8 x float> @test_permilvarps_ymm
; SKYLAKE-LABEL: test_permilvarps_ymm:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpermilps %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpermilps (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpermilps (%rdi), %ymm0, %ymm0 # sched: [8:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_permilvarps_ymm:
; SKX: # BB#0:
@@ -3423,9 +3423,9 @@ define <8 x float> @test_rcpps(<8 x floa
; SKYLAKE-LABEL: test_rcpps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vrcpps %ymm0, %ymm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: vrcpps (%rdi), %ymm1 # sched: [4:1.00]
+; SKYLAKE-NEXT: vrcpps (%rdi), %ymm1 # sched: [11:1.00]
; SKYLAKE-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_rcpps:
; SKX: # BB#0:
@@ -3480,9 +3480,9 @@ define <4 x double> @test_roundpd(<4 x d
; SKYLAKE-LABEL: test_roundpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vroundpd $7, %ymm0, %ymm0 # sched: [8:0.67]
-; SKYLAKE-NEXT: vroundpd $7, (%rdi), %ymm1 # sched: [8:0.67]
+; SKYLAKE-NEXT: vroundpd $7, (%rdi), %ymm1 # sched: [15:0.67]
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_roundpd:
; SKX: # BB#0:
@@ -3537,9 +3537,9 @@ define <8 x float> @test_roundps(<8 x fl
; SKYLAKE-LABEL: test_roundps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vroundps $7, %ymm0, %ymm0 # sched: [8:0.67]
-; SKYLAKE-NEXT: vroundps $7, (%rdi), %ymm1 # sched: [8:0.67]
+; SKYLAKE-NEXT: vroundps $7, (%rdi), %ymm1 # sched: [15:0.67]
; SKYLAKE-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_roundps:
; SKX: # BB#0:
@@ -3594,9 +3594,9 @@ define <8 x float> @test_rsqrtps(<8 x fl
; SKYLAKE-LABEL: test_rsqrtps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vrsqrtps %ymm0, %ymm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: vrsqrtps (%rdi), %ymm1 # sched: [4:1.00]
+; SKYLAKE-NEXT: vrsqrtps (%rdi), %ymm1 # sched: [11:1.00]
; SKYLAKE-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_rsqrtps:
; SKX: # BB#0:
@@ -3651,9 +3651,9 @@ define <4 x double> @test_shufpd(<4 x do
; SKYLAKE-LABEL: test_shufpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vshufpd {{.*#+}} ymm0 = ymm0[1],ymm1[0],ymm0[2],ymm1[3] sched: [1:1.00]
-; SKYLAKE-NEXT: vshufpd {{.*#+}} ymm1 = ymm1[1],mem[0],ymm1[2],mem[3] sched: [1:1.00]
+; SKYLAKE-NEXT: vshufpd {{.*#+}} ymm1 = ymm1[1],mem[0],ymm1[2],mem[3] sched: [8:1.00]
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_shufpd:
; SKX: # BB#0:
@@ -3704,8 +3704,8 @@ define <8 x float> @test_shufps(<8 x flo
; SKYLAKE-LABEL: test_shufps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,0],ymm1[0,0],ymm0[4,4],ymm1[4,4] sched: [1:1.00]
-; SKYLAKE-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,3],mem[0,0],ymm0[4,7],mem[4,4] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,3],mem[0,0],ymm0[4,7],mem[4,4] sched: [8:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_shufps:
; SKX: # BB#0:
@@ -3755,9 +3755,9 @@ define <4 x double> @test_sqrtpd(<4 x do
; SKYLAKE-LABEL: test_sqrtpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vsqrtpd %ymm0, %ymm0 # sched: [18:1.00]
-; SKYLAKE-NEXT: vsqrtpd (%rdi), %ymm1 # sched: [18:1.00]
+; SKYLAKE-NEXT: vsqrtpd (%rdi), %ymm1 # sched: [25:1.00]
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_sqrtpd:
; SKX: # BB#0:
@@ -3812,9 +3812,9 @@ define <8 x float> @test_sqrtps(<8 x flo
; SKYLAKE-LABEL: test_sqrtps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vsqrtps %ymm0, %ymm0 # sched: [12:1.00]
-; SKYLAKE-NEXT: vsqrtps (%rdi), %ymm1 # sched: [12:1.00]
+; SKYLAKE-NEXT: vsqrtps (%rdi), %ymm1 # sched: [19:1.00]
; SKYLAKE-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_sqrtps:
; SKX: # BB#0:
@@ -3866,8 +3866,8 @@ define <4 x double> @test_subpd(<4 x dou
; SKYLAKE-LABEL: test_subpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vsubpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vsubpd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vsubpd (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_subpd:
; SKX: # BB#0:
@@ -3914,8 +3914,8 @@ define <8 x float> @test_subps(<8 x floa
; SKYLAKE-LABEL: test_subps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vsubps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vsubps (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vsubps (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_subps:
; SKX: # BB#0:
@@ -3972,10 +3972,10 @@ define i32 @test_testpd(<2 x double> %a0
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: xorl %eax, %eax # sched: [1:0.25]
; SKYLAKE-NEXT: vtestpd %xmm1, %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT: setb %al # sched: [1:1.00]
-; SKYLAKE-NEXT: vtestpd (%rdi), %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT: adcl $0, %eax # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: setb %al # sched: [1:0.50]
+; SKYLAKE-NEXT: vtestpd (%rdi), %xmm0 # sched: [8:1.00]
+; SKYLAKE-NEXT: adcl $0, %eax # sched: [1:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_testpd:
; SKX: # BB#0:
@@ -4046,11 +4046,11 @@ define i32 @test_testpd_ymm(<4 x double>
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: xorl %eax, %eax # sched: [1:0.25]
; SKYLAKE-NEXT: vtestpd %ymm1, %ymm0 # sched: [2:1.00]
-; SKYLAKE-NEXT: setb %al # sched: [1:1.00]
-; SKYLAKE-NEXT: vtestpd (%rdi), %ymm0 # sched: [2:1.00]
-; SKYLAKE-NEXT: adcl $0, %eax # sched: [1:1.00]
+; SKYLAKE-NEXT: setb %al # sched: [1:0.50]
+; SKYLAKE-NEXT: vtestpd (%rdi), %ymm0 # sched: [9:1.00]
+; SKYLAKE-NEXT: adcl $0, %eax # sched: [1:0.50]
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_testpd_ymm:
; SKX: # BB#0:
@@ -4120,10 +4120,10 @@ define i32 @test_testps(<4 x float> %a0,
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: xorl %eax, %eax # sched: [1:0.25]
; SKYLAKE-NEXT: vtestps %xmm1, %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT: setb %al # sched: [1:1.00]
-; SKYLAKE-NEXT: vtestps (%rdi), %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT: adcl $0, %eax # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: setb %al # sched: [1:0.50]
+; SKYLAKE-NEXT: vtestps (%rdi), %xmm0 # sched: [8:1.00]
+; SKYLAKE-NEXT: adcl $0, %eax # sched: [1:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_testps:
; SKX: # BB#0:
@@ -4194,11 +4194,11 @@ define i32 @test_testps_ymm(<8 x float>
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: xorl %eax, %eax # sched: [1:0.25]
; SKYLAKE-NEXT: vtestps %ymm1, %ymm0 # sched: [2:1.00]
-; SKYLAKE-NEXT: setb %al # sched: [1:1.00]
-; SKYLAKE-NEXT: vtestps (%rdi), %ymm0 # sched: [2:1.00]
-; SKYLAKE-NEXT: adcl $0, %eax # sched: [1:1.00]
+; SKYLAKE-NEXT: setb %al # sched: [1:0.50]
+; SKYLAKE-NEXT: vtestps (%rdi), %ymm0 # sched: [9:1.00]
+; SKYLAKE-NEXT: adcl $0, %eax # sched: [1:0.50]
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_testps_ymm:
; SKX: # BB#0:
@@ -4261,9 +4261,9 @@ define <4 x double> @test_unpckhpd(<4 x
; SKYLAKE-LABEL: test_unpckhpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vunpckhpd {{.*#+}} ymm0 = ymm0[1],ymm1[1],ymm0[3],ymm1[3] sched: [1:1.00]
-; SKYLAKE-NEXT: vunpckhpd {{.*#+}} ymm1 = ymm1[1],mem[1],ymm1[3],mem[3] sched: [1:1.00]
+; SKYLAKE-NEXT: vunpckhpd {{.*#+}} ymm1 = ymm1[1],mem[1],ymm1[3],mem[3] sched: [8:1.00]
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_unpckhpd:
; SKX: # BB#0:
@@ -4314,8 +4314,8 @@ define <8 x float> @test_unpckhps(<8 x f
; SKYLAKE-LABEL: test_unpckhps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vunpckhps {{.*#+}} ymm0 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7] sched: [1:1.00]
-; SKYLAKE-NEXT: vunpckhps {{.*#+}} ymm0 = ymm0[2],mem[2],ymm0[3],mem[3],ymm0[6],mem[6],ymm0[7],mem[7] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vunpckhps {{.*#+}} ymm0 = ymm0[2],mem[2],ymm0[3],mem[3],ymm0[6],mem[6],ymm0[7],mem[7] sched: [8:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_unpckhps:
; SKX: # BB#0:
@@ -4365,9 +4365,9 @@ define <4 x double> @test_unpcklpd(<4 x
; SKYLAKE-LABEL: test_unpcklpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2] sched: [1:1.00]
-; SKYLAKE-NEXT: vunpcklpd {{.*#+}} ymm1 = ymm1[0],mem[0],ymm1[2],mem[2] sched: [1:1.00]
+; SKYLAKE-NEXT: vunpcklpd {{.*#+}} ymm1 = ymm1[0],mem[0],ymm1[2],mem[2] sched: [8:1.00]
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_unpcklpd:
; SKX: # BB#0:
@@ -4418,8 +4418,8 @@ define <8 x float> @test_unpcklps(<8 x f
; SKYLAKE-LABEL: test_unpcklps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vunpcklps {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] sched: [1:1.00]
-; SKYLAKE-NEXT: vunpcklps {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[4],mem[4],ymm0[5],mem[5] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vunpcklps {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[4],mem[4],ymm0[5],mem[5] sched: [8:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_unpcklps:
; SKX: # BB#0:
@@ -4468,10 +4468,10 @@ define <4 x double> @test_xorpd(<4 x dou
;
; SKYLAKE-LABEL: test_xorpd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vxorpd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vxorpd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vxorpd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vxorpd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
; SKYLAKE-NEXT: vaddpd %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_xorpd:
; SKX: # BB#0:
@@ -4528,10 +4528,10 @@ define <8 x float> @test_xorps(<8 x floa
;
; SKYLAKE-LABEL: test_xorps:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vxorps %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vxorps (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vxorps %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vxorps (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
; SKYLAKE-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_xorps:
; SKX: # BB#0:
@@ -4583,7 +4583,7 @@ define void @test_zeroall() {
; SKYLAKE-LABEL: test_zeroall:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vzeroall # sched: [16:4.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_zeroall:
; SKX: # BB#0:
@@ -4623,7 +4623,7 @@ define void @test_zeroupper() {
; SKYLAKE-LABEL: test_zeroupper:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_zeroupper:
; SKX: # BB#0:
Modified: llvm/trunk/test/CodeGen/X86/avx2-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-schedule.ll Mon Oct 16 23:47:04 2017
@@ -20,9 +20,9 @@ define <8 x i32> @test_broadcasti128(<8
;
; SKYLAKE-LABEL: test_broadcasti128:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1] sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddd %ymm0, %ymm1, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1] sched: [7:0.50]
+; SKYLAKE-NEXT: vpaddd %ymm0, %ymm1, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_broadcasti128:
; SKX: # BB#0:
@@ -58,7 +58,7 @@ define <4 x double> @test_broadcastsd_ym
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vbroadcastsd %xmm0, %ymm0 # sched: [3:1.00]
; SKYLAKE-NEXT: vaddpd %ymm0, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_broadcastsd_ymm:
; SKX: # BB#0:
@@ -93,7 +93,7 @@ define <4 x float> @test_broadcastss(<4
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vbroadcastss %xmm0, %xmm0 # sched: [1:1.00]
; SKYLAKE-NEXT: vaddps %xmm0, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_broadcastss:
; SKX: # BB#0:
@@ -128,7 +128,7 @@ define <8 x float> @test_broadcastss_ymm
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vbroadcastss %xmm0, %ymm0 # sched: [3:1.00]
; SKYLAKE-NEXT: vaddps %ymm0, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_broadcastss_ymm:
; SKX: # BB#0:
@@ -167,12 +167,12 @@ define <4 x i32> @test_extracti128(<8 x
;
; SKYLAKE-LABEL: test_extracti128:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm2 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm2 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
; SKYLAKE-NEXT: vextracti128 $1, %ymm0, %xmm0 # sched: [3:1.00]
; SKYLAKE-NEXT: vextracti128 $1, %ymm2, (%rdi) # sched: [1:1.00]
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_extracti128:
; SKX: # BB#0:
@@ -212,8 +212,8 @@ define <2 x double> @test_gatherdpd(<2 x
;
; SKYLAKE-LABEL: test_gatherdpd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vgatherdpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vgatherdpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_gatherdpd:
; SKX: # BB#0:
@@ -242,8 +242,8 @@ define <4 x double> @test_gatherdpd_ymm(
;
; SKYLAKE-LABEL: test_gatherdpd_ymm:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vgatherdpd %ymm2, (%rdi,%xmm1,8), %ymm0 # sched: [20:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vgatherdpd %ymm2, (%rdi,%xmm1,8), %ymm0 # sched: [25:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_gatherdpd_ymm:
; SKX: # BB#0:
@@ -272,8 +272,8 @@ define <4 x float> @test_gatherdps(<4 x
;
; SKYLAKE-LABEL: test_gatherdps:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vgatherdps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vgatherdps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_gatherdps:
; SKX: # BB#0:
@@ -302,8 +302,8 @@ define <8 x float> @test_gatherdps_ymm(<
;
; SKYLAKE-LABEL: test_gatherdps_ymm:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vgatherdps %ymm2, (%rdi,%ymm1,4), %ymm0 # sched: [20:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vgatherdps %ymm2, (%rdi,%ymm1,4), %ymm0 # sched: [25:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_gatherdps_ymm:
; SKX: # BB#0:
@@ -332,8 +332,8 @@ define <2 x double> @test_gatherqpd(<2 x
;
; SKYLAKE-LABEL: test_gatherqpd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vgatherqpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vgatherqpd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_gatherqpd:
; SKX: # BB#0:
@@ -362,8 +362,8 @@ define <4 x double> @test_gatherqpd_ymm(
;
; SKYLAKE-LABEL: test_gatherqpd_ymm:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vgatherqpd %ymm2, (%rdi,%ymm1,8), %ymm0 # sched: [20:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vgatherqpd %ymm2, (%rdi,%ymm1,8), %ymm0 # sched: [25:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_gatherqpd_ymm:
; SKX: # BB#0:
@@ -392,8 +392,8 @@ define <4 x float> @test_gatherqps(<4 x
;
; SKYLAKE-LABEL: test_gatherqps:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vgatherqps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vgatherqps %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_gatherqps:
; SKX: # BB#0:
@@ -424,9 +424,9 @@ define <4 x float> @test_gatherqps_ymm(<
;
; SKYLAKE-LABEL: test_gatherqps_ymm:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vgatherqps %xmm2, (%rdi,%ymm1,4), %xmm0 # sched: [20:1.00]
+; SKYLAKE-NEXT: vgatherqps %xmm2, (%rdi,%ymm1,4), %xmm0 # sched: [25:1.00]
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_gatherqps_ymm:
; SKX: # BB#0:
@@ -462,9 +462,9 @@ define <8 x i32> @test_inserti128(<8 x i
; SKYLAKE-LABEL: test_inserti128:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm1 # sched: [3:1.00]
-; SKYLAKE-NEXT: vinserti128 $1, (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddd %ymm0, %ymm1, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vinserti128 $1, (%rdi), %ymm0, %ymm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpaddd %ymm0, %ymm1, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_inserti128:
; SKX: # BB#0:
@@ -501,8 +501,8 @@ define <4 x i64> @test_movntdqa(i8* %a0)
;
; SKYLAKE-LABEL: test_movntdqa:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmovntdqa (%rdi), %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vmovntdqa (%rdi), %ymm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movntdqa:
; SKX: # BB#0:
@@ -534,8 +534,8 @@ define <16 x i16> @test_mpsadbw(<32 x i8
; SKYLAKE-LABEL: test_mpsadbw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmpsadbw $7, %ymm1, %ymm0, %ymm0 # sched: [4:2.00]
-; SKYLAKE-NEXT: vmpsadbw $7, (%rdi), %ymm0, %ymm0 # sched: [4:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vmpsadbw $7, (%rdi), %ymm0, %ymm0 # sched: [11:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_mpsadbw:
; SKX: # BB#0:
@@ -573,10 +573,10 @@ define <32 x i8> @test_pabsb(<32 x i8> %
;
; SKYLAKE-LABEL: test_pabsb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpabsb %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpabsb (%rdi), %ymm1 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpabsb %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpabsb (%rdi), %ymm1 # sched: [8:0.50]
+; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pabsb:
; SKX: # BB#0:
@@ -616,10 +616,10 @@ define <8 x i32> @test_pabsd(<8 x i32> %
;
; SKYLAKE-LABEL: test_pabsd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpabsd %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpabsd (%rdi), %ymm1 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpabsd %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpabsd (%rdi), %ymm1 # sched: [8:0.50]
+; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pabsd:
; SKX: # BB#0:
@@ -659,10 +659,10 @@ define <16 x i16> @test_pabsw(<16 x i16>
;
; SKYLAKE-LABEL: test_pabsw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpabsw %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpabsw (%rdi), %ymm1 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpabsw %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpabsw (%rdi), %ymm1 # sched: [8:0.50]
+; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pabsw:
; SKX: # BB#0:
@@ -701,8 +701,8 @@ define <16 x i16> @test_packssdw(<8 x i3
; SKYLAKE-LABEL: test_packssdw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpackssdw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpackssdw (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpackssdw (%rdi), %ymm0, %ymm0 # sched: [8:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_packssdw:
; SKX: # BB#0:
@@ -739,8 +739,8 @@ define <32 x i8> @test_packsswb(<16 x i1
; SKYLAKE-LABEL: test_packsswb:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpacksswb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpacksswb (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpacksswb (%rdi), %ymm0, %ymm0 # sched: [8:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_packsswb:
; SKX: # BB#0:
@@ -777,8 +777,8 @@ define <16 x i16> @test_packusdw(<8 x i3
; SKYLAKE-LABEL: test_packusdw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpackusdw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpackusdw (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpackusdw (%rdi), %ymm0, %ymm0 # sched: [8:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_packusdw:
; SKX: # BB#0:
@@ -815,8 +815,8 @@ define <32 x i8> @test_packuswb(<16 x i1
; SKYLAKE-LABEL: test_packuswb:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpackuswb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpackuswb (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpackuswb (%rdi), %ymm0, %ymm0 # sched: [8:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_packuswb:
; SKX: # BB#0:
@@ -852,9 +852,9 @@ define <32 x i8> @test_paddb(<32 x i8> %
;
; SKYLAKE-LABEL: test_paddb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpaddb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpaddb %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpaddb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_paddb:
; SKX: # BB#0:
@@ -888,9 +888,9 @@ define <8 x i32> @test_paddd(<8 x i32> %
;
; SKYLAKE-LABEL: test_paddd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpaddd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_paddd:
; SKX: # BB#0:
@@ -924,9 +924,9 @@ define <4 x i64> @test_paddq(<4 x i64> %
;
; SKYLAKE-LABEL: test_paddq:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpaddq (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_paddq:
; SKX: # BB#0:
@@ -960,9 +960,9 @@ define <32 x i8> @test_paddsb(<32 x i8>
;
; SKYLAKE-LABEL: test_paddsb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpaddsb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddsb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpaddsb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpaddsb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_paddsb:
; SKX: # BB#0:
@@ -997,9 +997,9 @@ define <16 x i16> @test_paddsw(<16 x i16
;
; SKYLAKE-LABEL: test_paddsw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpaddsw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddsw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpaddsw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpaddsw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_paddsw:
; SKX: # BB#0:
@@ -1034,9 +1034,9 @@ define <32 x i8> @test_paddusb(<32 x i8>
;
; SKYLAKE-LABEL: test_paddusb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpaddusb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddusb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpaddusb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpaddusb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_paddusb:
; SKX: # BB#0:
@@ -1071,9 +1071,9 @@ define <16 x i16> @test_paddusw(<16 x i1
;
; SKYLAKE-LABEL: test_paddusw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpaddusw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddusw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpaddusw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpaddusw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_paddusw:
; SKX: # BB#0:
@@ -1108,9 +1108,9 @@ define <16 x i16> @test_paddw(<16 x i16>
;
; SKYLAKE-LABEL: test_paddw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpaddw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpaddw %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpaddw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_paddw:
; SKX: # BB#0:
@@ -1145,8 +1145,8 @@ define <32 x i8> @test_palignr(<32 x i8>
; SKYLAKE-LABEL: test_palignr:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpalignr {{.*#+}} ymm0 = ymm1[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm0[0],ymm1[17,18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm0[16] sched: [1:1.00]
-; SKYLAKE-NEXT: vpalignr {{.*#+}} ymm0 = mem[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm0[0],mem[17,18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm0[16] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpalignr {{.*#+}} ymm0 = mem[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],ymm0[0],mem[17,18,19,20,21,22,23,24,25,26,27,28,29,30,31],ymm0[16] sched: [8:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_palignr:
; SKX: # BB#0:
@@ -1182,10 +1182,10 @@ define <4 x i64> @test_pand(<4 x i64> %a
;
; SKYLAKE-LABEL: test_pand:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpand %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpand (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpand %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpand (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pand:
; SKX: # BB#0:
@@ -1224,10 +1224,10 @@ define <4 x i64> @test_pandn(<4 x i64> %
;
; SKYLAKE-LABEL: test_pandn:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpandn %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpandn (%rdi), %ymm0, %ymm1 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpandn %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpandn (%rdi), %ymm0, %ymm1 # sched: [8:0.50]
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pandn:
; SKX: # BB#0:
@@ -1266,9 +1266,9 @@ define <32 x i8> @test_pavgb(<32 x i8> %
;
; SKYLAKE-LABEL: test_pavgb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpavgb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpavgb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpavgb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpavgb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pavgb:
; SKX: # BB#0:
@@ -1312,9 +1312,9 @@ define <16 x i16> @test_pavgw(<16 x i16>
;
; SKYLAKE-LABEL: test_pavgw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpavgw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpavgw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpavgw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpavgw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pavgw:
; SKX: # BB#0:
@@ -1360,10 +1360,10 @@ define <4 x i32> @test_pblendd(<4 x i32>
;
; SKYLAKE-LABEL: test_pblendd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[3] sched: [1:0.50]
-; SKYLAKE-NEXT: vpblendd {{.*#+}} xmm1 = mem[0],xmm1[1],mem[2],xmm1[3] sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[3] sched: [1:0.33]
+; SKYLAKE-NEXT: vpblendd {{.*#+}} xmm1 = mem[0],xmm1[1],mem[2],xmm1[3] sched: [7:0.50]
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pblendd:
; SKX: # BB#0:
@@ -1402,10 +1402,10 @@ define <8 x i32> @test_pblendd_ymm(<8 x
;
; SKYLAKE-LABEL: test_pblendd_ymm:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2],ymm0[3,4,5,6],ymm1[7] sched: [1:0.50]
-; SKYLAKE-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0],mem[1,2],ymm1[3,4,5,6,7] sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2],ymm0[3,4,5,6],ymm1[7] sched: [1:0.33]
+; SKYLAKE-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0],mem[1,2],ymm1[3,4,5,6,7] sched: [8:0.50]
+; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pblendd_ymm:
; SKX: # BB#0:
@@ -1443,8 +1443,8 @@ define <32 x i8> @test_pblendvb(<32 x i8
; SKYLAKE-LABEL: test_pblendvb:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0 # sched: [2:0.67]
-; SKYLAKE-NEXT: vpblendvb %ymm3, (%rdi), %ymm0, %ymm0 # sched: [2:0.67]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpblendvb %ymm3, (%rdi), %ymm0, %ymm0 # sched: [8:0.67]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pblendvb:
; SKX: # BB#0:
@@ -1480,8 +1480,8 @@ define <16 x i16> @test_pblendw(<16 x i1
; SKYLAKE-LABEL: test_pblendw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4],ymm0[5,6,7,8,9],ymm1[10,11,12],ymm0[13,14,15] sched: [1:1.00]
-; SKYLAKE-NEXT: vpblendw {{.*#+}} ymm0 = mem[0],ymm0[1],mem[2],ymm0[3],mem[4],ymm0[5],mem[6],ymm0[7],mem[8],ymm0[9],mem[10],ymm0[11],mem[12],ymm0[13],mem[14],ymm0[15] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpblendw {{.*#+}} ymm0 = mem[0],ymm0[1],mem[2],ymm0[3],mem[4],ymm0[5],mem[6],ymm0[7],mem[8],ymm0[9],mem[10],ymm0[11],mem[12],ymm0[13],mem[14],ymm0[15] sched: [8:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pblendw:
; SKX: # BB#0:
@@ -1518,9 +1518,9 @@ define <16 x i8> @test_pbroadcastb(<16 x
; SKYLAKE-LABEL: test_pbroadcastb:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpbroadcastb %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpbroadcastb (%rdi), %xmm1 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpbroadcastb (%rdi), %xmm1 # sched: [7:1.00]
+; SKYLAKE-NEXT: vpaddb %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pbroadcastb:
; SKX: # BB#0:
@@ -1560,9 +1560,9 @@ define <32 x i8> @test_pbroadcastb_ymm(<
; SKYLAKE-LABEL: test_pbroadcastb_ymm:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpbroadcastb %xmm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpbroadcastb (%rdi), %ymm1 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpbroadcastb (%rdi), %ymm1 # sched: [8:1.00]
+; SKYLAKE-NEXT: vpaddb %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pbroadcastb_ymm:
; SKX: # BB#0:
@@ -1602,9 +1602,9 @@ define <4 x i32> @test_pbroadcastd(<4 x
; SKYLAKE-LABEL: test_pbroadcastd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpbroadcastd %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpbroadcastd (%rdi), %xmm1 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpbroadcastd (%rdi), %xmm1 # sched: [6:0.50]
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pbroadcastd:
; SKX: # BB#0:
@@ -1643,9 +1643,9 @@ define <8 x i32> @test_pbroadcastd_ymm(<
; SKYLAKE-LABEL: test_pbroadcastd_ymm:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpbroadcastd %xmm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpbroadcastd (%rdi), %ymm1 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpbroadcastd (%rdi), %ymm1 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pbroadcastd_ymm:
; SKX: # BB#0:
@@ -1684,9 +1684,9 @@ define <2 x i64> @test_pbroadcastq(<2 x
; SKYLAKE-LABEL: test_pbroadcastq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpbroadcastq %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpbroadcastq (%rdi), %xmm1 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpbroadcastq (%rdi), %xmm1 # sched: [6:0.50]
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pbroadcastq:
; SKX: # BB#0:
@@ -1725,9 +1725,9 @@ define <4 x i64> @test_pbroadcastq_ymm(<
; SKYLAKE-LABEL: test_pbroadcastq_ymm:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpbroadcastq %xmm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpbroadcastq (%rdi), %ymm1 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpbroadcastq (%rdi), %ymm1 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pbroadcastq_ymm:
; SKX: # BB#0:
@@ -1766,9 +1766,9 @@ define <8 x i16> @test_pbroadcastw(<8 x
; SKYLAKE-LABEL: test_pbroadcastw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpbroadcastw %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpbroadcastw (%rdi), %xmm1 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpbroadcastw (%rdi), %xmm1 # sched: [7:1.00]
+; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pbroadcastw:
; SKX: # BB#0:
@@ -1808,9 +1808,9 @@ define <16 x i16> @test_pbroadcastw_ymm(
; SKYLAKE-LABEL: test_pbroadcastw_ymm:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpbroadcastw %xmm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpbroadcastw (%rdi), %ymm1 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpbroadcastw (%rdi), %ymm1 # sched: [8:1.00]
+; SKYLAKE-NEXT: vpaddw %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pbroadcastw_ymm:
; SKX: # BB#0:
@@ -1847,9 +1847,9 @@ define <32 x i8> @test_pcmpeqb(<32 x i8>
;
; SKYLAKE-LABEL: test_pcmpeqb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpcmpeqb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpcmpeqb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pcmpeqb:
; SKX: # BB#0:
@@ -1887,9 +1887,9 @@ define <8 x i32> @test_pcmpeqd(<8 x i32>
;
; SKYLAKE-LABEL: test_pcmpeqd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpcmpeqd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpcmpeqd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpcmpeqd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpcmpeqd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pcmpeqd:
; SKX: # BB#0:
@@ -1927,9 +1927,9 @@ define <4 x i64> @test_pcmpeqq(<4 x i64>
;
; SKYLAKE-LABEL: test_pcmpeqq:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpcmpeqq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpcmpeqq (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pcmpeqq:
; SKX: # BB#0:
@@ -1967,9 +1967,9 @@ define <16 x i16> @test_pcmpeqw(<16 x i1
;
; SKYLAKE-LABEL: test_pcmpeqw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpcmpeqw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpcmpeqw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pcmpeqw:
; SKX: # BB#0:
@@ -2007,9 +2007,9 @@ define <32 x i8> @test_pcmpgtb(<32 x i8>
;
; SKYLAKE-LABEL: test_pcmpgtb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpcmpgtb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpcmpgtb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pcmpgtb:
; SKX: # BB#0:
@@ -2047,9 +2047,9 @@ define <8 x i32> @test_pcmpgtd(<8 x i32>
;
; SKYLAKE-LABEL: test_pcmpgtd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpcmpgtd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpcmpgtd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pcmpgtd:
; SKX: # BB#0:
@@ -2088,8 +2088,8 @@ define <4 x i64> @test_pcmpgtq(<4 x i64>
; SKYLAKE-LABEL: test_pcmpgtq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpcmpgtq (%rdi), %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpcmpgtq (%rdi), %ymm0, %ymm0 # sched: [10:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pcmpgtq:
; SKX: # BB#0:
@@ -2127,9 +2127,9 @@ define <16 x i16> @test_pcmpgtw(<16 x i1
;
; SKYLAKE-LABEL: test_pcmpgtw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpcmpgtw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpcmpgtw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pcmpgtw:
; SKX: # BB#0:
@@ -2170,9 +2170,9 @@ define <4 x i64> @test_perm2i128(<4 x i6
; SKYLAKE-LABEL: test_perm2i128:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm0[2,3],ymm1[0,1] sched: [3:1.00]
-; SKYLAKE-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],mem[0,1] sched: [3:1.00]
-; SKYLAKE-NEXT: vpaddq %ymm0, %ymm1, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],mem[0,1] sched: [10:1.00]
+; SKYLAKE-NEXT: vpaddq %ymm0, %ymm1, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_perm2i128:
; SKX: # BB#0:
@@ -2212,9 +2212,9 @@ define <8 x i32> @test_permd(<8 x i32> %
; SKYLAKE-LABEL: test_permd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpermd %ymm1, %ymm0, %ymm1 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpermd (%rdi), %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpaddd %ymm0, %ymm1, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpermd (%rdi), %ymm0, %ymm0 # sched: [10:1.00]
+; SKYLAKE-NEXT: vpaddd %ymm0, %ymm1, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_permd:
; SKX: # BB#0:
@@ -2255,9 +2255,9 @@ define <4 x double> @test_permpd(<4 x do
; SKYLAKE-LABEL: test_permpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[3,2,2,3] sched: [3:1.00]
-; SKYLAKE-NEXT: vpermpd {{.*#+}} ymm1 = mem[0,2,2,3] sched: [3:1.00]
+; SKYLAKE-NEXT: vpermpd {{.*#+}} ymm1 = mem[0,2,2,3] sched: [10:1.00]
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_permpd:
; SKX: # BB#0:
@@ -2297,9 +2297,9 @@ define <8 x float> @test_permps(<8 x i32
; SKYLAKE-LABEL: test_permps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpermps %ymm1, %ymm0, %ymm1 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpermps (%rdi), %ymm0, %ymm0 # sched: [3:1.00]
+; SKYLAKE-NEXT: vpermps (%rdi), %ymm0, %ymm0 # sched: [10:1.00]
; SKYLAKE-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_permps:
; SKX: # BB#0:
@@ -2340,9 +2340,9 @@ define <4 x i64> @test_permq(<4 x i64> %
; SKYLAKE-LABEL: test_permq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,2,2,3] sched: [3:1.00]
-; SKYLAKE-NEXT: vpermq {{.*#+}} ymm1 = mem[0,2,2,3] sched: [3:1.00]
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpermq {{.*#+}} ymm1 = mem[0,2,2,3] sched: [10:1.00]
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_permq:
; SKX: # BB#0:
@@ -2377,8 +2377,8 @@ define <4 x i32> @test_pgatherdd(<4 x i3
;
; SKYLAKE-LABEL: test_pgatherdd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpgatherdd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpgatherdd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pgatherdd:
; SKX: # BB#0:
@@ -2407,8 +2407,8 @@ define <8 x i32> @test_pgatherdd_ymm(<8
;
; SKYLAKE-LABEL: test_pgatherdd_ymm:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpgatherdd %ymm2, (%rdi,%ymm1,2), %ymm0 # sched: [20:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpgatherdd %ymm2, (%rdi,%ymm1,2), %ymm0 # sched: [25:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pgatherdd_ymm:
; SKX: # BB#0:
@@ -2437,8 +2437,8 @@ define <2 x i64> @test_pgatherdq(<2 x i6
;
; SKYLAKE-LABEL: test_pgatherdq:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpgatherdq %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpgatherdq %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pgatherdq:
; SKX: # BB#0:
@@ -2467,8 +2467,8 @@ define <4 x i64> @test_pgatherdq_ymm(<4
;
; SKYLAKE-LABEL: test_pgatherdq_ymm:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpgatherdq %ymm2, (%rdi,%xmm1,2), %ymm0 # sched: [20:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpgatherdq %ymm2, (%rdi,%xmm1,2), %ymm0 # sched: [25:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pgatherdq_ymm:
; SKX: # BB#0:
@@ -2497,8 +2497,8 @@ define <4 x i32> @test_pgatherqd(<4 x i3
;
; SKYLAKE-LABEL: test_pgatherqd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpgatherqd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpgatherqd %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pgatherqd:
; SKX: # BB#0:
@@ -2529,9 +2529,9 @@ define <4 x i32> @test_pgatherqd_ymm(<4
;
; SKYLAKE-LABEL: test_pgatherqd_ymm:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpgatherqd %xmm2, (%rdi,%ymm1,2), %xmm0 # sched: [20:1.00]
+; SKYLAKE-NEXT: vpgatherqd %xmm2, (%rdi,%ymm1,2), %xmm0 # sched: [25:1.00]
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pgatherqd_ymm:
; SKX: # BB#0:
@@ -2562,8 +2562,8 @@ define <2 x i64> @test_pgatherqq(<2 x i6
;
; SKYLAKE-LABEL: test_pgatherqq:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpgatherqq %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [17:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpgatherqq %xmm2, (%rdi,%xmm1,2), %xmm0 # sched: [22:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pgatherqq:
; SKX: # BB#0:
@@ -2592,8 +2592,8 @@ define <4 x i64> @test_pgatherqq_ymm(<4
;
; SKYLAKE-LABEL: test_pgatherqq_ymm:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpgatherqq %ymm2, (%rdi,%ymm1,2), %ymm0 # sched: [20:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpgatherqq %ymm2, (%rdi,%ymm1,2), %ymm0 # sched: [25:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pgatherqq_ymm:
; SKX: # BB#0:
@@ -2625,8 +2625,8 @@ define <8 x i32> @test_phaddd(<8 x i32>
; SKYLAKE-LABEL: test_phaddd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vphaddd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: vphaddd (%rdi), %ymm0, %ymm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vphaddd (%rdi), %ymm0, %ymm0 # sched: [10:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_phaddd:
; SKX: # BB#0:
@@ -2662,8 +2662,8 @@ define <16 x i16> @test_phaddsw(<16 x i1
; SKYLAKE-LABEL: test_phaddsw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vphaddsw %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: vphaddsw (%rdi), %ymm0, %ymm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vphaddsw (%rdi), %ymm0, %ymm0 # sched: [10:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_phaddsw:
; SKX: # BB#0:
@@ -2699,8 +2699,8 @@ define <16 x i16> @test_phaddw(<16 x i16
; SKYLAKE-LABEL: test_phaddw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vphaddw %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: vphaddw (%rdi), %ymm0, %ymm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vphaddw (%rdi), %ymm0, %ymm0 # sched: [10:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_phaddw:
; SKX: # BB#0:
@@ -2736,8 +2736,8 @@ define <8 x i32> @test_phsubd(<8 x i32>
; SKYLAKE-LABEL: test_phsubd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vphsubd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: vphsubd (%rdi), %ymm0, %ymm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vphsubd (%rdi), %ymm0, %ymm0 # sched: [10:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_phsubd:
; SKX: # BB#0:
@@ -2773,8 +2773,8 @@ define <16 x i16> @test_phsubsw(<16 x i1
; SKYLAKE-LABEL: test_phsubsw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vphsubsw %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: vphsubsw (%rdi), %ymm0, %ymm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vphsubsw (%rdi), %ymm0, %ymm0 # sched: [10:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_phsubsw:
; SKX: # BB#0:
@@ -2810,8 +2810,8 @@ define <16 x i16> @test_phsubw(<16 x i16
; SKYLAKE-LABEL: test_phsubw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vphsubw %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: vphsubw (%rdi), %ymm0, %ymm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vphsubw (%rdi), %ymm0, %ymm0 # sched: [10:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_phsubw:
; SKX: # BB#0:
@@ -2847,8 +2847,8 @@ define <16 x i16> @test_pmaddubsw(<32 x
; SKYLAKE-LABEL: test_pmaddubsw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vpmaddubsw (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmaddubsw (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaddubsw:
; SKX: # BB#0:
@@ -2885,8 +2885,8 @@ define <8 x i32> @test_pmaddwd(<16 x i16
; SKYLAKE-LABEL: test_pmaddwd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vpmaddwd (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmaddwd (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaddwd:
; SKX: # BB#0:
@@ -2924,10 +2924,10 @@ define <4 x i32> @test_pmaskmovd(i8* %a0
;
; SKYLAKE-LABEL: test_pmaskmovd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpmaskmovd (%rdi), %xmm0, %xmm2 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpmaskmovd %xmm1, %xmm0, (%rdi) # sched: [1:1.00]
+; SKYLAKE-NEXT: vpmaskmovd (%rdi), %xmm0, %xmm2 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpmaskmovd %xmm1, %xmm0, (%rdi) # sched: [2:1.00]
; SKYLAKE-NEXT: vmovdqa %xmm2, %xmm0 # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaskmovd:
; SKX: # BB#0:
@@ -2966,10 +2966,10 @@ define <8 x i32> @test_pmaskmovd_ymm(i8*
;
; SKYLAKE-LABEL: test_pmaskmovd_ymm:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpmaskmovd (%rdi), %ymm0, %ymm2 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpmaskmovd %ymm1, %ymm0, (%rdi) # sched: [1:1.00]
+; SKYLAKE-NEXT: vpmaskmovd (%rdi), %ymm0, %ymm2 # sched: [8:0.50]
+; SKYLAKE-NEXT: vpmaskmovd %ymm1, %ymm0, (%rdi) # sched: [2:1.00]
; SKYLAKE-NEXT: vmovdqa %ymm2, %ymm0 # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaskmovd_ymm:
; SKX: # BB#0:
@@ -3008,10 +3008,10 @@ define <2 x i64> @test_pmaskmovq(i8* %a0
;
; SKYLAKE-LABEL: test_pmaskmovq:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpmaskmovq (%rdi), %xmm0, %xmm2 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpmaskmovq %xmm1, %xmm0, (%rdi) # sched: [1:1.00]
+; SKYLAKE-NEXT: vpmaskmovq (%rdi), %xmm0, %xmm2 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpmaskmovq %xmm1, %xmm0, (%rdi) # sched: [2:1.00]
; SKYLAKE-NEXT: vmovdqa %xmm2, %xmm0 # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaskmovq:
; SKX: # BB#0:
@@ -3050,10 +3050,10 @@ define <4 x i64> @test_pmaskmovq_ymm(i8*
;
; SKYLAKE-LABEL: test_pmaskmovq_ymm:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpmaskmovq (%rdi), %ymm0, %ymm2 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpmaskmovq %ymm1, %ymm0, (%rdi) # sched: [1:1.00]
+; SKYLAKE-NEXT: vpmaskmovq (%rdi), %ymm0, %ymm2 # sched: [8:0.50]
+; SKYLAKE-NEXT: vpmaskmovq %ymm1, %ymm0, (%rdi) # sched: [2:1.00]
; SKYLAKE-NEXT: vmovdqa %ymm2, %ymm0 # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaskmovq_ymm:
; SKX: # BB#0:
@@ -3090,9 +3090,9 @@ define <32 x i8> @test_pmaxsb(<32 x i8>
;
; SKYLAKE-LABEL: test_pmaxsb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpmaxsb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpmaxsb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaxsb:
; SKX: # BB#0:
@@ -3127,9 +3127,9 @@ define <8 x i32> @test_pmaxsd(<8 x i32>
;
; SKYLAKE-LABEL: test_pmaxsd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpmaxsd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpmaxsd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaxsd:
; SKX: # BB#0:
@@ -3164,9 +3164,9 @@ define <16 x i16> @test_pmaxsw(<16 x i16
;
; SKYLAKE-LABEL: test_pmaxsw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpmaxsw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpmaxsw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaxsw:
; SKX: # BB#0:
@@ -3201,9 +3201,9 @@ define <32 x i8> @test_pmaxub(<32 x i8>
;
; SKYLAKE-LABEL: test_pmaxub:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpmaxub (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpmaxub (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaxub:
; SKX: # BB#0:
@@ -3238,9 +3238,9 @@ define <8 x i32> @test_pmaxud(<8 x i32>
;
; SKYLAKE-LABEL: test_pmaxud:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpmaxud (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpmaxud (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaxud:
; SKX: # BB#0:
@@ -3275,9 +3275,9 @@ define <16 x i16> @test_pmaxuw(<16 x i16
;
; SKYLAKE-LABEL: test_pmaxuw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpmaxuw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpmaxuw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaxuw:
; SKX: # BB#0:
@@ -3312,9 +3312,9 @@ define <32 x i8> @test_pminsb(<32 x i8>
;
; SKYLAKE-LABEL: test_pminsb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpminsb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpminsb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpminsb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpminsb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pminsb:
; SKX: # BB#0:
@@ -3349,9 +3349,9 @@ define <8 x i32> @test_pminsd(<8 x i32>
;
; SKYLAKE-LABEL: test_pminsd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpminsd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpminsd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpminsd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpminsd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pminsd:
; SKX: # BB#0:
@@ -3386,9 +3386,9 @@ define <16 x i16> @test_pminsw(<16 x i16
;
; SKYLAKE-LABEL: test_pminsw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpminsw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpminsw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpminsw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpminsw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pminsw:
; SKX: # BB#0:
@@ -3423,9 +3423,9 @@ define <32 x i8> @test_pminub(<32 x i8>
;
; SKYLAKE-LABEL: test_pminub:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpminub %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpminub (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpminub %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpminub (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pminub:
; SKX: # BB#0:
@@ -3460,9 +3460,9 @@ define <8 x i32> @test_pminud(<8 x i32>
;
; SKYLAKE-LABEL: test_pminud:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpminud %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpminud (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpminud %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpminud (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pminud:
; SKX: # BB#0:
@@ -3497,9 +3497,9 @@ define <16 x i16> @test_pminuw(<16 x i16
;
; SKYLAKE-LABEL: test_pminuw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpminuw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpminuw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpminuw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpminuw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pminuw:
; SKX: # BB#0:
@@ -3536,7 +3536,7 @@ define i32 @test_pmovmskb(<32 x i8> %a0)
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovmskb %ymm0, %eax # sched: [2:1.00]
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovmskb:
; SKX: # BB#0:
@@ -3572,9 +3572,9 @@ define <8 x i32> @test_pmovsxbd(<16 x i8
; SKYLAKE-LABEL: test_pmovsxbd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovsxbd %xmm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpmovsxbd (%rdi), %ymm1 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovsxbd (%rdi), %ymm1 # sched: [8:1.00]
+; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovsxbd:
; SKX: # BB#0:
@@ -3616,9 +3616,9 @@ define <4 x i64> @test_pmovsxbq(<16 x i8
; SKYLAKE-LABEL: test_pmovsxbq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovsxbq %xmm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpmovsxbq (%rdi), %ymm1 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovsxbq (%rdi), %ymm1 # sched: [8:1.00]
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovsxbq:
; SKX: # BB#0:
@@ -3660,9 +3660,9 @@ define <16 x i16> @test_pmovsxbw(<16 x i
; SKYLAKE-LABEL: test_pmovsxbw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovsxbw %xmm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpmovsxbw (%rdi), %ymm1 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpaddw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovsxbw (%rdi), %ymm1 # sched: [9:1.00]
+; SKYLAKE-NEXT: vpaddw %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovsxbw:
; SKX: # BB#0:
@@ -3702,9 +3702,9 @@ define <4 x i64> @test_pmovsxdq(<4 x i32
; SKYLAKE-LABEL: test_pmovsxdq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovsxdq %xmm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpmovsxdq (%rdi), %ymm1 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovsxdq (%rdi), %ymm1 # sched: [9:1.00]
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovsxdq:
; SKX: # BB#0:
@@ -3744,9 +3744,9 @@ define <8 x i32> @test_pmovsxwd(<8 x i16
; SKYLAKE-LABEL: test_pmovsxwd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovsxwd %xmm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpmovsxwd (%rdi), %ymm1 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovsxwd (%rdi), %ymm1 # sched: [9:1.00]
+; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovsxwd:
; SKX: # BB#0:
@@ -3786,9 +3786,9 @@ define <4 x i64> @test_pmovsxwq(<8 x i16
; SKYLAKE-LABEL: test_pmovsxwq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovsxwq %xmm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpmovsxwq (%rdi), %ymm1 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovsxwq (%rdi), %ymm1 # sched: [8:1.00]
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovsxwq:
; SKX: # BB#0:
@@ -3830,9 +3830,9 @@ define <8 x i32> @test_pmovzxbd(<16 x i8
; SKYLAKE-LABEL: test_pmovzxbd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero sched: [3:1.00]
-; SKYLAKE-NEXT: vpmovzxbd {{.*#+}} ymm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero sched: [3:1.00]
-; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovzxbd {{.*#+}} ymm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero sched: [10:1.00]
+; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovzxbd:
; SKX: # BB#0:
@@ -3874,9 +3874,9 @@ define <4 x i64> @test_pmovzxbq(<16 x i8
; SKYLAKE-LABEL: test_pmovzxbq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovzxbq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero sched: [3:1.00]
-; SKYLAKE-NEXT: vpmovzxbq {{.*#+}} ymm1 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero,mem[2],zero,zero,zero,zero,zero,zero,zero,mem[3],zero,zero,zero,zero,zero,zero,zero sched: [3:1.00]
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovzxbq {{.*#+}} ymm1 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero,mem[2],zero,zero,zero,zero,zero,zero,zero,mem[3],zero,zero,zero,zero,zero,zero,zero sched: [10:1.00]
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovzxbq:
; SKX: # BB#0:
@@ -3918,9 +3918,9 @@ define <16 x i16> @test_pmovzxbw(<16 x i
; SKYLAKE-LABEL: test_pmovzxbw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero sched: [3:1.00]
-; SKYLAKE-NEXT: vpmovzxbw {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero sched: [3:1.00]
-; SKYLAKE-NEXT: vpaddw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovzxbw {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero sched: [10:1.00]
+; SKYLAKE-NEXT: vpaddw %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovzxbw:
; SKX: # BB#0:
@@ -3960,9 +3960,9 @@ define <4 x i64> @test_pmovzxdq(<4 x i32
; SKYLAKE-LABEL: test_pmovzxdq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero sched: [3:1.00]
-; SKYLAKE-NEXT: vpmovzxdq {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero sched: [3:1.00]
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovzxdq {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero sched: [10:1.00]
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovzxdq:
; SKX: # BB#0:
@@ -4002,9 +4002,9 @@ define <8 x i32> @test_pmovzxwd(<8 x i16
; SKYLAKE-LABEL: test_pmovzxwd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero sched: [3:1.00]
-; SKYLAKE-NEXT: vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero sched: [3:1.00]
-; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero sched: [9:1.00]
+; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovzxwd:
; SKX: # BB#0:
@@ -4044,9 +4044,9 @@ define <4 x i64> @test_pmovzxwq(<8 x i16
; SKYLAKE-LABEL: test_pmovzxwq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovzxwq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero sched: [3:1.00]
-; SKYLAKE-NEXT: vpmovzxwq {{.*#+}} ymm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero sched: [3:1.00]
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovzxwq {{.*#+}} ymm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero sched: [10:1.00]
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovzxwq:
; SKX: # BB#0:
@@ -4086,8 +4086,8 @@ define <4 x i64> @test_pmuldq(<8 x i32>
; SKYLAKE-LABEL: test_pmuldq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmuldq %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vpmuldq (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmuldq (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmuldq:
; SKX: # BB#0:
@@ -4124,8 +4124,8 @@ define <16 x i16> @test_pmulhrsw(<16 x i
; SKYLAKE-LABEL: test_pmulhrsw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmulhrsw %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vpmulhrsw (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmulhrsw (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmulhrsw:
; SKX: # BB#0:
@@ -4161,8 +4161,8 @@ define <16 x i16> @test_pmulhuw(<16 x i1
; SKYLAKE-LABEL: test_pmulhuw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vpmulhuw (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmulhuw (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmulhuw:
; SKX: # BB#0:
@@ -4198,8 +4198,8 @@ define <16 x i16> @test_pmulhw(<16 x i16
; SKYLAKE-LABEL: test_pmulhw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmulhw %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vpmulhw (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmulhw (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmulhw:
; SKX: # BB#0:
@@ -4235,8 +4235,8 @@ define <8 x i32> @test_pmulld(<8 x i32>
; SKYLAKE-LABEL: test_pmulld:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmulld %ymm1, %ymm0, %ymm0 # sched: [8:0.67]
-; SKYLAKE-NEXT: vpmulld (%rdi), %ymm0, %ymm0 # sched: [8:0.67]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmulld (%rdi), %ymm0, %ymm0 # sched: [15:0.67]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmulld:
; SKX: # BB#0:
@@ -4271,8 +4271,8 @@ define <16 x i16> @test_pmullw(<16 x i16
; SKYLAKE-LABEL: test_pmullw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmullw %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vpmullw (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmullw (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmullw:
; SKX: # BB#0:
@@ -4307,8 +4307,8 @@ define <4 x i64> @test_pmuludq(<8 x i32>
; SKYLAKE-LABEL: test_pmuludq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmuludq %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vpmuludq (%rdi), %ymm0, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmuludq (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmuludq:
; SKX: # BB#0:
@@ -4346,10 +4346,10 @@ define <4 x i64> @test_por(<4 x i64> %a0
;
; SKYLAKE-LABEL: test_por:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpor (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpor (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_por:
; SKX: # BB#0:
@@ -4387,8 +4387,8 @@ define <4 x i64> @test_psadbw(<32 x i8>
; SKYLAKE-LABEL: test_psadbw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpsadbw (%rdi), %ymm0, %ymm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsadbw (%rdi), %ymm0, %ymm0 # sched: [10:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psadbw:
; SKX: # BB#0:
@@ -4425,8 +4425,8 @@ define <32 x i8> @test_pshufb(<32 x i8>
; SKYLAKE-LABEL: test_pshufb:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpshufb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpshufb (%rdi), %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpshufb (%rdi), %ymm0, %ymm0 # sched: [8:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pshufb:
; SKX: # BB#0:
@@ -4464,9 +4464,9 @@ define <8 x i32> @test_pshufd(<8 x i32>
; SKYLAKE-LABEL: test_pshufd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4] sched: [1:1.00]
-; SKYLAKE-NEXT: vpshufd {{.*#+}} ymm1 = mem[1,0,3,2,5,4,7,6] sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpshufd {{.*#+}} ymm1 = mem[1,0,3,2,5,4,7,6] sched: [8:1.00]
+; SKYLAKE-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pshufd:
; SKX: # BB#0:
@@ -4506,9 +4506,9 @@ define <16 x i16> @test_pshufhw(<16 x i1
; SKYLAKE-LABEL: test_pshufhw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,7,6,5,4,8,9,10,11,15,14,13,12] sched: [1:1.00]
-; SKYLAKE-NEXT: vpshufhw {{.*#+}} ymm1 = mem[0,1,2,3,5,4,7,6,8,9,10,11,13,12,15,14] sched: [1:1.00]
-; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpshufhw {{.*#+}} ymm1 = mem[0,1,2,3,5,4,7,6,8,9,10,11,13,12,15,14] sched: [8:1.00]
+; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pshufhw:
; SKX: # BB#0:
@@ -4548,9 +4548,9 @@ define <16 x i16> @test_pshuflw(<16 x i1
; SKYLAKE-LABEL: test_pshuflw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpshuflw {{.*#+}} ymm0 = ymm0[3,2,1,0,4,5,6,7,11,10,9,8,12,13,14,15] sched: [1:1.00]
-; SKYLAKE-NEXT: vpshuflw {{.*#+}} ymm1 = mem[1,0,3,2,4,5,6,7,9,8,11,10,12,13,14,15] sched: [1:1.00]
-; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpshuflw {{.*#+}} ymm1 = mem[1,0,3,2,4,5,6,7,9,8,11,10,12,13,14,15] sched: [8:1.00]
+; SKYLAKE-NEXT: vpor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pshuflw:
; SKX: # BB#0:
@@ -4587,9 +4587,9 @@ define <32 x i8> @test_psignb(<32 x i8>
;
; SKYLAKE-LABEL: test_psignb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsignb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsignb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsignb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsignb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psignb:
; SKX: # BB#0:
@@ -4624,9 +4624,9 @@ define <8 x i32> @test_psignd(<8 x i32>
;
; SKYLAKE-LABEL: test_psignd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsignd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsignd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsignd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsignd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psignd:
; SKX: # BB#0:
@@ -4661,9 +4661,9 @@ define <16 x i16> @test_psignw(<16 x i16
;
; SKYLAKE-LABEL: test_psignw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsignw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsignw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsignw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsignw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psignw:
; SKX: # BB#0:
@@ -4701,9 +4701,9 @@ define <8 x i32> @test_pslld(<8 x i32> %
; SKYLAKE-LABEL: test_pslld:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpslld %xmm1, %ymm0, %ymm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: vpslld (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpslld $2, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpslld (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: vpslld $2, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pslld:
; SKX: # BB#0:
@@ -4740,7 +4740,7 @@ define <32 x i8> @test_pslldq(<32 x i8>
; SKYLAKE-LABEL: test_pslldq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12],zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pslldq:
; SKX: # BB#0:
@@ -4773,9 +4773,9 @@ define <4 x i64> @test_psllq(<4 x i64> %
; SKYLAKE-LABEL: test_psllq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpsllq %xmm1, %ymm0, %ymm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: vpsllq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsllq $2, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsllq (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: vpsllq $2, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psllq:
; SKX: # BB#0:
@@ -4813,9 +4813,9 @@ define <4 x i32> @test_psllvd(<4 x i32>
;
; SKYLAKE-LABEL: test_psllvd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsllvd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsllvd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsllvd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsllvd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psllvd:
; SKX: # BB#0:
@@ -4850,9 +4850,9 @@ define <8 x i32> @test_psllvd_ymm(<8 x i
;
; SKYLAKE-LABEL: test_psllvd_ymm:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsllvd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsllvd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psllvd_ymm:
; SKX: # BB#0:
@@ -4887,9 +4887,9 @@ define <2 x i64> @test_psllvq(<2 x i64>
;
; SKYLAKE-LABEL: test_psllvq:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsllvq %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsllvq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsllvq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsllvq (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psllvq:
; SKX: # BB#0:
@@ -4924,9 +4924,9 @@ define <4 x i64> @test_psllvq_ymm(<4 x i
;
; SKYLAKE-LABEL: test_psllvq_ymm:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsllvq %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsllvq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsllvq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsllvq (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psllvq_ymm:
; SKX: # BB#0:
@@ -4964,9 +4964,9 @@ define <16 x i16> @test_psllw(<16 x i16>
; SKYLAKE-LABEL: test_psllw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpsllw %xmm1, %ymm0, %ymm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: vpsllw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsllw $2, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsllw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: vpsllw $2, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psllw:
; SKX: # BB#0:
@@ -5007,9 +5007,9 @@ define <8 x i32> @test_psrad(<8 x i32> %
; SKYLAKE-LABEL: test_psrad:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpsrad %xmm1, %ymm0, %ymm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: vpsrad (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsrad $2, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsrad (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: vpsrad $2, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psrad:
; SKX: # BB#0:
@@ -5047,9 +5047,9 @@ define <4 x i32> @test_psravd(<4 x i32>
;
; SKYLAKE-LABEL: test_psravd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsravd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsravd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsravd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsravd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psravd:
; SKX: # BB#0:
@@ -5084,9 +5084,9 @@ define <8 x i32> @test_psravd_ymm(<8 x i
;
; SKYLAKE-LABEL: test_psravd_ymm:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsravd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsravd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsravd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsravd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psravd_ymm:
; SKX: # BB#0:
@@ -5124,9 +5124,9 @@ define <16 x i16> @test_psraw(<16 x i16>
; SKYLAKE-LABEL: test_psraw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpsraw %xmm1, %ymm0, %ymm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: vpsraw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsraw $2, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsraw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: vpsraw $2, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psraw:
; SKX: # BB#0:
@@ -5167,9 +5167,9 @@ define <8 x i32> @test_psrld(<8 x i32> %
; SKYLAKE-LABEL: test_psrld:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpsrld %xmm1, %ymm0, %ymm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: vpsrld (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsrld $2, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsrld (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: vpsrld $2, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psrld:
; SKX: # BB#0:
@@ -5206,7 +5206,7 @@ define <32 x i8> @test_psrldq(<32 x i8>
; SKYLAKE-LABEL: test_psrldq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[3,4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,ymm0[19,20,21,22,23,24,25,26,27,28,29,30,31],zero,zero,zero sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psrldq:
; SKX: # BB#0:
@@ -5239,9 +5239,9 @@ define <4 x i64> @test_psrlq(<4 x i64> %
; SKYLAKE-LABEL: test_psrlq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpsrlq %xmm1, %ymm0, %ymm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: vpsrlq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsrlq $2, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsrlq (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: vpsrlq $2, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psrlq:
; SKX: # BB#0:
@@ -5279,9 +5279,9 @@ define <4 x i32> @test_psrlvd(<4 x i32>
;
; SKYLAKE-LABEL: test_psrlvd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsrlvd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsrlvd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psrlvd:
; SKX: # BB#0:
@@ -5316,9 +5316,9 @@ define <8 x i32> @test_psrlvd_ymm(<8 x i
;
; SKYLAKE-LABEL: test_psrlvd_ymm:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsrlvd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsrlvd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psrlvd_ymm:
; SKX: # BB#0:
@@ -5353,9 +5353,9 @@ define <2 x i64> @test_psrlvq(<2 x i64>
;
; SKYLAKE-LABEL: test_psrlvq:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsrlvq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsrlvq (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psrlvq:
; SKX: # BB#0:
@@ -5390,9 +5390,9 @@ define <4 x i64> @test_psrlvq_ymm(<4 x i
;
; SKYLAKE-LABEL: test_psrlvq_ymm:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsrlvq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsrlvq (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psrlvq_ymm:
; SKX: # BB#0:
@@ -5430,9 +5430,9 @@ define <16 x i16> @test_psrlw(<16 x i16>
; SKYLAKE-LABEL: test_psrlw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpsrlw %xmm1, %ymm0, %ymm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: vpsrlw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsrlw $2, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsrlw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: vpsrlw $2, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psrlw:
; SKX: # BB#0:
@@ -5470,9 +5470,9 @@ define <32 x i8> @test_psubb(<32 x i8> %
;
; SKYLAKE-LABEL: test_psubb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsubb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsubb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsubb %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpsubb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psubb:
; SKX: # BB#0:
@@ -5506,9 +5506,9 @@ define <8 x i32> @test_psubd(<8 x i32> %
;
; SKYLAKE-LABEL: test_psubd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsubd (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpsubd (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psubd:
; SKX: # BB#0:
@@ -5542,9 +5542,9 @@ define <4 x i64> @test_psubq(<4 x i64> %
;
; SKYLAKE-LABEL: test_psubq:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsubq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsubq (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsubq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpsubq (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psubq:
; SKX: # BB#0:
@@ -5578,9 +5578,9 @@ define <32 x i8> @test_psubsb(<32 x i8>
;
; SKYLAKE-LABEL: test_psubsb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsubsb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsubsb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsubsb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsubsb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psubsb:
; SKX: # BB#0:
@@ -5615,9 +5615,9 @@ define <16 x i16> @test_psubsw(<16 x i16
;
; SKYLAKE-LABEL: test_psubsw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsubsw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsubsw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsubsw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsubsw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psubsw:
; SKX: # BB#0:
@@ -5652,9 +5652,9 @@ define <32 x i8> @test_psubusb(<32 x i8>
;
; SKYLAKE-LABEL: test_psubusb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsubusb %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsubusb (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsubusb %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsubusb (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psubusb:
; SKX: # BB#0:
@@ -5689,9 +5689,9 @@ define <16 x i16> @test_psubusw(<16 x i1
;
; SKYLAKE-LABEL: test_psubusw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsubusw %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsubusw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsubusw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsubusw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psubusw:
; SKX: # BB#0:
@@ -5726,9 +5726,9 @@ define <16 x i16> @test_psubw(<16 x i16>
;
; SKYLAKE-LABEL: test_psubw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsubw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsubw (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsubw %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpsubw (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psubw:
; SKX: # BB#0:
@@ -5763,8 +5763,8 @@ define <32 x i8> @test_punpckhbw(<32 x i
; SKYLAKE-LABEL: test_punpckhbw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpunpckhbw {{.*#+}} ymm0 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31] sched: [1:1.00]
-; SKYLAKE-NEXT: vpunpckhbw {{.*#+}} ymm0 = ymm0[8],mem[8],ymm0[9],mem[9],ymm0[10],mem[10],ymm0[11],mem[11],ymm0[12],mem[12],ymm0[13],mem[13],ymm0[14],mem[14],ymm0[15],mem[15],ymm0[24],mem[24],ymm0[25],mem[25],ymm0[26],mem[26],ymm0[27],mem[27],ymm0[28],mem[28],ymm0[29],mem[29],ymm0[30],mem[30],ymm0[31],mem[31] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpunpckhbw {{.*#+}} ymm0 = ymm0[8],mem[8],ymm0[9],mem[9],ymm0[10],mem[10],ymm0[11],mem[11],ymm0[12],mem[12],ymm0[13],mem[13],ymm0[14],mem[14],ymm0[15],mem[15],ymm0[24],mem[24],ymm0[25],mem[25],ymm0[26],mem[26],ymm0[27],mem[27],ymm0[28],mem[28],ymm0[29],mem[29],ymm0[30],mem[30],ymm0[31],mem[31] sched: [8:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_punpckhbw:
; SKX: # BB#0:
@@ -5803,10 +5803,10 @@ define <8 x i32> @test_punpckhdq(<8 x i3
; SKYLAKE-LABEL: test_punpckhdq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpunpckhdq {{.*#+}} ymm0 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7] sched: [1:1.00]
-; SKYLAKE-NEXT: vpunpckhdq {{.*#+}} ymm0 = ymm0[2],mem[2],ymm0[3],mem[3],ymm0[6],mem[6],ymm0[7],mem[7] sched: [1:1.00]
-; SKYLAKE-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpunpckhdq {{.*#+}} ymm0 = ymm0[2],mem[2],ymm0[3],mem[3],ymm0[6],mem[6],ymm0[7],mem[7] sched: [8:1.00]
+; SKYLAKE-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_punpckhdq:
; SKX: # BB#0:
@@ -5848,9 +5848,9 @@ define <4 x i64> @test_punpckhqdq(<4 x i
; SKYLAKE-LABEL: test_punpckhqdq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpunpckhqdq {{.*#+}} ymm1 = ymm0[1],ymm1[1],ymm0[3],ymm1[3] sched: [1:1.00]
-; SKYLAKE-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddq %ymm0, %ymm1, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],mem[1],ymm0[3],mem[3] sched: [8:1.00]
+; SKYLAKE-NEXT: vpaddq %ymm0, %ymm1, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_punpckhqdq:
; SKX: # BB#0:
@@ -5888,8 +5888,8 @@ define <16 x i16> @test_punpckhwd(<16 x
; SKYLAKE-LABEL: test_punpckhwd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpunpckhwd {{.*#+}} ymm0 = ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15] sched: [1:1.00]
-; SKYLAKE-NEXT: vpunpckhwd {{.*#+}} ymm0 = ymm0[4],mem[4],ymm0[5],mem[5],ymm0[6],mem[6],ymm0[7],mem[7],ymm0[12],mem[12],ymm0[13],mem[13],ymm0[14],mem[14],ymm0[15],mem[15] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpunpckhwd {{.*#+}} ymm0 = ymm0[4],mem[4],ymm0[5],mem[5],ymm0[6],mem[6],ymm0[7],mem[7],ymm0[12],mem[12],ymm0[13],mem[13],ymm0[14],mem[14],ymm0[15],mem[15] sched: [8:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_punpckhwd:
; SKX: # BB#0:
@@ -5924,8 +5924,8 @@ define <32 x i8> @test_punpcklbw(<32 x i
; SKYLAKE-LABEL: test_punpcklbw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23] sched: [1:1.00]
-; SKYLAKE-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[2],mem[2],ymm0[3],mem[3],ymm0[4],mem[4],ymm0[5],mem[5],ymm0[6],mem[6],ymm0[7],mem[7],ymm0[16],mem[16],ymm0[17],mem[17],ymm0[18],mem[18],ymm0[19],mem[19],ymm0[20],mem[20],ymm0[21],mem[21],ymm0[22],mem[22],ymm0[23],mem[23] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[2],mem[2],ymm0[3],mem[3],ymm0[4],mem[4],ymm0[5],mem[5],ymm0[6],mem[6],ymm0[7],mem[7],ymm0[16],mem[16],ymm0[17],mem[17],ymm0[18],mem[18],ymm0[19],mem[19],ymm0[20],mem[20],ymm0[21],mem[21],ymm0[22],mem[22],ymm0[23],mem[23] sched: [8:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_punpcklbw:
; SKX: # BB#0:
@@ -5964,10 +5964,10 @@ define <8 x i32> @test_punpckldq(<8 x i3
; SKYLAKE-LABEL: test_punpckldq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] sched: [1:1.00]
-; SKYLAKE-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[4],mem[4],ymm0[5],mem[5] sched: [1:1.00]
-; SKYLAKE-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[4],mem[4],ymm0[5],mem[5] sched: [8:1.00]
+; SKYLAKE-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsubd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_punpckldq:
; SKX: # BB#0:
@@ -6009,9 +6009,9 @@ define <4 x i64> @test_punpcklqdq(<4 x i
; SKYLAKE-LABEL: test_punpcklqdq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpunpcklqdq {{.*#+}} ymm1 = ymm0[0],ymm1[0],ymm0[2],ymm1[2] sched: [1:1.00]
-; SKYLAKE-NEXT: vpunpcklqdq {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[2],mem[2] sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddq %ymm0, %ymm1, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpunpcklqdq {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[2],mem[2] sched: [8:1.00]
+; SKYLAKE-NEXT: vpaddq %ymm0, %ymm1, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_punpcklqdq:
; SKX: # BB#0:
@@ -6049,8 +6049,8 @@ define <16 x i16> @test_punpcklwd(<16 x
; SKYLAKE-LABEL: test_punpcklwd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11] sched: [1:1.00]
-; SKYLAKE-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[2],mem[2],ymm0[3],mem[3],ymm0[8],mem[8],ymm0[9],mem[9],ymm0[10],mem[10],ymm0[11],mem[11] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[2],mem[2],ymm0[3],mem[3],ymm0[8],mem[8],ymm0[9],mem[9],ymm0[10],mem[10],ymm0[11],mem[11] sched: [8:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_punpcklwd:
; SKX: # BB#0:
@@ -6086,10 +6086,10 @@ define <4 x i64> @test_pxor(<4 x i64> %a
;
; SKYLAKE-LABEL: test_pxor:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpxor %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpxor (%rdi), %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpxor %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpxor (%rdi), %ymm0, %ymm0 # sched: [8:0.50]
+; SKYLAKE-NEXT: vpaddq %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pxor:
; SKX: # BB#0:
Modified: llvm/trunk/test/CodeGen/X86/bmi-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bmi-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bmi-schedule.ll Mon Oct 16 23:47:04 2017
@@ -29,10 +29,10 @@ define i16 @test_andn_i16(i16 zeroext %a
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: andnl %esi, %edi, %eax # sched: [1:0.50]
; SKYLAKE-NEXT: notl %edi # sched: [1:0.25]
-; SKYLAKE-NEXT: andw (%rdx), %di # sched: [1:0.50]
+; SKYLAKE-NEXT: andw (%rdx), %di # sched: [6:0.50]
; SKYLAKE-NEXT: addl %edi, %eax # sched: [1:0.25]
; SKYLAKE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_andn_i16:
; BTVER2: # BB#0:
@@ -77,9 +77,9 @@ define i32 @test_andn_i32(i32 %a0, i32 %
; SKYLAKE-LABEL: test_andn_i32:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: andnl %esi, %edi, %ecx # sched: [1:0.50]
-; SKYLAKE-NEXT: andnl (%rdx), %edi, %eax # sched: [1:0.50]
+; SKYLAKE-NEXT: andnl (%rdx), %edi, %eax # sched: [6:0.50]
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_andn_i32:
; BTVER2: # BB#0:
@@ -120,9 +120,9 @@ define i64 @test_andn_i64(i64 %a0, i64 %
; SKYLAKE-LABEL: test_andn_i64:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: andnq %rsi, %rdi, %rcx # sched: [1:0.50]
-; SKYLAKE-NEXT: andnq (%rdx), %rdi, %rax # sched: [1:0.50]
+; SKYLAKE-NEXT: andnq (%rdx), %rdi, %rax # sched: [6:0.50]
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_andn_i64:
; BTVER2: # BB#0:
@@ -162,10 +162,10 @@ define i32 @test_bextr_i32(i32 %a0, i32
;
; SKYLAKE-LABEL: test_bextr_i32:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: bextrl %edi, (%rdx), %ecx # sched: [2:0.50]
+; SKYLAKE-NEXT: bextrl %edi, (%rdx), %ecx # sched: [7:0.50]
; SKYLAKE-NEXT: bextrl %edi, %esi, %eax # sched: [2:0.50]
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_bextr_i32:
; BTVER2: # BB#0:
@@ -205,10 +205,10 @@ define i64 @test_bextr_i64(i64 %a0, i64
;
; SKYLAKE-LABEL: test_bextr_i64:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: bextrq %rdi, (%rdx), %rcx # sched: [2:0.50]
+; SKYLAKE-NEXT: bextrq %rdi, (%rdx), %rcx # sched: [7:0.50]
; SKYLAKE-NEXT: bextrq %rdi, %rsi, %rax # sched: [2:0.50]
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_bextr_i64:
; BTVER2: # BB#0:
@@ -248,10 +248,10 @@ define i32 @test_blsi_i32(i32 %a0, i32 *
;
; SKYLAKE-LABEL: test_blsi_i32:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: blsil (%rsi), %ecx # sched: [1:0.50]
+; SKYLAKE-NEXT: blsil (%rsi), %ecx # sched: [6:0.50]
; SKYLAKE-NEXT: blsil %edi, %eax # sched: [1:0.50]
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_blsi_i32:
; BTVER2: # BB#0:
@@ -292,10 +292,10 @@ define i64 @test_blsi_i64(i64 %a0, i64 *
;
; SKYLAKE-LABEL: test_blsi_i64:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: blsiq (%rsi), %rcx # sched: [1:0.50]
+; SKYLAKE-NEXT: blsiq (%rsi), %rcx # sched: [6:0.50]
; SKYLAKE-NEXT: blsiq %rdi, %rax # sched: [1:0.50]
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_blsi_i64:
; BTVER2: # BB#0:
@@ -336,10 +336,10 @@ define i32 @test_blsmsk_i32(i32 %a0, i32
;
; SKYLAKE-LABEL: test_blsmsk_i32:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: blsmskl (%rsi), %ecx # sched: [1:0.50]
+; SKYLAKE-NEXT: blsmskl (%rsi), %ecx # sched: [6:0.50]
; SKYLAKE-NEXT: blsmskl %edi, %eax # sched: [1:0.50]
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_blsmsk_i32:
; BTVER2: # BB#0:
@@ -380,10 +380,10 @@ define i64 @test_blsmsk_i64(i64 %a0, i64
;
; SKYLAKE-LABEL: test_blsmsk_i64:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: blsmskq (%rsi), %rcx # sched: [1:0.50]
+; SKYLAKE-NEXT: blsmskq (%rsi), %rcx # sched: [6:0.50]
; SKYLAKE-NEXT: blsmskq %rdi, %rax # sched: [1:0.50]
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_blsmsk_i64:
; BTVER2: # BB#0:
@@ -424,10 +424,10 @@ define i32 @test_blsr_i32(i32 %a0, i32 *
;
; SKYLAKE-LABEL: test_blsr_i32:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: blsrl (%rsi), %ecx # sched: [1:0.50]
+; SKYLAKE-NEXT: blsrl (%rsi), %ecx # sched: [6:0.50]
; SKYLAKE-NEXT: blsrl %edi, %eax # sched: [1:0.50]
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_blsr_i32:
; BTVER2: # BB#0:
@@ -468,10 +468,10 @@ define i64 @test_blsr_i64(i64 %a0, i64 *
;
; SKYLAKE-LABEL: test_blsr_i64:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: blsrq (%rsi), %rcx # sched: [1:0.50]
+; SKYLAKE-NEXT: blsrq (%rsi), %rcx # sched: [6:0.50]
; SKYLAKE-NEXT: blsrq %rdi, %rax # sched: [1:0.50]
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_blsr_i64:
; BTVER2: # BB#0:
@@ -514,11 +514,11 @@ define i16 @test_cttz_i16(i16 zeroext %a
;
; SKYLAKE-LABEL: test_cttz_i16:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: tzcntw (%rsi), %cx # sched: [3:1.00]
+; SKYLAKE-NEXT: tzcntw (%rsi), %cx # sched: [8:1.00]
; SKYLAKE-NEXT: tzcntw %di, %ax # sched: [3:1.00]
; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25]
; SKYLAKE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_cttz_i16:
; BTVER2: # BB#0:
@@ -560,10 +560,10 @@ define i32 @test_cttz_i32(i32 %a0, i32 *
;
; SKYLAKE-LABEL: test_cttz_i32:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: tzcntl (%rsi), %ecx # sched: [3:1.00]
+; SKYLAKE-NEXT: tzcntl (%rsi), %ecx # sched: [8:1.00]
; SKYLAKE-NEXT: tzcntl %edi, %eax # sched: [3:1.00]
; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_cttz_i32:
; BTVER2: # BB#0:
@@ -603,10 +603,10 @@ define i64 @test_cttz_i64(i64 %a0, i64 *
;
; SKYLAKE-LABEL: test_cttz_i64:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: tzcntq (%rsi), %rcx # sched: [3:1.00]
+; SKYLAKE-NEXT: tzcntq (%rsi), %rcx # sched: [8:1.00]
; SKYLAKE-NEXT: tzcntq %rdi, %rax # sched: [3:1.00]
; SKYLAKE-NEXT: orq %rcx, %rax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_cttz_i64:
; BTVER2: # BB#0:
Modified: llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bmi2-schedule.ll Mon Oct 16 23:47:04 2017
@@ -13,12 +13,26 @@ define i32 @test_bzhi_i32(i32 %a0, i32 %
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
-; COMMON-LABEL: test_bzhi_i32:
-; COMMON: # BB#0:
-; COMMON-NEXT: bzhil %edi, (%rdx), %ecx # sched: [1:0.50]
-; COMMON-NEXT: bzhil %edi, %esi, %eax # sched: [1:0.50]
-; COMMON-NEXT: addl %ecx, %eax # sched: [1:0.25]
-; COMMON-NEXT: retq # sched: [2:1.00]
+; HASWELL-LABEL: test_bzhi_i32:
+; HASWELL: # BB#0:
+; HASWELL-NEXT: bzhil %edi, (%rdx), %ecx # sched: [1:0.50]
+; HASWELL-NEXT: bzhil %edi, %esi, %eax # sched: [1:0.50]
+; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
+; HASWELL-NEXT: retq # sched: [2:1.00]
+;
+; SKYLAKE-LABEL: test_bzhi_i32:
+; SKYLAKE: # BB#0:
+; SKYLAKE-NEXT: bzhil %edi, (%rdx), %ecx # sched: [6:0.50]
+; SKYLAKE-NEXT: bzhil %edi, %esi, %eax # sched: [1:0.50]
+; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
+;
+; KNL-LABEL: test_bzhi_i32:
+; KNL: # BB#0:
+; KNL-NEXT: bzhil %edi, (%rdx), %ecx # sched: [1:0.50]
+; KNL-NEXT: bzhil %edi, %esi, %eax # sched: [1:0.50]
+; KNL-NEXT: addl %ecx, %eax # sched: [1:0.25]
+; KNL-NEXT: retq # sched: [2:1.00]
;
; ZNVER1-LABEL: test_bzhi_i32:
; ZNVER1: # BB#0:
@@ -42,12 +56,26 @@ define i64 @test_bzhi_i64(i64 %a0, i64 %
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
-; COMMON-LABEL: test_bzhi_i64:
-; COMMON: # BB#0:
-; COMMON-NEXT: bzhiq %rdi, (%rdx), %rcx # sched: [1:0.50]
-; COMMON-NEXT: bzhiq %rdi, %rsi, %rax # sched: [1:0.50]
-; COMMON-NEXT: addq %rcx, %rax # sched: [1:0.25]
-; COMMON-NEXT: retq # sched: [2:1.00]
+; HASWELL-LABEL: test_bzhi_i64:
+; HASWELL: # BB#0:
+; HASWELL-NEXT: bzhiq %rdi, (%rdx), %rcx # sched: [1:0.50]
+; HASWELL-NEXT: bzhiq %rdi, %rsi, %rax # sched: [1:0.50]
+; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
+; HASWELL-NEXT: retq # sched: [2:1.00]
+;
+; SKYLAKE-LABEL: test_bzhi_i64:
+; SKYLAKE: # BB#0:
+; SKYLAKE-NEXT: bzhiq %rdi, (%rdx), %rcx # sched: [6:0.50]
+; SKYLAKE-NEXT: bzhiq %rdi, %rsi, %rax # sched: [1:0.50]
+; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
+;
+; KNL-LABEL: test_bzhi_i64:
+; KNL: # BB#0:
+; KNL-NEXT: bzhiq %rdi, (%rdx), %rcx # sched: [1:0.50]
+; KNL-NEXT: bzhiq %rdi, %rsi, %rax # sched: [1:0.50]
+; KNL-NEXT: addq %rcx, %rax # sched: [1:0.25]
+; KNL-NEXT: retq # sched: [2:1.00]
;
; ZNVER1-LABEL: test_bzhi_i64:
; ZNVER1: # BB#0:
@@ -75,14 +103,32 @@ define i64 @test_mulx_i64(i64 %a0, i64 %
; GENERIC-NEXT: orq %rcx, %rax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
-; COMMON-LABEL: test_mulx_i64:
-; COMMON: # BB#0:
-; COMMON-NEXT: movq %rdx, %rax # sched: [1:0.25]
-; COMMON-NEXT: movq %rdi, %rdx # sched: [1:0.25]
-; COMMON-NEXT: mulxq %rsi, %rsi, %rcx # sched: [4:1.00]
-; COMMON-NEXT: mulxq (%rax), %rdx, %rax # sched: [4:1.00]
-; COMMON-NEXT: orq %rcx, %rax # sched: [1:0.25]
-; COMMON-NEXT: retq # sched: [2:1.00]
+; HASWELL-LABEL: test_mulx_i64:
+; HASWELL: # BB#0:
+; HASWELL-NEXT: movq %rdx, %rax # sched: [1:0.25]
+; HASWELL-NEXT: movq %rdi, %rdx # sched: [1:0.25]
+; HASWELL-NEXT: mulxq %rsi, %rsi, %rcx # sched: [4:1.00]
+; HASWELL-NEXT: mulxq (%rax), %rdx, %rax # sched: [4:1.00]
+; HASWELL-NEXT: orq %rcx, %rax # sched: [1:0.25]
+; HASWELL-NEXT: retq # sched: [2:1.00]
+;
+; SKYLAKE-LABEL: test_mulx_i64:
+; SKYLAKE: # BB#0:
+; SKYLAKE-NEXT: movq %rdx, %rax # sched: [1:0.25]
+; SKYLAKE-NEXT: movq %rdi, %rdx # sched: [1:0.25]
+; SKYLAKE-NEXT: mulxq %rsi, %rsi, %rcx # sched: [4:1.00]
+; SKYLAKE-NEXT: mulxq (%rax), %rdx, %rax # sched: [9:1.00]
+; SKYLAKE-NEXT: orq %rcx, %rax # sched: [1:0.25]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
+;
+; KNL-LABEL: test_mulx_i64:
+; KNL: # BB#0:
+; KNL-NEXT: movq %rdx, %rax # sched: [1:0.25]
+; KNL-NEXT: movq %rdi, %rdx # sched: [1:0.25]
+; KNL-NEXT: mulxq %rsi, %rsi, %rcx # sched: [4:1.00]
+; KNL-NEXT: mulxq (%rax), %rdx, %rax # sched: [4:1.00]
+; KNL-NEXT: orq %rcx, %rax # sched: [1:0.25]
+; KNL-NEXT: retq # sched: [2:1.00]
;
; ZNVER1-LABEL: test_mulx_i64:
; ZNVER1: # BB#0:
@@ -114,12 +160,26 @@ define i32 @test_pdep_i32(i32 %a0, i32 %
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
-; COMMON-LABEL: test_pdep_i32:
-; COMMON: # BB#0:
-; COMMON-NEXT: pdepl (%rdx), %edi, %ecx # sched: [3:1.00]
-; COMMON-NEXT: pdepl %esi, %edi, %eax # sched: [3:1.00]
-; COMMON-NEXT: addl %ecx, %eax # sched: [1:0.25]
-; COMMON-NEXT: retq # sched: [2:1.00]
+; HASWELL-LABEL: test_pdep_i32:
+; HASWELL: # BB#0:
+; HASWELL-NEXT: pdepl (%rdx), %edi, %ecx # sched: [3:1.00]
+; HASWELL-NEXT: pdepl %esi, %edi, %eax # sched: [3:1.00]
+; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
+; HASWELL-NEXT: retq # sched: [2:1.00]
+;
+; SKYLAKE-LABEL: test_pdep_i32:
+; SKYLAKE: # BB#0:
+; SKYLAKE-NEXT: pdepl (%rdx), %edi, %ecx # sched: [8:1.00]
+; SKYLAKE-NEXT: pdepl %esi, %edi, %eax # sched: [3:1.00]
+; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
+;
+; KNL-LABEL: test_pdep_i32:
+; KNL: # BB#0:
+; KNL-NEXT: pdepl (%rdx), %edi, %ecx # sched: [3:1.00]
+; KNL-NEXT: pdepl %esi, %edi, %eax # sched: [3:1.00]
+; KNL-NEXT: addl %ecx, %eax # sched: [1:0.25]
+; KNL-NEXT: retq # sched: [2:1.00]
;
; ZNVER1-LABEL: test_pdep_i32:
; ZNVER1: # BB#0:
@@ -143,12 +203,26 @@ define i64 @test_pdep_i64(i64 %a0, i64 %
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
-; COMMON-LABEL: test_pdep_i64:
-; COMMON: # BB#0:
-; COMMON-NEXT: pdepq (%rdx), %rdi, %rcx # sched: [3:1.00]
-; COMMON-NEXT: pdepq %rsi, %rdi, %rax # sched: [3:1.00]
-; COMMON-NEXT: addq %rcx, %rax # sched: [1:0.25]
-; COMMON-NEXT: retq # sched: [2:1.00]
+; HASWELL-LABEL: test_pdep_i64:
+; HASWELL: # BB#0:
+; HASWELL-NEXT: pdepq (%rdx), %rdi, %rcx # sched: [3:1.00]
+; HASWELL-NEXT: pdepq %rsi, %rdi, %rax # sched: [3:1.00]
+; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
+; HASWELL-NEXT: retq # sched: [2:1.00]
+;
+; SKYLAKE-LABEL: test_pdep_i64:
+; SKYLAKE: # BB#0:
+; SKYLAKE-NEXT: pdepq (%rdx), %rdi, %rcx # sched: [8:1.00]
+; SKYLAKE-NEXT: pdepq %rsi, %rdi, %rax # sched: [3:1.00]
+; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
+;
+; KNL-LABEL: test_pdep_i64:
+; KNL: # BB#0:
+; KNL-NEXT: pdepq (%rdx), %rdi, %rcx # sched: [3:1.00]
+; KNL-NEXT: pdepq %rsi, %rdi, %rax # sched: [3:1.00]
+; KNL-NEXT: addq %rcx, %rax # sched: [1:0.25]
+; KNL-NEXT: retq # sched: [2:1.00]
;
; ZNVER1-LABEL: test_pdep_i64:
; ZNVER1: # BB#0:
@@ -172,12 +246,26 @@ define i32 @test_pext_i32(i32 %a0, i32 %
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
-; COMMON-LABEL: test_pext_i32:
-; COMMON: # BB#0:
-; COMMON-NEXT: pextl (%rdx), %edi, %ecx # sched: [3:1.00]
-; COMMON-NEXT: pextl %esi, %edi, %eax # sched: [3:1.00]
-; COMMON-NEXT: addl %ecx, %eax # sched: [1:0.25]
-; COMMON-NEXT: retq # sched: [2:1.00]
+; HASWELL-LABEL: test_pext_i32:
+; HASWELL: # BB#0:
+; HASWELL-NEXT: pextl (%rdx), %edi, %ecx # sched: [3:1.00]
+; HASWELL-NEXT: pextl %esi, %edi, %eax # sched: [3:1.00]
+; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
+; HASWELL-NEXT: retq # sched: [2:1.00]
+;
+; SKYLAKE-LABEL: test_pext_i32:
+; SKYLAKE: # BB#0:
+; SKYLAKE-NEXT: pextl (%rdx), %edi, %ecx # sched: [8:1.00]
+; SKYLAKE-NEXT: pextl %esi, %edi, %eax # sched: [3:1.00]
+; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
+;
+; KNL-LABEL: test_pext_i32:
+; KNL: # BB#0:
+; KNL-NEXT: pextl (%rdx), %edi, %ecx # sched: [3:1.00]
+; KNL-NEXT: pextl %esi, %edi, %eax # sched: [3:1.00]
+; KNL-NEXT: addl %ecx, %eax # sched: [1:0.25]
+; KNL-NEXT: retq # sched: [2:1.00]
;
; ZNVER1-LABEL: test_pext_i32:
; ZNVER1: # BB#0:
@@ -201,12 +289,26 @@ define i64 @test_pext_i64(i64 %a0, i64 %
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
-; COMMON-LABEL: test_pext_i64:
-; COMMON: # BB#0:
-; COMMON-NEXT: pextq (%rdx), %rdi, %rcx # sched: [3:1.00]
-; COMMON-NEXT: pextq %rsi, %rdi, %rax # sched: [3:1.00]
-; COMMON-NEXT: addq %rcx, %rax # sched: [1:0.25]
-; COMMON-NEXT: retq # sched: [2:1.00]
+; HASWELL-LABEL: test_pext_i64:
+; HASWELL: # BB#0:
+; HASWELL-NEXT: pextq (%rdx), %rdi, %rcx # sched: [3:1.00]
+; HASWELL-NEXT: pextq %rsi, %rdi, %rax # sched: [3:1.00]
+; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
+; HASWELL-NEXT: retq # sched: [2:1.00]
+;
+; SKYLAKE-LABEL: test_pext_i64:
+; SKYLAKE: # BB#0:
+; SKYLAKE-NEXT: pextq (%rdx), %rdi, %rcx # sched: [8:1.00]
+; SKYLAKE-NEXT: pextq %rsi, %rdi, %rax # sched: [3:1.00]
+; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
+;
+; KNL-LABEL: test_pext_i64:
+; KNL: # BB#0:
+; KNL-NEXT: pextq (%rdx), %rdi, %rcx # sched: [3:1.00]
+; KNL-NEXT: pextq %rsi, %rdi, %rax # sched: [3:1.00]
+; KNL-NEXT: addq %rcx, %rax # sched: [1:0.25]
+; KNL-NEXT: retq # sched: [2:1.00]
;
; ZNVER1-LABEL: test_pext_i64:
; ZNVER1: # BB#0:
@@ -239,10 +341,10 @@ define i32 @test_rorx_i32(i32 %a0, i32 %
;
; SKYLAKE-LABEL: test_rorx_i32:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: rorxl $5, %edi, %ecx # sched: [1:1.00]
-; SKYLAKE-NEXT: rorxl $5, (%rdx), %eax # sched: [1:0.50]
+; SKYLAKE-NEXT: rorxl $5, %edi, %ecx # sched: [1:0.50]
+; SKYLAKE-NEXT: rorxl $5, (%rdx), %eax # sched: [6:0.50]
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_rorx_i32:
; KNL: # BB#0:
@@ -285,10 +387,10 @@ define i64 @test_rorx_i64(i64 %a0, i64 %
;
; SKYLAKE-LABEL: test_rorx_i64:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: rorxq $5, %rdi, %rcx # sched: [1:1.00]
-; SKYLAKE-NEXT: rorxq $5, (%rdx), %rax # sched: [1:0.50]
+; SKYLAKE-NEXT: rorxq $5, %rdi, %rcx # sched: [1:0.50]
+; SKYLAKE-NEXT: rorxq $5, (%rdx), %rax # sched: [6:0.50]
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_rorx_i64:
; KNL: # BB#0:
@@ -331,10 +433,10 @@ define i32 @test_sarx_i32(i32 %a0, i32 %
;
; SKYLAKE-LABEL: test_sarx_i32:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: sarxl %esi, %edi, %ecx # sched: [1:1.00]
-; SKYLAKE-NEXT: sarxl %esi, (%rdx), %eax # sched: [1:0.50]
+; SKYLAKE-NEXT: sarxl %esi, %edi, %ecx # sched: [1:0.50]
+; SKYLAKE-NEXT: sarxl %esi, (%rdx), %eax # sched: [6:0.50]
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_sarx_i32:
; KNL: # BB#0:
@@ -373,10 +475,10 @@ define i64 @test_sarx_i64(i64 %a0, i64 %
;
; SKYLAKE-LABEL: test_sarx_i64:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: sarxq %rsi, %rdi, %rcx # sched: [1:1.00]
-; SKYLAKE-NEXT: sarxq %rsi, (%rdx), %rax # sched: [1:0.50]
+; SKYLAKE-NEXT: sarxq %rsi, %rdi, %rcx # sched: [1:0.50]
+; SKYLAKE-NEXT: sarxq %rsi, (%rdx), %rax # sched: [6:0.50]
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_sarx_i64:
; KNL: # BB#0:
@@ -415,10 +517,10 @@ define i32 @test_shlx_i32(i32 %a0, i32 %
;
; SKYLAKE-LABEL: test_shlx_i32:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: shlxl %esi, %edi, %ecx # sched: [1:1.00]
-; SKYLAKE-NEXT: shlxl %esi, (%rdx), %eax # sched: [1:0.50]
+; SKYLAKE-NEXT: shlxl %esi, %edi, %ecx # sched: [1:0.50]
+; SKYLAKE-NEXT: shlxl %esi, (%rdx), %eax # sched: [6:0.50]
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_shlx_i32:
; KNL: # BB#0:
@@ -457,10 +559,10 @@ define i64 @test_shlx_i64(i64 %a0, i64 %
;
; SKYLAKE-LABEL: test_shlx_i64:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: shlxq %rsi, %rdi, %rcx # sched: [1:1.00]
-; SKYLAKE-NEXT: shlxq %rsi, (%rdx), %rax # sched: [1:0.50]
+; SKYLAKE-NEXT: shlxq %rsi, %rdi, %rcx # sched: [1:0.50]
+; SKYLAKE-NEXT: shlxq %rsi, (%rdx), %rax # sched: [6:0.50]
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_shlx_i64:
; KNL: # BB#0:
@@ -499,10 +601,10 @@ define i32 @test_shrx_i32(i32 %a0, i32 %
;
; SKYLAKE-LABEL: test_shrx_i32:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: shrxl %esi, %edi, %ecx # sched: [1:1.00]
-; SKYLAKE-NEXT: shrxl %esi, (%rdx), %eax # sched: [1:0.50]
+; SKYLAKE-NEXT: shrxl %esi, %edi, %ecx # sched: [1:0.50]
+; SKYLAKE-NEXT: shrxl %esi, (%rdx), %eax # sched: [6:0.50]
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_shrx_i32:
; KNL: # BB#0:
@@ -541,10 +643,10 @@ define i64 @test_shrx_i64(i64 %a0, i64 %
;
; SKYLAKE-LABEL: test_shrx_i64:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: shrxq %rsi, %rdi, %rcx # sched: [1:1.00]
-; SKYLAKE-NEXT: shrxq %rsi, (%rdx), %rax # sched: [1:0.50]
+; SKYLAKE-NEXT: shrxq %rsi, %rdi, %rcx # sched: [1:0.50]
+; SKYLAKE-NEXT: shrxq %rsi, (%rdx), %rax # sched: [6:0.50]
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_shrx_i64:
; KNL: # BB#0:
Modified: llvm/trunk/test/CodeGen/X86/f16c-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/f16c-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/f16c-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/f16c-schedule.ll Mon Oct 16 23:47:04 2017
@@ -30,10 +30,10 @@ define <4 x float> @test_vcvtph2ps_128(<
;
; SKYLAKE-LABEL: test_vcvtph2ps_128:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vcvtph2ps (%rdi), %xmm1 # sched: [4:0.50]
+; SKYLAKE-NEXT: vcvtph2ps (%rdi), %xmm1 # sched: [9:0.50]
; SKYLAKE-NEXT: vcvtph2ps %xmm0, %xmm0 # sched: [5:1.00]
; SKYLAKE-NEXT: vaddps %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_vcvtph2ps_128:
; BTVER2: # BB#0:
@@ -80,10 +80,10 @@ define <8 x float> @test_vcvtph2ps_256(<
;
; SKYLAKE-LABEL: test_vcvtph2ps_256:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vcvtph2ps (%rdi), %ymm1 # sched: [4:0.50]
+; SKYLAKE-NEXT: vcvtph2ps (%rdi), %ymm1 # sched: [10:0.50]
; SKYLAKE-NEXT: vcvtph2ps %xmm0, %ymm0 # sched: [7:1.00]
; SKYLAKE-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_vcvtph2ps_256:
; BTVER2: # BB#0:
@@ -128,8 +128,8 @@ define <8 x i16> @test_vcvtps2ph_128(<4
; SKYLAKE-LABEL: test_vcvtps2ph_128:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvtps2ph $0, %xmm0, %xmm0 # sched: [5:1.00]
-; SKYLAKE-NEXT: vcvtps2ph $0, %xmm1, (%rdi) # sched: [5:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vcvtps2ph $0, %xmm1, (%rdi) # sched: [6:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_vcvtps2ph_128:
; BTVER2: # BB#0:
@@ -175,9 +175,9 @@ define <8 x i16> @test_vcvtps2ph_256(<8
; SKYLAKE-LABEL: test_vcvtps2ph_256:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvtps2ph $0, %ymm0, %xmm0 # sched: [7:1.00]
-; SKYLAKE-NEXT: vcvtps2ph $0, %ymm1, (%rdi) # sched: [7:1.00]
+; SKYLAKE-NEXT: vcvtps2ph $0, %ymm1, (%rdi) # sched: [8:1.00]
; SKYLAKE-NEXT: vzeroupper # sched: [4:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_vcvtps2ph_256:
; BTVER2: # BB#0:
Modified: llvm/trunk/test/CodeGen/X86/fma-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fma-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fma-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fma-schedule.ll Mon Oct 16 23:47:04 2017
@@ -30,8 +30,8 @@ define <2 x double> @test_vfmadd213pd(<2
; SKYLAKE-LABEL: test_vfmadd213pd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfmadd213pd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfmadd213pd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfmadd213pd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfmadd213pd:
; KNL: # BB#0:
@@ -72,8 +72,8 @@ define <4 x double> @test_vfmadd213pd_ym
; SKYLAKE-LABEL: test_vfmadd213pd_ymm:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfmadd213pd %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfmadd213pd (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfmadd213pd (%rdi), %ymm1, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfmadd213pd_ymm:
; KNL: # BB#0:
@@ -114,8 +114,8 @@ define <4 x float> @test_vfmadd213ps(<4
; SKYLAKE-LABEL: test_vfmadd213ps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfmadd213ps (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfmadd213ps (%rdi), %xmm1, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfmadd213ps:
; KNL: # BB#0:
@@ -156,8 +156,8 @@ define <8 x float> @test_vfmadd213ps_ymm
; SKYLAKE-LABEL: test_vfmadd213ps_ymm:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfmadd213ps %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfmadd213ps (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfmadd213ps (%rdi), %ymm1, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfmadd213ps_ymm:
; KNL: # BB#0:
@@ -198,8 +198,8 @@ define <2 x double> @test_vfmadd213sd(<2
; SKYLAKE-LABEL: test_vfmadd213sd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfmadd213sd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfmadd213sd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfmadd213sd (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfmadd213sd:
; KNL: # BB#0:
@@ -240,8 +240,8 @@ define <4 x float> @test_vfmadd213ss(<4
; SKYLAKE-LABEL: test_vfmadd213ss:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfmadd213ss %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfmadd213ss (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfmadd213ss (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfmadd213ss:
; KNL: # BB#0:
@@ -294,8 +294,8 @@ define <2 x double> @test_vfmaddsubpd(<2
; SKYLAKE-LABEL: test_vfmaddsubpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfmaddsub213pd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfmaddsub213pd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfmaddsub213pd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfmaddsubpd:
; KNL: # BB#0:
@@ -336,8 +336,8 @@ define <4 x double> @test_vfmaddsubpd_ym
; SKYLAKE-LABEL: test_vfmaddsubpd_ymm:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfmaddsub213pd %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfmaddsub213pd (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfmaddsub213pd (%rdi), %ymm1, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfmaddsubpd_ymm:
; KNL: # BB#0:
@@ -378,8 +378,8 @@ define <4 x float> @test_vfmaddsubps(<4
; SKYLAKE-LABEL: test_vfmaddsubps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfmaddsub213ps %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfmaddsub213ps (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfmaddsub213ps (%rdi), %xmm1, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfmaddsubps:
; KNL: # BB#0:
@@ -420,8 +420,8 @@ define <8 x float> @test_vfmaddsubps_ymm
; SKYLAKE-LABEL: test_vfmaddsubps_ymm:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfmaddsub213ps %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfmaddsub213ps (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfmaddsub213ps (%rdi), %ymm1, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfmaddsubps_ymm:
; KNL: # BB#0:
@@ -474,8 +474,8 @@ define <2 x double> @test_vfmsubaddpd(<2
; SKYLAKE-LABEL: test_vfmsubaddpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfmsubadd213pd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfmsubadd213pd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfmsubadd213pd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfmsubaddpd:
; KNL: # BB#0:
@@ -516,8 +516,8 @@ define <4 x double> @test_vfmsubaddpd_ym
; SKYLAKE-LABEL: test_vfmsubaddpd_ymm:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfmsubadd213pd %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfmsubadd213pd (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfmsubadd213pd (%rdi), %ymm1, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfmsubaddpd_ymm:
; KNL: # BB#0:
@@ -558,8 +558,8 @@ define <4 x float> @test_vfmsubaddps(<4
; SKYLAKE-LABEL: test_vfmsubaddps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfmsubadd213ps %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfmsubadd213ps (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfmsubadd213ps (%rdi), %xmm1, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfmsubaddps:
; KNL: # BB#0:
@@ -600,8 +600,8 @@ define <8 x float> @test_vfmsubaddps_ymm
; SKYLAKE-LABEL: test_vfmsubaddps_ymm:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfmsubadd213ps %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfmsubadd213ps (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfmsubadd213ps (%rdi), %ymm1, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfmsubaddps_ymm:
; KNL: # BB#0:
@@ -654,8 +654,8 @@ define <2 x double> @test_vfmsub213pd(<2
; SKYLAKE-LABEL: test_vfmsub213pd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfmsub213pd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfmsub213pd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfmsub213pd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfmsub213pd:
; KNL: # BB#0:
@@ -696,8 +696,8 @@ define <4 x double> @test_vfmsub213pd_ym
; SKYLAKE-LABEL: test_vfmsub213pd_ymm:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfmsub213pd %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfmsub213pd (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfmsub213pd (%rdi), %ymm1, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfmsub213pd_ymm:
; KNL: # BB#0:
@@ -738,8 +738,8 @@ define <4 x float> @test_vfmsub213ps(<4
; SKYLAKE-LABEL: test_vfmsub213ps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfmsub213ps %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfmsub213ps (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfmsub213ps (%rdi), %xmm1, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfmsub213ps:
; KNL: # BB#0:
@@ -780,8 +780,8 @@ define <8 x float> @test_vfmsub213ps_ymm
; SKYLAKE-LABEL: test_vfmsub213ps_ymm:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfmsub213ps %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfmsub213ps (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfmsub213ps (%rdi), %ymm1, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfmsub213ps_ymm:
; KNL: # BB#0:
@@ -822,8 +822,8 @@ define <2 x double> @test_vfmsub213sd(<2
; SKYLAKE-LABEL: test_vfmsub213sd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfmsub213sd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfmsub213sd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfmsub213sd (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfmsub213sd:
; KNL: # BB#0:
@@ -864,8 +864,8 @@ define <4 x float> @test_vfmsub213ss(<4
; SKYLAKE-LABEL: test_vfmsub213ss:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfmsub213ss %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfmsub213ss (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfmsub213ss (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfmsub213ss:
; KNL: # BB#0:
@@ -918,8 +918,8 @@ define <2 x double> @test_vfnmadd213pd(<
; SKYLAKE-LABEL: test_vfnmadd213pd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfnmadd213pd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfnmadd213pd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfnmadd213pd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfnmadd213pd:
; KNL: # BB#0:
@@ -960,8 +960,8 @@ define <4 x double> @test_vfnmadd213pd_y
; SKYLAKE-LABEL: test_vfnmadd213pd_ymm:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfnmadd213pd %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfnmadd213pd (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfnmadd213pd (%rdi), %ymm1, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfnmadd213pd_ymm:
; KNL: # BB#0:
@@ -1002,8 +1002,8 @@ define <4 x float> @test_vfnmadd213ps(<4
; SKYLAKE-LABEL: test_vfnmadd213ps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfnmadd213ps %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfnmadd213ps (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfnmadd213ps (%rdi), %xmm1, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfnmadd213ps:
; KNL: # BB#0:
@@ -1044,8 +1044,8 @@ define <8 x float> @test_vfnmadd213ps_ym
; SKYLAKE-LABEL: test_vfnmadd213ps_ymm:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfnmadd213ps %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfnmadd213ps (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfnmadd213ps (%rdi), %ymm1, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfnmadd213ps_ymm:
; KNL: # BB#0:
@@ -1086,8 +1086,8 @@ define <2 x double> @test_vfnmadd213sd(<
; SKYLAKE-LABEL: test_vfnmadd213sd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfnmadd213sd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfnmadd213sd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfnmadd213sd (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfnmadd213sd:
; KNL: # BB#0:
@@ -1128,8 +1128,8 @@ define <4 x float> @test_vfnmadd213ss(<4
; SKYLAKE-LABEL: test_vfnmadd213ss:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfnmadd213ss %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfnmadd213ss (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfnmadd213ss (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfnmadd213ss:
; KNL: # BB#0:
@@ -1182,8 +1182,8 @@ define <2 x double> @test_vfnmsub213pd(<
; SKYLAKE-LABEL: test_vfnmsub213pd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfnmsub213pd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfnmsub213pd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfnmsub213pd (%rdi), %xmm1, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfnmsub213pd:
; KNL: # BB#0:
@@ -1224,8 +1224,8 @@ define <4 x double> @test_vfnmsub213pd_y
; SKYLAKE-LABEL: test_vfnmsub213pd_ymm:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfnmsub213pd %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfnmsub213pd (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfnmsub213pd (%rdi), %ymm1, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfnmsub213pd_ymm:
; KNL: # BB#0:
@@ -1266,8 +1266,8 @@ define <4 x float> @test_vfnmsub213ps(<4
; SKYLAKE-LABEL: test_vfnmsub213ps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfnmsub213ps %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfnmsub213ps (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfnmsub213ps (%rdi), %xmm1, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfnmsub213ps:
; KNL: # BB#0:
@@ -1308,8 +1308,8 @@ define <8 x float> @test_vfnmsub213ps_ym
; SKYLAKE-LABEL: test_vfnmsub213ps_ymm:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfnmsub213ps %ymm2, %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfnmsub213ps (%rdi), %ymm1, %ymm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfnmsub213ps (%rdi), %ymm1, %ymm0 # sched: [11:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfnmsub213ps_ymm:
; KNL: # BB#0:
@@ -1350,8 +1350,8 @@ define <2 x double> @test_vfnmsub213sd(<
; SKYLAKE-LABEL: test_vfnmsub213sd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfnmsub213sd %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfnmsub213sd (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfnmsub213sd (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfnmsub213sd:
; KNL: # BB#0:
@@ -1392,8 +1392,8 @@ define <4 x float> @test_vfnmsub213ss(<4
; SKYLAKE-LABEL: test_vfnmsub213ss:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vfnmsub213ss %xmm2, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vfnmsub213ss (%rdi), %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vfnmsub213ss (%rdi), %xmm1, %xmm0 # sched: [9:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; KNL-LABEL: test_vfnmsub213ss:
; KNL: # BB#0:
Modified: llvm/trunk/test/CodeGen/X86/lea32-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lea32-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/lea32-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/lea32-schedule.ll Mon Oct 16 23:47:04 2017
@@ -51,7 +51,7 @@ define i32 @test_lea_offset(i32) {
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
; SKYLAKE-NEXT: leal -24(%rdi), %eax # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_offset:
; BTVER2: # BB#0:
@@ -109,7 +109,7 @@ define i32 @test_lea_offset_big(i32) {
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
; SKYLAKE-NEXT: leal 1024(%rdi), %eax # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_offset_big:
; BTVER2: # BB#0:
@@ -174,7 +174,7 @@ define i32 @test_lea_add(i32, i32) {
; SKYLAKE-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
; SKYLAKE-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_add:
; BTVER2: # BB#0:
@@ -244,7 +244,7 @@ define i32 @test_lea_add_offset(i32, i32
; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
; SKYLAKE-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]
; SKYLAKE-NEXT: addl $16, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_add_offset:
; BTVER2: # BB#0:
@@ -319,7 +319,7 @@ define i32 @test_lea_add_offset_big(i32,
; SKYLAKE-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50]
; SKYLAKE-NEXT: addl $-4096, %eax # imm = 0xF000
; SKYLAKE-NEXT: # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_add_offset_big:
; BTVER2: # BB#0:
@@ -380,7 +380,7 @@ define i32 @test_lea_mul(i32) {
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
; SKYLAKE-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_mul:
; BTVER2: # BB#0:
@@ -442,7 +442,7 @@ define i32 @test_lea_mul_offset(i32) {
; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
; SKYLAKE-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50]
; SKYLAKE-NEXT: addl $-32, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_mul_offset:
; BTVER2: # BB#0:
@@ -509,7 +509,7 @@ define i32 @test_lea_mul_offset_big(i32)
; SKYLAKE-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50]
; SKYLAKE-NEXT: addl $10000, %eax # imm = 0x2710
; SKYLAKE-NEXT: # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_mul_offset_big:
; BTVER2: # BB#0:
@@ -574,7 +574,7 @@ define i32 @test_lea_add_scale(i32, i32)
; SKYLAKE-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
; SKYLAKE-NEXT: leal (%rdi,%rsi,2), %eax # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_add_scale:
; BTVER2: # BB#0:
@@ -645,7 +645,7 @@ define i32 @test_lea_add_scale_offset(i3
; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
; SKYLAKE-NEXT: leal (%rdi,%rsi,4), %eax # sched: [1:0.50]
; SKYLAKE-NEXT: addl $96, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_add_scale_offset:
; BTVER2: # BB#0:
@@ -721,7 +721,7 @@ define i32 @test_lea_add_scale_offset_bi
; SKYLAKE-NEXT: leal (%rdi,%rsi,8), %eax # sched: [1:0.50]
; SKYLAKE-NEXT: addl $-1200, %eax # imm = 0xFB50
; SKYLAKE-NEXT: # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_add_scale_offset_big:
; BTVER2: # BB#0:
Modified: llvm/trunk/test/CodeGen/X86/lea64-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lea64-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/lea64-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/lea64-schedule.ll Mon Oct 16 23:47:04 2017
@@ -45,7 +45,7 @@ define i64 @test_lea_offset(i64) {
; SKYLAKE-LABEL: test_lea_offset:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: leaq -24(%rdi), %rax # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_offset:
; BTVER2: # BB#0:
@@ -95,7 +95,7 @@ define i64 @test_lea_offset_big(i64) {
; SKYLAKE-LABEL: test_lea_offset_big:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: leaq 1024(%rdi), %rax # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_offset_big:
; BTVER2: # BB#0:
@@ -146,7 +146,7 @@ define i64 @test_lea_add(i64, i64) {
; SKYLAKE-LABEL: test_lea_add:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: leaq (%rdi,%rsi), %rax # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_add:
; BTVER2: # BB#0:
@@ -200,7 +200,7 @@ define i64 @test_lea_add_offset(i64, i64
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: leaq (%rdi,%rsi), %rax # sched: [1:0.50]
; SKYLAKE-NEXT: addq $16, %rax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_add_offset:
; BTVER2: # BB#0:
@@ -259,7 +259,7 @@ define i64 @test_lea_add_offset_big(i64,
; SKYLAKE-NEXT: leaq (%rdi,%rsi), %rax # sched: [1:0.50]
; SKYLAKE-NEXT: addq $-4096, %rax # imm = 0xF000
; SKYLAKE-NEXT: # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_add_offset_big:
; BTVER2: # BB#0:
@@ -310,7 +310,7 @@ define i64 @test_lea_mul(i64) {
; SKYLAKE-LABEL: test_lea_mul:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_mul:
; BTVER2: # BB#0:
@@ -364,7 +364,7 @@ define i64 @test_lea_mul_offset(i64) {
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:0.50]
; SKYLAKE-NEXT: addq $-32, %rax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_mul_offset:
; BTVER2: # BB#0:
@@ -423,7 +423,7 @@ define i64 @test_lea_mul_offset_big(i64)
; SKYLAKE-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:0.50]
; SKYLAKE-NEXT: addq $10000, %rax # imm = 0x2710
; SKYLAKE-NEXT: # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_mul_offset_big:
; BTVER2: # BB#0:
@@ -474,7 +474,7 @@ define i64 @test_lea_add_scale(i64, i64)
; SKYLAKE-LABEL: test_lea_add_scale:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: leaq (%rdi,%rsi,2), %rax # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_add_scale:
; BTVER2: # BB#0:
@@ -529,7 +529,7 @@ define i64 @test_lea_add_scale_offset(i6
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: leaq (%rdi,%rsi,4), %rax # sched: [1:0.50]
; SKYLAKE-NEXT: addq $96, %rax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_add_scale_offset:
; BTVER2: # BB#0:
@@ -589,7 +589,7 @@ define i64 @test_lea_add_scale_offset_bi
; SKYLAKE-NEXT: leaq (%rdi,%rsi,8), %rax # sched: [1:0.50]
; SKYLAKE-NEXT: addq $-1200, %rax # imm = 0xFB50
; SKYLAKE-NEXT: # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_lea_add_scale_offset_big:
; BTVER2: # BB#0:
Modified: llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll Mon Oct 16 23:47:04 2017
@@ -25,11 +25,11 @@ define i16 @test_ctlz_i16(i16 zeroext %a
;
; SKYLAKE-LABEL: test_ctlz_i16:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: lzcntw (%rsi), %cx # sched: [3:1.00]
+; SKYLAKE-NEXT: lzcntw (%rsi), %cx # sched: [8:1.00]
; SKYLAKE-NEXT: lzcntw %di, %ax # sched: [3:1.00]
; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25]
; SKYLAKE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_ctlz_i16:
; BTVER2: # BB#0:
@@ -71,10 +71,10 @@ define i32 @test_ctlz_i32(i32 %a0, i32 *
;
; SKYLAKE-LABEL: test_ctlz_i32:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: lzcntl (%rsi), %ecx # sched: [3:1.00]
+; SKYLAKE-NEXT: lzcntl (%rsi), %ecx # sched: [8:1.00]
; SKYLAKE-NEXT: lzcntl %edi, %eax # sched: [3:1.00]
; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_ctlz_i32:
; BTVER2: # BB#0:
@@ -114,10 +114,10 @@ define i64 @test_ctlz_i64(i64 %a0, i64 *
;
; SKYLAKE-LABEL: test_ctlz_i64:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: lzcntq (%rsi), %rcx # sched: [3:1.00]
+; SKYLAKE-NEXT: lzcntq (%rsi), %rcx # sched: [8:1.00]
; SKYLAKE-NEXT: lzcntq %rdi, %rax # sched: [3:1.00]
; SKYLAKE-NEXT: orq %rcx, %rax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_ctlz_i64:
; BTVER2: # BB#0:
Modified: llvm/trunk/test/CodeGen/X86/movbe-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/movbe-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/movbe-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/movbe-schedule.ll Mon Oct 16 23:47:04 2017
@@ -39,9 +39,9 @@ define i16 @test_movbe_i16(i16 *%a0, i16
;
; SKYLAKE-LABEL: test_movbe_i16:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: movbew (%rdi), %ax # sched: [1:0.50]
-; SKYLAKE-NEXT: movbew %si, (%rdx) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: movbew (%rdi), %ax # sched: [6:0.50]
+; SKYLAKE-NEXT: movbew %si, (%rdx) # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_movbe_i16:
; BTVER2: # BB#0:
@@ -93,9 +93,9 @@ define i32 @test_movbe_i32(i32 *%a0, i32
;
; SKYLAKE-LABEL: test_movbe_i32:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: movbel (%rdi), %eax # sched: [1:0.50]
-; SKYLAKE-NEXT: movbel %esi, (%rdx) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: movbel (%rdi), %eax # sched: [6:0.50]
+; SKYLAKE-NEXT: movbel %esi, (%rdx) # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_movbe_i32:
; BTVER2: # BB#0:
@@ -147,9 +147,9 @@ define i64 @test_movbe_i64(i64 *%a0, i64
;
; SKYLAKE-LABEL: test_movbe_i64:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: movbeq (%rdi), %rax # sched: [1:0.50]
-; SKYLAKE-NEXT: movbeq %rsi, (%rdx) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: movbeq (%rdi), %rax # sched: [6:0.50]
+; SKYLAKE-NEXT: movbeq %rsi, (%rdx) # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_movbe_i64:
; BTVER2: # BB#0:
Modified: llvm/trunk/test/CodeGen/X86/popcnt-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/popcnt-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/popcnt-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/popcnt-schedule.ll Mon Oct 16 23:47:04 2017
@@ -45,11 +45,11 @@ define i16 @test_ctpop_i16(i16 zeroext %
;
; SKYLAKE-LABEL: test_ctpop_i16:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: popcntw (%rsi), %cx # sched: [3:1.00]
+; SKYLAKE-NEXT: popcntw (%rsi), %cx # sched: [8:1.00]
; SKYLAKE-NEXT: popcntw %di, %ax # sched: [3:1.00]
; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25]
; SKYLAKE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_ctpop_i16:
; BTVER2: # BB#0:
@@ -105,10 +105,10 @@ define i32 @test_ctpop_i32(i32 %a0, i32
;
; SKYLAKE-LABEL: test_ctpop_i32:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: popcntl (%rsi), %ecx # sched: [3:1.00]
+; SKYLAKE-NEXT: popcntl (%rsi), %ecx # sched: [8:1.00]
; SKYLAKE-NEXT: popcntl %edi, %eax # sched: [3:1.00]
; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_ctpop_i32:
; BTVER2: # BB#0:
@@ -162,10 +162,10 @@ define i64 @test_ctpop_i64(i64 %a0, i64
;
; SKYLAKE-LABEL: test_ctpop_i64:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: popcntq (%rsi), %rcx # sched: [3:1.00]
+; SKYLAKE-NEXT: popcntq (%rsi), %rcx # sched: [8:1.00]
; SKYLAKE-NEXT: popcntq %rdi, %rax # sched: [3:1.00]
; SKYLAKE-NEXT: orq %rcx, %rax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_ctpop_i64:
; BTVER2: # BB#0:
Modified: llvm/trunk/test/CodeGen/X86/sse-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse-schedule.ll Mon Oct 16 23:47:04 2017
@@ -44,8 +44,8 @@ define <4 x float> @test_addps(<4 x floa
; SKYLAKE-LABEL: test_addps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vaddps (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vaddps (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_addps:
; SKX: # BB#0:
@@ -104,8 +104,8 @@ define float @test_addss(float %a0, floa
; SKYLAKE-LABEL: test_addss:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vaddss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vaddss (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vaddss (%rdi), %xmm0, %xmm0 # sched: [9:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_addss:
; SKX: # BB#0:
@@ -167,9 +167,9 @@ define <4 x float> @test_andps(<4 x floa
;
; SKYLAKE-LABEL: test_andps:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vandps %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vandps (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vandps %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vandps (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_andps:
; SKX: # BB#0:
@@ -235,9 +235,9 @@ define <4 x float> @test_andnotps(<4 x f
;
; SKYLAKE-LABEL: test_andnotps:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vandnps %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vandnps (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vandnps %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vandnps (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_andnotps:
; SKX: # BB#0:
@@ -307,9 +307,9 @@ define <4 x float> @test_cmpps(<4 x floa
; SKYLAKE-LABEL: test_cmpps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcmpeqps %xmm1, %xmm0, %xmm1 # sched: [4:0.33]
-; SKYLAKE-NEXT: vcmpeqps (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vorps %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vcmpeqps (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: vorps %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cmpps:
; SKX: # BB#0:
@@ -376,7 +376,7 @@ define float @test_cmpss(float %a0, floa
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcmpeqss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; SKYLAKE-NEXT: vcmpeqss (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cmpss:
; SKX: # BB#0:
@@ -480,16 +480,16 @@ define i32 @test_comiss(<4 x float> %a0,
; SKYLAKE-LABEL: test_comiss:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcomiss %xmm1, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: setnp %al # sched: [1:1.00]
-; SKYLAKE-NEXT: sete %cl # sched: [1:1.00]
+; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]
+; SKYLAKE-NEXT: sete %cl # sched: [1:0.50]
; SKYLAKE-NEXT: andb %al, %cl # sched: [1:0.25]
; SKYLAKE-NEXT: vcomiss (%rdi), %xmm0 # sched: [8:1.00]
-; SKYLAKE-NEXT: setnp %al # sched: [1:1.00]
-; SKYLAKE-NEXT: sete %dl # sched: [1:1.00]
+; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]
+; SKYLAKE-NEXT: sete %dl # sched: [1:0.50]
; SKYLAKE-NEXT: andb %al, %dl # sched: [1:0.25]
; SKYLAKE-NEXT: orb %cl, %dl # sched: [1:0.25]
; SKYLAKE-NEXT: movzbl %dl, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_comiss:
; SKX: # BB#0:
@@ -581,7 +581,7 @@ define float @test_cvtsi2ss(i32 %a0, i32
; SKYLAKE-NEXT: vcvtsi2ssl %edi, %xmm0, %xmm0 # sched: [5:1.00]
; SKYLAKE-NEXT: vcvtsi2ssl (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
; SKYLAKE-NEXT: vaddss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvtsi2ss:
; SKX: # BB#0:
@@ -651,7 +651,7 @@ define float @test_cvtsi2ssq(i64 %a0, i6
; SKYLAKE-NEXT: vcvtsi2ssq %rdi, %xmm0, %xmm0 # sched: [6:2.00]
; SKYLAKE-NEXT: vcvtsi2ssq (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
; SKYLAKE-NEXT: vaddss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvtsi2ssq:
; SKX: # BB#0:
@@ -719,9 +719,9 @@ define i32 @test_cvtss2si(float %a0, flo
; SKYLAKE-LABEL: test_cvtss2si:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvtss2si %xmm0, %ecx # sched: [6:1.00]
-; SKYLAKE-NEXT: vcvtss2si (%rdi), %eax # sched: [6:1.00]
+; SKYLAKE-NEXT: vcvtss2si (%rdi), %eax # sched: [11:1.00]
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvtss2si:
; SKX: # BB#0:
@@ -792,9 +792,9 @@ define i64 @test_cvtss2siq(float %a0, fl
; SKYLAKE-LABEL: test_cvtss2siq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvtss2si %xmm0, %rcx # sched: [6:1.00]
-; SKYLAKE-NEXT: vcvtss2si (%rdi), %rax # sched: [6:1.00]
+; SKYLAKE-NEXT: vcvtss2si (%rdi), %rax # sched: [11:1.00]
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvtss2siq:
; SKX: # BB#0:
@@ -865,9 +865,9 @@ define i32 @test_cvttss2si(float %a0, fl
; SKYLAKE-LABEL: test_cvttss2si:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvttss2si %xmm0, %ecx # sched: [7:1.00]
-; SKYLAKE-NEXT: vcvttss2si (%rdi), %eax # sched: [6:1.00]
+; SKYLAKE-NEXT: vcvttss2si (%rdi), %eax # sched: [11:1.00]
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvttss2si:
; SKX: # BB#0:
@@ -935,9 +935,9 @@ define i64 @test_cvttss2siq(float %a0, f
; SKYLAKE-LABEL: test_cvttss2siq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvttss2si %xmm0, %rcx # sched: [7:1.00]
-; SKYLAKE-NEXT: vcvttss2si (%rdi), %rax # sched: [6:1.00]
+; SKYLAKE-NEXT: vcvttss2si (%rdi), %rax # sched: [11:1.00]
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvttss2siq:
; SKX: # BB#0:
@@ -1000,8 +1000,8 @@ define <4 x float> @test_divps(<4 x floa
; SKYLAKE-LABEL: test_divps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vdivps %xmm1, %xmm0, %xmm0 # sched: [11:1.00]
-; SKYLAKE-NEXT: vdivps (%rdi), %xmm0, %xmm0 # sched: [11:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vdivps (%rdi), %xmm0, %xmm0 # sched: [17:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_divps:
; SKX: # BB#0:
@@ -1060,8 +1060,8 @@ define float @test_divss(float %a0, floa
; SKYLAKE-LABEL: test_divss:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vdivss %xmm1, %xmm0, %xmm0 # sched: [11:1.00]
-; SKYLAKE-NEXT: vdivss (%rdi), %xmm0, %xmm0 # sched: [11:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vdivss (%rdi), %xmm0, %xmm0 # sched: [16:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_divss:
; SKX: # BB#0:
@@ -1120,8 +1120,8 @@ define void @test_ldmxcsr(i32 %a0) {
; SKYLAKE-LABEL: test_ldmxcsr:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: movl %edi, -{{[0-9]+}}(%rsp) # sched: [1:1.00]
-; SKYLAKE-NEXT: vldmxcsr -{{[0-9]+}}(%rsp) # sched: [2:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vldmxcsr -{{[0-9]+}}(%rsp) # sched: [7:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_ldmxcsr:
; SKX: # BB#0:
@@ -1182,8 +1182,8 @@ define <4 x float> @test_maxps(<4 x floa
; SKYLAKE-LABEL: test_maxps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmaxps %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vmaxps (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vmaxps (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_maxps:
; SKX: # BB#0:
@@ -1243,8 +1243,8 @@ define <4 x float> @test_maxss(<4 x floa
; SKYLAKE-LABEL: test_maxss:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmaxss %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vmaxss (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vmaxss (%rdi), %xmm0, %xmm0 # sched: [9:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_maxss:
; SKX: # BB#0:
@@ -1304,8 +1304,8 @@ define <4 x float> @test_minps(<4 x floa
; SKYLAKE-LABEL: test_minps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vminps %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vminps (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vminps (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_minps:
; SKX: # BB#0:
@@ -1365,8 +1365,8 @@ define <4 x float> @test_minss(<4 x floa
; SKYLAKE-LABEL: test_minss:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vminss %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vminss (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vminss (%rdi), %xmm0, %xmm0 # sched: [9:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_minss:
; SKX: # BB#0:
@@ -1430,10 +1430,10 @@ define void @test_movaps(<4 x float> *%a
;
; SKYLAKE-LABEL: test_movaps:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmovaps (%rdi), %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vmovaps (%rdi), %xmm0 # sched: [6:0.50]
; SKYLAKE-NEXT: vaddps %xmm0, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmovaps %xmm0, (%rsi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movaps:
; SKX: # BB#0:
@@ -1498,7 +1498,7 @@ define <4 x float> @test_movhlps(<4 x fl
; SKYLAKE-LABEL: test_movhlps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movhlps:
; SKX: # BB#0:
@@ -1560,10 +1560,10 @@ define void @test_movhps(<4 x float> %a0
;
; SKYLAKE-LABEL: test_movhps:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [1:1.00]
+; SKYLAKE-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [6:1.00]
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vpextrq $1, %xmm0, (%rdi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpextrq $1, %xmm0, (%rdi) # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movhps:
; SKX: # BB#0:
@@ -1632,7 +1632,7 @@ define <4 x float> @test_movlhps(<4 x fl
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] sched: [1:1.00]
; SKYLAKE-NEXT: vaddps %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movlhps:
; SKX: # BB#0:
@@ -1694,10 +1694,10 @@ define void @test_movlps(<4 x float> %a0
;
; SKYLAKE-LABEL: test_movlps:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmovlpd {{.*#+}} xmm1 = mem[0],xmm1[1] sched: [1:1.00]
+; SKYLAKE-NEXT: vmovlpd {{.*#+}} xmm1 = mem[0],xmm1[1] sched: [6:1.00]
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmovlps %xmm0, (%rdi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movlps:
; SKX: # BB#0:
@@ -1760,7 +1760,7 @@ define i32 @test_movmskps(<4 x float> %a
; SKYLAKE-LABEL: test_movmskps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmovmskps %xmm0, %eax # sched: [2:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movmskps:
; SKX: # BB#0:
@@ -1816,7 +1816,7 @@ define void @test_movntps(<4 x float> %a
; SKYLAKE-LABEL: test_movntps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmovntps %xmm0, (%rdi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movntps:
; SKX: # BB#0:
@@ -1874,10 +1874,10 @@ define void @test_movss_mem(float* %a0,
;
; SKYLAKE-LABEL: test_movss_mem:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero sched: [1:0.50]
+; SKYLAKE-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero sched: [5:0.50]
; SKYLAKE-NEXT: vaddss %xmm0, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmovss %xmm0, (%rsi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movss_mem:
; SKX: # BB#0:
@@ -1939,8 +1939,8 @@ define <4 x float> @test_movss_reg(<4 x
;
; SKYLAKE-LABEL: test_movss_reg:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movss_reg:
; SKX: # BB#0:
@@ -1998,10 +1998,10 @@ define void @test_movups(<4 x float> *%a
;
; SKYLAKE-LABEL: test_movups:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmovups (%rdi), %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vmovups (%rdi), %xmm0 # sched: [6:0.50]
; SKYLAKE-NEXT: vaddps %xmm0, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmovups %xmm0, (%rsi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movups:
; SKX: # BB#0:
@@ -2063,8 +2063,8 @@ define <4 x float> @test_mulps(<4 x floa
; SKYLAKE-LABEL: test_mulps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmulps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vmulps (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vmulps (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_mulps:
; SKX: # BB#0:
@@ -2123,8 +2123,8 @@ define float @test_mulss(float %a0, floa
; SKYLAKE-LABEL: test_mulss:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmulss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vmulss (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vmulss (%rdi), %xmm0, %xmm0 # sched: [9:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_mulss:
; SKX: # BB#0:
@@ -2186,9 +2186,9 @@ define <4 x float> @test_orps(<4 x float
;
; SKYLAKE-LABEL: test_orps:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vorps %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vorps (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vorps %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vorps (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_orps:
; SKX: # BB#0:
@@ -2251,8 +2251,8 @@ define void @test_prefetchnta(i8* %a0) {
;
; SKYLAKE-LABEL: test_prefetchnta:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: prefetchnta (%rdi) # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: prefetchnta (%rdi) # sched: [5:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_prefetchnta:
; SKX: # BB#0:
@@ -2314,9 +2314,9 @@ define <4 x float> @test_rcpps(<4 x floa
; SKYLAKE-LABEL: test_rcpps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vrcpps %xmm0, %xmm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: vrcpps (%rdi), %xmm1 # sched: [4:1.00]
+; SKYLAKE-NEXT: vrcpps (%rdi), %xmm1 # sched: [10:1.00]
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_rcpps:
; SKX: # BB#0:
@@ -2392,10 +2392,10 @@ define <4 x float> @test_rcpss(float %a0
; SKYLAKE-LABEL: test_rcpss:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vrcpss %xmm0, %xmm0, %xmm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [1:0.50]
+; SKYLAKE-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [5:0.50]
; SKYLAKE-NEXT: vrcpss %xmm1, %xmm1, %xmm1 # sched: [4:1.00]
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_rcpss:
; SKX: # BB#0:
@@ -2471,9 +2471,9 @@ define <4 x float> @test_rsqrtps(<4 x fl
; SKYLAKE-LABEL: test_rsqrtps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vrsqrtps %xmm0, %xmm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: vrsqrtps (%rdi), %xmm1 # sched: [4:1.00]
+; SKYLAKE-NEXT: vrsqrtps (%rdi), %xmm1 # sched: [10:1.00]
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_rsqrtps:
; SKX: # BB#0:
@@ -2549,10 +2549,10 @@ define <4 x float> @test_rsqrtss(float %
; SKYLAKE-LABEL: test_rsqrtss:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vrsqrtss %xmm0, %xmm0, %xmm0 # sched: [4:1.00]
-; SKYLAKE-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [1:0.50]
+; SKYLAKE-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [5:0.50]
; SKYLAKE-NEXT: vrsqrtss %xmm1, %xmm1, %xmm1 # sched: [4:1.00]
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_rsqrtss:
; SKX: # BB#0:
@@ -2621,8 +2621,8 @@ define void @test_sfence() {
;
; SKYLAKE-LABEL: test_sfence:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: sfence # sched: [1:0.33]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: sfence # sched: [2:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_sfence:
; SKX: # BB#0:
@@ -2681,8 +2681,8 @@ define <4 x float> @test_shufps(<4 x flo
; SKYLAKE-LABEL: test_shufps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0] sched: [1:1.00]
-; SKYLAKE-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,3],mem[0,0] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,3],mem[0,0] sched: [7:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_shufps:
; SKX: # BB#0:
@@ -2747,9 +2747,9 @@ define <4 x float> @test_sqrtps(<4 x flo
; SKYLAKE-LABEL: test_sqrtps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vsqrtps %xmm0, %xmm0 # sched: [12:1.00]
-; SKYLAKE-NEXT: vsqrtps (%rdi), %xmm1 # sched: [12:1.00]
+; SKYLAKE-NEXT: vsqrtps (%rdi), %xmm1 # sched: [18:1.00]
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_sqrtps:
; SKX: # BB#0:
@@ -2825,10 +2825,10 @@ define <4 x float> @test_sqrtss(<4 x flo
; SKYLAKE-LABEL: test_sqrtss:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [12:1.00]
-; SKYLAKE-NEXT: vmovaps (%rdi), %xmm1 # sched: [1:0.50]
+; SKYLAKE-NEXT: vmovaps (%rdi), %xmm1 # sched: [6:0.50]
; SKYLAKE-NEXT: vsqrtss %xmm1, %xmm1, %xmm1 # sched: [12:1.00]
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_sqrtss:
; SKX: # BB#0:
@@ -2894,9 +2894,9 @@ define i32 @test_stmxcsr() {
;
; SKYLAKE-LABEL: test_stmxcsr:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vstmxcsr -{{[0-9]+}}(%rsp) # sched: [1:1.00]
-; SKYLAKE-NEXT: movl -{{[0-9]+}}(%rsp), %eax # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vstmxcsr -{{[0-9]+}}(%rsp) # sched: [2:1.00]
+; SKYLAKE-NEXT: movl -{{[0-9]+}}(%rsp), %eax # sched: [5:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_stmxcsr:
; SKX: # BB#0:
@@ -2957,8 +2957,8 @@ define <4 x float> @test_subps(<4 x floa
; SKYLAKE-LABEL: test_subps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vsubps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vsubps (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vsubps (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_subps:
; SKX: # BB#0:
@@ -3017,8 +3017,8 @@ define float @test_subss(float %a0, floa
; SKYLAKE-LABEL: test_subss:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vsubss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vsubss (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vsubss (%rdi), %xmm0, %xmm0 # sched: [9:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_subss:
; SKX: # BB#0:
@@ -3117,16 +3117,16 @@ define i32 @test_ucomiss(<4 x float> %a0
; SKYLAKE-LABEL: test_ucomiss:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vucomiss %xmm1, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: setnp %al # sched: [1:1.00]
-; SKYLAKE-NEXT: sete %cl # sched: [1:1.00]
+; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]
+; SKYLAKE-NEXT: sete %cl # sched: [1:0.50]
; SKYLAKE-NEXT: andb %al, %cl # sched: [1:0.25]
; SKYLAKE-NEXT: vucomiss (%rdi), %xmm0 # sched: [8:1.00]
-; SKYLAKE-NEXT: setnp %al # sched: [1:1.00]
-; SKYLAKE-NEXT: sete %dl # sched: [1:1.00]
+; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]
+; SKYLAKE-NEXT: sete %dl # sched: [1:0.50]
; SKYLAKE-NEXT: andb %al, %dl # sched: [1:0.25]
; SKYLAKE-NEXT: orb %cl, %dl # sched: [1:0.25]
; SKYLAKE-NEXT: movzbl %dl, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_ucomiss:
; SKX: # BB#0:
@@ -3215,8 +3215,8 @@ define <4 x float> @test_unpckhps(<4 x f
; SKYLAKE-LABEL: test_unpckhps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vunpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3] sched: [1:1.00]
-; SKYLAKE-NEXT: vunpckhps {{.*#+}} xmm0 = xmm0[2],mem[2],xmm0[3],mem[3] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vunpckhps {{.*#+}} xmm0 = xmm0[2],mem[2],xmm0[3],mem[3] sched: [7:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_unpckhps:
; SKX: # BB#0:
@@ -3279,8 +3279,8 @@ define <4 x float> @test_unpcklps(<4 x f
; SKYLAKE-LABEL: test_unpcklps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] sched: [1:1.00]
-; SKYLAKE-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] sched: [7:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_unpcklps:
; SKX: # BB#0:
@@ -3342,9 +3342,9 @@ define <4 x float> @test_xorps(<4 x floa
;
; SKYLAKE-LABEL: test_xorps:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vxorps %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vxorps (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vxorps %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vxorps (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_xorps:
; SKX: # BB#0:
Modified: llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse2-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse2-schedule.ll Mon Oct 16 23:47:04 2017
@@ -44,8 +44,8 @@ define <2 x double> @test_addpd(<2 x dou
; SKYLAKE-LABEL: test_addpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vaddpd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vaddpd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_addpd:
; SKX: # BB#0:
@@ -104,8 +104,8 @@ define double @test_addsd(double %a0, do
; SKYLAKE-LABEL: test_addsd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vaddsd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vaddsd (%rdi), %xmm0, %xmm0 # sched: [9:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_addsd:
; SKX: # BB#0:
@@ -168,10 +168,10 @@ define <2 x double> @test_andpd(<2 x dou
;
; SKYLAKE-LABEL: test_andpd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vandpd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vandpd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vandpd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vandpd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
; SKYLAKE-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_andpd:
; SKX: # BB#0:
@@ -242,10 +242,10 @@ define <2 x double> @test_andnotpd(<2 x
;
; SKYLAKE-LABEL: test_andnotpd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vandnpd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vandnpd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vandnpd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vandnpd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
; SKYLAKE-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_andnotpd:
; SKX: # BB#0:
@@ -319,9 +319,9 @@ define <2 x double> @test_cmppd(<2 x dou
; SKYLAKE-LABEL: test_cmppd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm1 # sched: [4:0.33]
-; SKYLAKE-NEXT: vcmpeqpd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vorpd %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vcmpeqpd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: vorpd %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cmppd:
; SKX: # BB#0:
@@ -388,7 +388,7 @@ define double @test_cmpsd(double %a0, do
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; SKYLAKE-NEXT: vcmpeqsd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cmpsd:
; SKX: # BB#0:
@@ -492,16 +492,16 @@ define i32 @test_comisd(<2 x double> %a0
; SKYLAKE-LABEL: test_comisd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcomisd %xmm1, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: setnp %al # sched: [1:1.00]
-; SKYLAKE-NEXT: sete %cl # sched: [1:1.00]
+; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]
+; SKYLAKE-NEXT: sete %cl # sched: [1:0.50]
; SKYLAKE-NEXT: andb %al, %cl # sched: [1:0.25]
; SKYLAKE-NEXT: vcomisd (%rdi), %xmm0 # sched: [8:1.00]
-; SKYLAKE-NEXT: setnp %al # sched: [1:1.00]
-; SKYLAKE-NEXT: sete %dl # sched: [1:1.00]
+; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]
+; SKYLAKE-NEXT: sete %dl # sched: [1:0.50]
; SKYLAKE-NEXT: andb %al, %dl # sched: [1:0.25]
; SKYLAKE-NEXT: orb %cl, %dl # sched: [1:0.25]
; SKYLAKE-NEXT: movzbl %dl, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_comisd:
; SKX: # BB#0:
@@ -591,9 +591,9 @@ define <2 x double> @test_cvtdq2pd(<4 x
; SKYLAKE-LABEL: test_cvtdq2pd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvtdq2pd %xmm0, %xmm0 # sched: [5:1.00]
-; SKYLAKE-NEXT: vcvtdq2pd (%rdi), %xmm1 # sched: [5:1.00]
+; SKYLAKE-NEXT: vcvtdq2pd (%rdi), %xmm1 # sched: [11:1.00]
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvtdq2pd:
; SKX: # BB#0:
@@ -664,9 +664,9 @@ define <4 x float> @test_cvtdq2ps(<4 x i
; SKYLAKE-LABEL: test_cvtdq2ps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvtdq2ps %xmm0, %xmm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vcvtdq2ps (%rdi), %xmm1 # sched: [4:0.50]
+; SKYLAKE-NEXT: vcvtdq2ps (%rdi), %xmm1 # sched: [10:0.50]
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvtdq2ps:
; SKX: # BB#0:
@@ -736,8 +736,8 @@ define <4 x i32> @test_cvtpd2dq(<2 x dou
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvtpd2dq %xmm0, %xmm0 # sched: [5:1.00]
; SKYLAKE-NEXT: vcvtpd2dqx (%rdi), %xmm1 # sched: [8:1.00]
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvtpd2dq:
; SKX: # BB#0:
@@ -809,7 +809,7 @@ define <4 x float> @test_cvtpd2ps(<2 x d
; SKYLAKE-NEXT: vcvtpd2ps %xmm0, %xmm0 # sched: [5:1.00]
; SKYLAKE-NEXT: vcvtpd2psx (%rdi), %xmm1 # sched: [8:1.00]
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvtpd2ps:
; SKX: # BB#0:
@@ -879,9 +879,9 @@ define <4 x i32> @test_cvtps2dq(<4 x flo
; SKYLAKE-LABEL: test_cvtps2dq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvtps2dq %xmm0, %xmm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vcvtps2dq (%rdi), %xmm1 # sched: [4:0.50]
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vcvtps2dq (%rdi), %xmm1 # sched: [10:0.50]
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvtps2dq:
; SKX: # BB#0:
@@ -951,9 +951,9 @@ define <2 x double> @test_cvtps2pd(<4 x
; SKYLAKE-LABEL: test_cvtps2pd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvtps2pd %xmm0, %xmm0 # sched: [5:1.00]
-; SKYLAKE-NEXT: vcvtps2pd (%rdi), %xmm1 # sched: [4:0.50]
+; SKYLAKE-NEXT: vcvtps2pd (%rdi), %xmm1 # sched: [9:0.50]
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvtps2pd:
; SKX: # BB#0:
@@ -1023,9 +1023,9 @@ define i32 @test_cvtsd2si(double %a0, do
; SKYLAKE-LABEL: test_cvtsd2si:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvtsd2si %xmm0, %ecx # sched: [6:1.00]
-; SKYLAKE-NEXT: vcvtsd2si (%rdi), %eax # sched: [6:1.00]
+; SKYLAKE-NEXT: vcvtsd2si (%rdi), %eax # sched: [11:1.00]
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvtsd2si:
; SKX: # BB#0:
@@ -1096,9 +1096,9 @@ define i64 @test_cvtsd2siq(double %a0, d
; SKYLAKE-LABEL: test_cvtsd2siq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvtsd2si %xmm0, %rcx # sched: [6:1.00]
-; SKYLAKE-NEXT: vcvtsd2si (%rdi), %rax # sched: [6:1.00]
+; SKYLAKE-NEXT: vcvtsd2si (%rdi), %rax # sched: [11:1.00]
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvtsd2siq:
; SKX: # BB#0:
@@ -1175,10 +1175,10 @@ define float @test_cvtsd2ss(double %a0,
; SKYLAKE-LABEL: test_cvtsd2ss:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvtsd2ss %xmm0, %xmm0, %xmm0 # sched: [5:1.00]
-; SKYLAKE-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero sched: [1:0.50]
+; SKYLAKE-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero sched: [5:0.50]
; SKYLAKE-NEXT: vcvtsd2ss %xmm1, %xmm1, %xmm1 # sched: [5:1.00]
; SKYLAKE-NEXT: vaddss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvtsd2ss:
; SKX: # BB#0:
@@ -1251,7 +1251,7 @@ define double @test_cvtsi2sd(i32 %a0, i3
; SKYLAKE-NEXT: vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [5:1.00]
; SKYLAKE-NEXT: vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
; SKYLAKE-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvtsi2sd:
; SKX: # BB#0:
@@ -1321,7 +1321,7 @@ define double @test_cvtsi2sdq(i64 %a0, i
; SKYLAKE-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0 # sched: [5:1.00]
; SKYLAKE-NEXT: vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
; SKYLAKE-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvtsi2sdq:
; SKX: # BB#0:
@@ -1397,10 +1397,10 @@ define double @test_cvtss2sd(float %a0,
; SKYLAKE-LABEL: test_cvtss2sd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvtss2sd %xmm0, %xmm0, %xmm0 # sched: [5:1.00]
-; SKYLAKE-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [1:0.50]
+; SKYLAKE-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [5:0.50]
; SKYLAKE-NEXT: vcvtss2sd %xmm1, %xmm1, %xmm1 # sched: [5:1.00]
; SKYLAKE-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvtss2sd:
; SKX: # BB#0:
@@ -1473,8 +1473,8 @@ define <4 x i32> @test_cvttpd2dq(<2 x do
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvttpd2dq %xmm0, %xmm0 # sched: [5:1.00]
; SKYLAKE-NEXT: vcvttpd2dqx (%rdi), %xmm1 # sched: [8:1.00]
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvttpd2dq:
; SKX: # BB#0:
@@ -1545,9 +1545,9 @@ define <4 x i32> @test_cvttps2dq(<4 x fl
; SKYLAKE-LABEL: test_cvttps2dq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvttps2dq %xmm0, %xmm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vcvttps2dq (%rdi), %xmm1 # sched: [4:0.50]
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vcvttps2dq (%rdi), %xmm1 # sched: [10:0.50]
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvttps2dq:
; SKX: # BB#0:
@@ -1615,9 +1615,9 @@ define i32 @test_cvttsd2si(double %a0, d
; SKYLAKE-LABEL: test_cvttsd2si:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvttsd2si %xmm0, %ecx # sched: [6:1.00]
-; SKYLAKE-NEXT: vcvttsd2si (%rdi), %eax # sched: [6:1.00]
+; SKYLAKE-NEXT: vcvttsd2si (%rdi), %eax # sched: [11:1.00]
; SKYLAKE-NEXT: addl %ecx, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvttsd2si:
; SKX: # BB#0:
@@ -1685,9 +1685,9 @@ define i64 @test_cvttsd2siq(double %a0,
; SKYLAKE-LABEL: test_cvttsd2siq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vcvttsd2si %xmm0, %rcx # sched: [6:1.00]
-; SKYLAKE-NEXT: vcvttsd2si (%rdi), %rax # sched: [6:1.00]
+; SKYLAKE-NEXT: vcvttsd2si (%rdi), %rax # sched: [11:1.00]
; SKYLAKE-NEXT: addq %rcx, %rax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cvttsd2siq:
; SKX: # BB#0:
@@ -1750,8 +1750,8 @@ define <2 x double> @test_divpd(<2 x dou
; SKYLAKE-LABEL: test_divpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vdivpd %xmm1, %xmm0, %xmm0 # sched: [14:1.00]
-; SKYLAKE-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [14:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vdivpd (%rdi), %xmm0, %xmm0 # sched: [20:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_divpd:
; SKX: # BB#0:
@@ -1810,8 +1810,8 @@ define double @test_divsd(double %a0, do
; SKYLAKE-LABEL: test_divsd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vdivsd %xmm1, %xmm0, %xmm0 # sched: [14:1.00]
-; SKYLAKE-NEXT: vdivsd (%rdi), %xmm0, %xmm0 # sched: [14:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vdivsd (%rdi), %xmm0, %xmm0 # sched: [19:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_divsd:
; SKX: # BB#0:
@@ -1871,7 +1871,7 @@ define void @test_lfence() {
; SKYLAKE-LABEL: test_lfence:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: lfence # sched: [2:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_lfence:
; SKX: # BB#0:
@@ -1926,8 +1926,8 @@ define void @test_mfence() {
;
; SKYLAKE-LABEL: test_mfence:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: mfence # sched: [2:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: mfence # sched: [3:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_mfence:
; SKX: # BB#0:
@@ -1980,8 +1980,8 @@ define void @test_maskmovdqu(<16 x i8> %
;
; SKYLAKE-LABEL: test_maskmovdqu:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmaskmovdqu %xmm1, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vmaskmovdqu %xmm1, %xmm0 # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_maskmovdqu:
; SKX: # BB#0:
@@ -2036,8 +2036,8 @@ define <2 x double> @test_maxpd(<2 x dou
; SKYLAKE-LABEL: test_maxpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmaxpd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vmaxpd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vmaxpd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_maxpd:
; SKX: # BB#0:
@@ -2097,8 +2097,8 @@ define <2 x double> @test_maxsd(<2 x dou
; SKYLAKE-LABEL: test_maxsd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmaxsd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vmaxsd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vmaxsd (%rdi), %xmm0, %xmm0 # sched: [9:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_maxsd:
; SKX: # BB#0:
@@ -2158,8 +2158,8 @@ define <2 x double> @test_minpd(<2 x dou
; SKYLAKE-LABEL: test_minpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vminpd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vminpd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vminpd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_minpd:
; SKX: # BB#0:
@@ -2219,8 +2219,8 @@ define <2 x double> @test_minsd(<2 x dou
; SKYLAKE-LABEL: test_minsd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vminsd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vminsd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vminsd (%rdi), %xmm0, %xmm0 # sched: [9:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_minsd:
; SKX: # BB#0:
@@ -2284,10 +2284,10 @@ define void @test_movapd(<2 x double> *%
;
; SKYLAKE-LABEL: test_movapd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmovapd (%rdi), %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vmovapd (%rdi), %xmm0 # sched: [6:0.50]
; SKYLAKE-NEXT: vaddpd %xmm0, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmovapd %xmm0, (%rsi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movapd:
; SKX: # BB#0:
@@ -2353,10 +2353,10 @@ define void @test_movdqa(<2 x i64> *%a0,
;
; SKYLAKE-LABEL: test_movdqa:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmovdqa (%rdi), %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vmovdqa (%rdi), %xmm0 # sched: [6:0.50]
+; SKYLAKE-NEXT: vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.33]
; SKYLAKE-NEXT: vmovdqa %xmm0, (%rsi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movdqa:
; SKX: # BB#0:
@@ -2422,10 +2422,10 @@ define void @test_movdqu(<2 x i64> *%a0,
;
; SKYLAKE-LABEL: test_movdqu:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmovdqu (%rdi), %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vmovdqu (%rdi), %xmm0 # sched: [6:0.50]
+; SKYLAKE-NEXT: vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.33]
; SKYLAKE-NEXT: vmovdqu %xmm0, (%rsi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movdqu:
; SKX: # BB#0:
@@ -2507,12 +2507,12 @@ define i32 @test_movd(<4 x i32> %a0, i32
; SKYLAKE-LABEL: test_movd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmovd %edi, %xmm1 # sched: [1:1.00]
-; SKYLAKE-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddd %xmm2, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero sched: [5:0.50]
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm1 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpaddd %xmm2, %xmm0, %xmm0 # sched: [1:0.33]
; SKYLAKE-NEXT: vmovd %xmm0, %eax # sched: [2:1.00]
; SKYLAKE-NEXT: vmovd %xmm1, (%rsi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movd:
; SKX: # BB#0:
@@ -2608,12 +2608,12 @@ define i64 @test_movd_64(<2 x i64> %a0,
; SKYLAKE-LABEL: test_movd_64:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmovq %rdi, %xmm1 # sched: [1:1.00]
-; SKYLAKE-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddq %xmm2, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero sched: [5:0.50]
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm1 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpaddq %xmm2, %xmm0, %xmm0 # sched: [1:0.33]
; SKYLAKE-NEXT: vmovq %xmm0, %rax # sched: [2:1.00]
; SKYLAKE-NEXT: vmovq %xmm1, (%rsi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movd_64:
; SKX: # BB#0:
@@ -2693,10 +2693,10 @@ define void @test_movhpd(<2 x double> %a
;
; SKYLAKE-LABEL: test_movhpd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [1:1.00]
+; SKYLAKE-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [6:1.00]
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmovhpd %xmm0, (%rdi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movhpd:
; SKX: # BB#0:
@@ -2765,10 +2765,10 @@ define void @test_movlpd(<2 x double> %a
;
; SKYLAKE-LABEL: test_movlpd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmovlpd {{.*#+}} xmm1 = mem[0],xmm1[1] sched: [1:1.00]
+; SKYLAKE-NEXT: vmovlpd {{.*#+}} xmm1 = mem[0],xmm1[1] sched: [6:1.00]
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmovlpd %xmm0, (%rdi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movlpd:
; SKX: # BB#0:
@@ -2830,7 +2830,7 @@ define i32 @test_movmskpd(<2 x double> %
; SKYLAKE-LABEL: test_movmskpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmovmskpd %xmm0, %eax # sched: [2:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movmskpd:
; SKX: # BB#0:
@@ -2886,9 +2886,9 @@ define void @test_movntdqa(<2 x i64> %a0
;
; SKYLAKE-LABEL: test_movntdqa:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpaddq %xmm0, %xmm0, %xmm0 # sched: [1:0.33]
; SKYLAKE-NEXT: vmovntdq %xmm0, (%rdi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movntdqa:
; SKX: # BB#0:
@@ -2947,7 +2947,7 @@ define void @test_movntpd(<2 x double> %
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vaddpd %xmm0, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmovntpd %xmm0, (%rdi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movntpd:
; SKX: # BB#0:
@@ -3009,10 +3009,10 @@ define <2 x i64> @test_movq_mem(<2 x i64
;
; SKYLAKE-LABEL: test_movq_mem:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero sched: [5:0.50]
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
; SKYLAKE-NEXT: vmovq %xmm0, (%rdi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movq_mem:
; SKX: # BB#0:
@@ -3077,9 +3077,9 @@ define <2 x i64> @test_movq_reg(<2 x i64
;
; SKYLAKE-LABEL: test_movq_reg:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddq %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero sched: [1:0.33]
+; SKYLAKE-NEXT: vpaddq %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movq_reg:
; SKX: # BB#0:
@@ -3141,10 +3141,10 @@ define void @test_movsd_mem(double* %a0,
;
; SKYLAKE-LABEL: test_movsd_mem:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero sched: [1:0.50]
+; SKYLAKE-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero sched: [5:0.50]
; SKYLAKE-NEXT: vaddsd %xmm0, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmovsd %xmm0, (%rsi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movsd_mem:
; SKX: # BB#0:
@@ -3208,7 +3208,7 @@ define <2 x double> @test_movsd_reg(<2 x
; SKYLAKE-LABEL: test_movsd_reg:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmovlhps {{.*#+}} xmm0 = xmm1[0],xmm0[0] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movsd_reg:
; SKX: # BB#0:
@@ -3266,10 +3266,10 @@ define void @test_movupd(<2 x double> *%
;
; SKYLAKE-LABEL: test_movupd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmovupd (%rdi), %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vmovupd (%rdi), %xmm0 # sched: [6:0.50]
; SKYLAKE-NEXT: vaddpd %xmm0, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmovupd %xmm0, (%rsi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movupd:
; SKX: # BB#0:
@@ -3331,8 +3331,8 @@ define <2 x double> @test_mulpd(<2 x dou
; SKYLAKE-LABEL: test_mulpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmulpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vmulpd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vmulpd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_mulpd:
; SKX: # BB#0:
@@ -3391,8 +3391,8 @@ define double @test_mulsd(double %a0, do
; SKYLAKE-LABEL: test_mulsd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmulsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vmulsd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vmulsd (%rdi), %xmm0, %xmm0 # sched: [9:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_mulsd:
; SKX: # BB#0:
@@ -3455,10 +3455,10 @@ define <2 x double> @test_orpd(<2 x doub
;
; SKYLAKE-LABEL: test_orpd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vorpd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vorpd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vorpd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vorpd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
; SKYLAKE-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_orpd:
; SKX: # BB#0:
@@ -3529,8 +3529,8 @@ define <8 x i16> @test_packssdw(<4 x i32
; SKYLAKE-LABEL: test_packssdw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpackssdw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpackssdw (%rdi), %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpackssdw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_packssdw:
; SKX: # BB#0:
@@ -3595,8 +3595,8 @@ define <16 x i8> @test_packsswb(<8 x i16
; SKYLAKE-LABEL: test_packsswb:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpacksswb (%rdi), %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpacksswb (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_packsswb:
; SKX: # BB#0:
@@ -3661,8 +3661,8 @@ define <16 x i8> @test_packuswb(<8 x i16
; SKYLAKE-LABEL: test_packuswb:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpackuswb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpackuswb (%rdi), %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpackuswb (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_packuswb:
; SKX: # BB#0:
@@ -3726,9 +3726,9 @@ define <16 x i8> @test_paddb(<16 x i8> %
;
; SKYLAKE-LABEL: test_paddb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpaddb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpaddb %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpaddb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_paddb:
; SKX: # BB#0:
@@ -3790,9 +3790,9 @@ define <4 x i32> @test_paddd(<4 x i32> %
;
; SKYLAKE-LABEL: test_paddd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpaddd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_paddd:
; SKX: # BB#0:
@@ -3850,9 +3850,9 @@ define <2 x i64> @test_paddq(<2 x i64> %
;
; SKYLAKE-LABEL: test_paddq:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpaddq (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_paddq:
; SKX: # BB#0:
@@ -3914,9 +3914,9 @@ define <16 x i8> @test_paddsb(<16 x i8>
;
; SKYLAKE-LABEL: test_paddsb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpaddsb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddsb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpaddsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpaddsb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_paddsb:
; SKX: # BB#0:
@@ -3979,9 +3979,9 @@ define <8 x i16> @test_paddsw(<8 x i16>
;
; SKYLAKE-LABEL: test_paddsw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpaddsw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddsw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpaddsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpaddsw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_paddsw:
; SKX: # BB#0:
@@ -4044,9 +4044,9 @@ define <16 x i8> @test_paddusb(<16 x i8>
;
; SKYLAKE-LABEL: test_paddusb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpaddusb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddusb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpaddusb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpaddusb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_paddusb:
; SKX: # BB#0:
@@ -4109,9 +4109,9 @@ define <8 x i16> @test_paddusw(<8 x i16>
;
; SKYLAKE-LABEL: test_paddusw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpaddusw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddusw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpaddusw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpaddusw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_paddusw:
; SKX: # BB#0:
@@ -4174,9 +4174,9 @@ define <8 x i16> @test_paddw(<8 x i16> %
;
; SKYLAKE-LABEL: test_paddw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpaddw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_paddw:
; SKX: # BB#0:
@@ -4239,10 +4239,10 @@ define <2 x i64> @test_pand(<2 x i64> %a
;
; SKYLAKE-LABEL: test_pand:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpand %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpand (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpand %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpand (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pand:
; SKX: # BB#0:
@@ -4315,10 +4315,10 @@ define <2 x i64> @test_pandn(<2 x i64> %
;
; SKYLAKE-LABEL: test_pandn:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpandn %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpandn (%rdi), %xmm0, %xmm1 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpandn %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpandn (%rdi), %xmm0, %xmm1 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pandn:
; SKX: # BB#0:
@@ -4386,9 +4386,9 @@ define <16 x i8> @test_pavgb(<16 x i8> %
;
; SKYLAKE-LABEL: test_pavgb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpavgb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpavgb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpavgb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpavgb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pavgb:
; SKX: # BB#0:
@@ -4460,9 +4460,9 @@ define <8 x i16> @test_pavgw(<8 x i16> %
;
; SKYLAKE-LABEL: test_pavgw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpavgw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpavgw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpavgw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpavgw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pavgw:
; SKX: # BB#0:
@@ -4537,10 +4537,10 @@ define <16 x i8> @test_pcmpeqb(<16 x i8>
;
; SKYLAKE-LABEL: test_pcmpeqb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm1 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpcmpeqb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpcmpeqb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pcmpeqb:
; SKX: # BB#0:
@@ -4611,10 +4611,10 @@ define <4 x i32> @test_pcmpeqd(<4 x i32>
;
; SKYLAKE-LABEL: test_pcmpeqd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm1 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pcmpeqd:
; SKX: # BB#0:
@@ -4685,10 +4685,10 @@ define <8 x i16> @test_pcmpeqw(<8 x i16>
;
; SKYLAKE-LABEL: test_pcmpeqw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm1 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpcmpeqw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpcmpeqw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pcmpeqw:
; SKX: # BB#0:
@@ -4760,10 +4760,10 @@ define <16 x i8> @test_pcmpgtb(<16 x i8>
;
; SKYLAKE-LABEL: test_pcmpgtb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm1 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpcmpgtb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpcmpgtb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pcmpgtb:
; SKX: # BB#0:
@@ -4835,10 +4835,10 @@ define <4 x i32> @test_pcmpgtd(<4 x i32>
;
; SKYLAKE-LABEL: test_pcmpgtd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm1 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpcmpeqd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pcmpgtd:
; SKX: # BB#0:
@@ -4910,10 +4910,10 @@ define <8 x i16> @test_pcmpgtw(<8 x i16>
;
; SKYLAKE-LABEL: test_pcmpgtw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm1 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpcmpgtw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm1 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpcmpgtw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpor %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pcmpgtw:
; SKX: # BB#0:
@@ -4979,7 +4979,7 @@ define i16 @test_pextrw(<8 x i16> %a0) {
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpextrw $6, %xmm0, %eax # sched: [3:1.00]
; SKYLAKE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pextrw:
; SKX: # BB#0:
@@ -5040,8 +5040,8 @@ define <8 x i16> @test_pinsrw(<8 x i16>
; SKYLAKE-LABEL: test_pinsrw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0 # sched: [2:2.00]
-; SKYLAKE-NEXT: vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [6:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pinsrw:
; SKX: # BB#0:
@@ -5108,8 +5108,8 @@ define <4 x i32> @test_pmaddwd(<8 x i16>
; SKYLAKE-LABEL: test_pmaddwd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vpmaddwd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmaddwd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaddwd:
; SKX: # BB#0:
@@ -5173,9 +5173,9 @@ define <8 x i16> @test_pmaxsw(<8 x i16>
;
; SKYLAKE-LABEL: test_pmaxsw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpmaxsw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpmaxsw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaxsw:
; SKX: # BB#0:
@@ -5238,9 +5238,9 @@ define <16 x i8> @test_pmaxub(<16 x i8>
;
; SKYLAKE-LABEL: test_pmaxub:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpmaxub (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpmaxub (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaxub:
; SKX: # BB#0:
@@ -5303,9 +5303,9 @@ define <8 x i16> @test_pminsw(<8 x i16>
;
; SKYLAKE-LABEL: test_pminsw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpminsw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpminsw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpminsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpminsw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pminsw:
; SKX: # BB#0:
@@ -5368,9 +5368,9 @@ define <16 x i8> @test_pminub(<16 x i8>
;
; SKYLAKE-LABEL: test_pminub:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpminub %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpminub (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpminub %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpminub (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pminub:
; SKX: # BB#0:
@@ -5427,7 +5427,7 @@ define i32 @test_pmovmskb(<16 x i8> %a0)
; SKYLAKE-LABEL: test_pmovmskb:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovmskb %xmm0, %eax # sched: [2:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovmskb:
; SKX: # BB#0:
@@ -5482,8 +5482,8 @@ define <8 x i16> @test_pmulhuw(<8 x i16>
; SKYLAKE-LABEL: test_pmulhuw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmulhuw %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vpmulhuw (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmulhuw (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmulhuw:
; SKX: # BB#0:
@@ -5543,8 +5543,8 @@ define <8 x i16> @test_pmulhw(<8 x i16>
; SKYLAKE-LABEL: test_pmulhw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmulhw %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vpmulhw (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmulhw (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmulhw:
; SKX: # BB#0:
@@ -5604,8 +5604,8 @@ define <8 x i16> @test_pmullw(<8 x i16>
; SKYLAKE-LABEL: test_pmullw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmullw %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vpmullw (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmullw (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmullw:
; SKX: # BB#0:
@@ -5672,8 +5672,8 @@ define <2 x i64> @test_pmuludq(<4 x i32>
; SKYLAKE-LABEL: test_pmuludq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmuludq %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vpmuludq (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmuludq (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmuludq:
; SKX: # BB#0:
@@ -5738,10 +5738,10 @@ define <2 x i64> @test_por(<2 x i64> %a0
;
; SKYLAKE-LABEL: test_por:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpor (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpor (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_por:
; SKX: # BB#0:
@@ -5812,8 +5812,8 @@ define <2 x i64> @test_psadbw(<16 x i8>
; SKYLAKE-LABEL: test_psadbw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpsadbw (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsadbw (%rdi), %xmm0, %xmm0 # sched: [9:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psadbw:
; SKX: # BB#0:
@@ -5881,9 +5881,9 @@ define <4 x i32> @test_pshufd(<4 x i32>
; SKYLAKE-LABEL: test_pshufd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,3,2] sched: [1:1.00]
-; SKYLAKE-NEXT: vpshufd {{.*#+}} xmm1 = mem[3,2,1,0] sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpshufd {{.*#+}} xmm1 = mem[3,2,1,0] sched: [7:1.00]
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pshufd:
; SKX: # BB#0:
@@ -5953,9 +5953,9 @@ define <8 x i16> @test_pshufhw(<8 x i16>
; SKYLAKE-LABEL: test_pshufhw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] sched: [1:1.00]
-; SKYLAKE-NEXT: vpshufhw {{.*#+}} xmm1 = mem[0,1,2,3,7,6,5,4] sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpshufhw {{.*#+}} xmm1 = mem[0,1,2,3,7,6,5,4] sched: [7:1.00]
+; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pshufhw:
; SKX: # BB#0:
@@ -6025,9 +6025,9 @@ define <8 x i16> @test_pshuflw(<8 x i16>
; SKYLAKE-LABEL: test_pshuflw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] sched: [1:1.00]
-; SKYLAKE-NEXT: vpshuflw {{.*#+}} xmm1 = mem[3,2,1,0,4,5,6,7] sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpshuflw {{.*#+}} xmm1 = mem[3,2,1,0,4,5,6,7] sched: [7:1.00]
+; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pshuflw:
; SKX: # BB#0:
@@ -6095,9 +6095,9 @@ define <4 x i32> @test_pslld(<4 x i32> %
; SKYLAKE-LABEL: test_pslld:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpslld %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT: vpslld (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpslld $2, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpslld (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpslld $2, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pslld:
; SKX: # BB#0:
@@ -6163,7 +6163,7 @@ define <4 x i32> @test_pslldq(<4 x i32>
; SKYLAKE-LABEL: test_pslldq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pslldq:
; SKX: # BB#0:
@@ -6222,9 +6222,9 @@ define <2 x i64> @test_psllq(<2 x i64> %
; SKYLAKE-LABEL: test_psllq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpsllq %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT: vpsllq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsllq $2, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsllq (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpsllq $2, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psllq:
; SKX: # BB#0:
@@ -6294,9 +6294,9 @@ define <8 x i16> @test_psllw(<8 x i16> %
; SKYLAKE-LABEL: test_psllw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpsllw %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT: vpsllw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsllw $2, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsllw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpsllw $2, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psllw:
; SKX: # BB#0:
@@ -6366,9 +6366,9 @@ define <4 x i32> @test_psrad(<4 x i32> %
; SKYLAKE-LABEL: test_psrad:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpsrad %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT: vpsrad (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsrad $2, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsrad (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpsrad $2, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psrad:
; SKX: # BB#0:
@@ -6438,9 +6438,9 @@ define <8 x i16> @test_psraw(<8 x i16> %
; SKYLAKE-LABEL: test_psraw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpsraw %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT: vpsraw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsraw $2, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsraw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpsraw $2, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psraw:
; SKX: # BB#0:
@@ -6510,9 +6510,9 @@ define <4 x i32> @test_psrld(<4 x i32> %
; SKYLAKE-LABEL: test_psrld:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpsrld %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT: vpsrld (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsrld $2, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsrld (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpsrld $2, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psrld:
; SKX: # BB#0:
@@ -6578,7 +6578,7 @@ define <4 x i32> @test_psrldq(<4 x i32>
; SKYLAKE-LABEL: test_psrldq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[4,5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psrldq:
; SKX: # BB#0:
@@ -6637,9 +6637,9 @@ define <2 x i64> @test_psrlq(<2 x i64> %
; SKYLAKE-LABEL: test_psrlq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpsrlq %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT: vpsrlq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsrlq $2, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsrlq (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpsrlq $2, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psrlq:
; SKX: # BB#0:
@@ -6709,9 +6709,9 @@ define <8 x i16> @test_psrlw(<8 x i16> %
; SKYLAKE-LABEL: test_psrlw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
-; SKYLAKE-NEXT: vpsrlw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsrlw $2, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsrlw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpsrlw $2, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psrlw:
; SKX: # BB#0:
@@ -6779,9 +6779,9 @@ define <16 x i8> @test_psubb(<16 x i8> %
;
; SKYLAKE-LABEL: test_psubb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsubb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsubb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsubb %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpsubb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psubb:
; SKX: # BB#0:
@@ -6843,9 +6843,9 @@ define <4 x i32> @test_psubd(<4 x i32> %
;
; SKYLAKE-LABEL: test_psubd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsubd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsubd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsubd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpsubd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psubd:
; SKX: # BB#0:
@@ -6903,9 +6903,9 @@ define <2 x i64> @test_psubq(<2 x i64> %
;
; SKYLAKE-LABEL: test_psubq:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsubq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsubq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsubq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpsubq (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psubq:
; SKX: # BB#0:
@@ -6967,9 +6967,9 @@ define <16 x i8> @test_psubsb(<16 x i8>
;
; SKYLAKE-LABEL: test_psubsb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsubsb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsubsb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsubsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsubsb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psubsb:
; SKX: # BB#0:
@@ -7032,9 +7032,9 @@ define <8 x i16> @test_psubsw(<8 x i16>
;
; SKYLAKE-LABEL: test_psubsw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsubsw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsubsw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsubsw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsubsw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psubsw:
; SKX: # BB#0:
@@ -7097,9 +7097,9 @@ define <16 x i8> @test_psubusb(<16 x i8>
;
; SKYLAKE-LABEL: test_psubusb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsubusb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsubusb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psubusb:
; SKX: # BB#0:
@@ -7162,9 +7162,9 @@ define <8 x i16> @test_psubusw(<8 x i16>
;
; SKYLAKE-LABEL: test_psubusw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsubusw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsubusw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsubusw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsubusw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psubusw:
; SKX: # BB#0:
@@ -7227,9 +7227,9 @@ define <8 x i16> @test_psubw(<8 x i16> %
;
; SKYLAKE-LABEL: test_psubw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsubw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpsubw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsubw %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpsubw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psubw:
; SKX: # BB#0:
@@ -7292,8 +7292,8 @@ define <16 x i8> @test_punpckhbw(<16 x i
; SKYLAKE-LABEL: test_punpckhbw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] sched: [1:1.00]
-; SKYLAKE-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8],mem[8],xmm0[9],mem[9],xmm0[10],mem[10],xmm0[11],mem[11],xmm0[12],mem[12],xmm0[13],mem[13],xmm0[14],mem[14],xmm0[15],mem[15] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8],mem[8],xmm0[9],mem[9],xmm0[10],mem[10],xmm0[11],mem[11],xmm0[12],mem[12],xmm0[13],mem[13],xmm0[14],mem[14],xmm0[15],mem[15] sched: [7:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_punpckhbw:
; SKX: # BB#0:
@@ -7359,9 +7359,9 @@ define <4 x i32> @test_punpckhdq(<4 x i3
; SKYLAKE-LABEL: test_punpckhdq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpunpckhdq {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3] sched: [1:1.00]
-; SKYLAKE-NEXT: vpunpckhdq {{.*#+}} xmm1 = xmm1[2],mem[2],xmm1[3],mem[3] sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpunpckhdq {{.*#+}} xmm1 = xmm1[2],mem[2],xmm1[3],mem[3] sched: [7:1.00]
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_punpckhdq:
; SKX: # BB#0:
@@ -7429,9 +7429,9 @@ define <2 x i64> @test_punpckhqdq(<2 x i
; SKYLAKE-LABEL: test_punpckhqdq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1] sched: [1:1.00]
-; SKYLAKE-NEXT: vpunpckhqdq {{.*#+}} xmm1 = xmm1[1],mem[1] sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpunpckhqdq {{.*#+}} xmm1 = xmm1[1],mem[1] sched: [7:1.00]
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_punpckhqdq:
; SKX: # BB#0:
@@ -7498,8 +7498,8 @@ define <8 x i16> @test_punpckhwd(<8 x i1
; SKYLAKE-LABEL: test_punpckhwd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] sched: [1:1.00]
-; SKYLAKE-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],mem[4],xmm0[5],mem[5],xmm0[6],mem[6],xmm0[7],mem[7] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],mem[4],xmm0[5],mem[5],xmm0[6],mem[6],xmm0[7],mem[7] sched: [7:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_punpckhwd:
; SKX: # BB#0:
@@ -7562,8 +7562,8 @@ define <16 x i8> @test_punpcklbw(<16 x i
; SKYLAKE-LABEL: test_punpcklbw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] sched: [1:1.00]
-; SKYLAKE-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3],xmm0[4],mem[4],xmm0[5],mem[5],xmm0[6],mem[6],xmm0[7],mem[7] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3],xmm0[4],mem[4],xmm0[5],mem[5],xmm0[6],mem[6],xmm0[7],mem[7] sched: [7:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_punpcklbw:
; SKX: # BB#0:
@@ -7629,9 +7629,9 @@ define <4 x i32> @test_punpckldq(<4 x i3
; SKYLAKE-LABEL: test_punpckldq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] sched: [1:1.00]
-; SKYLAKE-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1] sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1] sched: [7:1.00]
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_punpckldq:
; SKX: # BB#0:
@@ -7699,9 +7699,9 @@ define <2 x i64> @test_punpcklqdq(<2 x i
; SKYLAKE-LABEL: test_punpcklqdq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] sched: [1:1.00]
-; SKYLAKE-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],mem[0] sched: [7:1.00]
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_punpcklqdq:
; SKX: # BB#0:
@@ -7768,8 +7768,8 @@ define <8 x i16> @test_punpcklwd(<8 x i1
; SKYLAKE-LABEL: test_punpcklwd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] sched: [1:1.00]
-; SKYLAKE-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3] sched: [7:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_punpcklwd:
; SKX: # BB#0:
@@ -7832,10 +7832,10 @@ define <2 x i64> @test_pxor(<2 x i64> %a
;
; SKYLAKE-LABEL: test_pxor:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpxor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpxor (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpxor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vpxor (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pxor:
; SKX: # BB#0:
@@ -7903,9 +7903,9 @@ define <2 x double> @test_shufpd(<2 x do
; SKYLAKE-LABEL: test_shufpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1],xmm1[0] sched: [1:1.00]
-; SKYLAKE-NEXT: vshufpd {{.*#+}} xmm1 = xmm1[1],mem[0] sched: [1:1.00]
+; SKYLAKE-NEXT: vshufpd {{.*#+}} xmm1 = xmm1[1],mem[0] sched: [7:1.00]
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_shufpd:
; SKX: # BB#0:
@@ -7974,9 +7974,9 @@ define <2 x double> @test_sqrtpd(<2 x do
; SKYLAKE-LABEL: test_sqrtpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vsqrtpd %xmm0, %xmm0 # sched: [18:1.00]
-; SKYLAKE-NEXT: vsqrtpd (%rdi), %xmm1 # sched: [18:1.00]
+; SKYLAKE-NEXT: vsqrtpd (%rdi), %xmm1 # sched: [24:1.00]
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_sqrtpd:
; SKX: # BB#0:
@@ -8052,10 +8052,10 @@ define <2 x double> @test_sqrtsd(<2 x do
; SKYLAKE-LABEL: test_sqrtsd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [18:1.00]
-; SKYLAKE-NEXT: vmovapd (%rdi), %xmm1 # sched: [1:0.50]
+; SKYLAKE-NEXT: vmovapd (%rdi), %xmm1 # sched: [6:0.50]
; SKYLAKE-NEXT: vsqrtsd %xmm1, %xmm1, %xmm1 # sched: [18:1.00]
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_sqrtsd:
; SKX: # BB#0:
@@ -8122,8 +8122,8 @@ define <2 x double> @test_subpd(<2 x dou
; SKYLAKE-LABEL: test_subpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vsubpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vsubpd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vsubpd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_subpd:
; SKX: # BB#0:
@@ -8182,8 +8182,8 @@ define double @test_subsd(double %a0, do
; SKYLAKE-LABEL: test_subsd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vsubsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vsubsd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vsubsd (%rdi), %xmm0, %xmm0 # sched: [9:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_subsd:
; SKX: # BB#0:
@@ -8282,16 +8282,16 @@ define i32 @test_ucomisd(<2 x double> %a
; SKYLAKE-LABEL: test_ucomisd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vucomisd %xmm1, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: setnp %al # sched: [1:1.00]
-; SKYLAKE-NEXT: sete %cl # sched: [1:1.00]
+; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]
+; SKYLAKE-NEXT: sete %cl # sched: [1:0.50]
; SKYLAKE-NEXT: andb %al, %cl # sched: [1:0.25]
; SKYLAKE-NEXT: vucomisd (%rdi), %xmm0 # sched: [8:1.00]
-; SKYLAKE-NEXT: setnp %al # sched: [1:1.00]
-; SKYLAKE-NEXT: sete %dl # sched: [1:1.00]
+; SKYLAKE-NEXT: setnp %al # sched: [1:0.50]
+; SKYLAKE-NEXT: sete %dl # sched: [1:0.50]
; SKYLAKE-NEXT: andb %al, %dl # sched: [1:0.25]
; SKYLAKE-NEXT: orb %cl, %dl # sched: [1:0.25]
; SKYLAKE-NEXT: movzbl %dl, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_ucomisd:
; SKX: # BB#0:
@@ -8381,9 +8381,9 @@ define <2 x double> @test_unpckhpd(<2 x
; SKYLAKE-LABEL: test_unpckhpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] sched: [1:1.00]
-; SKYLAKE-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm1[1],mem[1] sched: [1:1.00]
+; SKYLAKE-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm1[1],mem[1] sched: [7:1.00]
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_unpckhpd:
; SKX: # BB#0:
@@ -8457,9 +8457,9 @@ define <2 x double> @test_unpcklpd(<2 x
; SKYLAKE-LABEL: test_unpcklpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] sched: [1:1.00]
-; SKYLAKE-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm0[0],mem[0] sched: [1:1.00]
+; SKYLAKE-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm0[0],mem[0] sched: [7:1.00]
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_unpcklpd:
; SKX: # BB#0:
@@ -8526,10 +8526,10 @@ define <2 x double> @test_xorpd(<2 x dou
;
; SKYLAKE-LABEL: test_xorpd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vxorpd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: vxorpd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vxorpd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: vxorpd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
; SKYLAKE-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_xorpd:
; SKX: # BB#0:
Modified: llvm/trunk/test/CodeGen/X86/sse3-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse3-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse3-schedule.ll Mon Oct 16 23:47:04 2017
@@ -44,8 +44,8 @@ define <2 x double> @test_addsubpd(<2 x
; SKYLAKE-LABEL: test_addsubpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vaddsubpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vaddsubpd (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vaddsubpd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_addsubpd:
; SKX: # BB#0:
@@ -105,8 +105,8 @@ define <4 x float> @test_addsubps(<4 x f
; SKYLAKE-LABEL: test_addsubps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vaddsubps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vaddsubps (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vaddsubps (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_addsubps:
; SKX: # BB#0:
@@ -166,8 +166,8 @@ define <2 x double> @test_haddpd(<2 x do
; SKYLAKE-LABEL: test_haddpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vhaddpd %xmm1, %xmm0, %xmm0 # sched: [6:2.00]
-; SKYLAKE-NEXT: vhaddpd (%rdi), %xmm0, %xmm0 # sched: [6:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vhaddpd (%rdi), %xmm0, %xmm0 # sched: [12:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_haddpd:
; SKX: # BB#0:
@@ -227,8 +227,8 @@ define <4 x float> @test_haddps(<4 x flo
; SKYLAKE-LABEL: test_haddps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vhaddps %xmm1, %xmm0, %xmm0 # sched: [6:2.00]
-; SKYLAKE-NEXT: vhaddps (%rdi), %xmm0, %xmm0 # sched: [6:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vhaddps (%rdi), %xmm0, %xmm0 # sched: [12:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_haddps:
; SKX: # BB#0:
@@ -288,8 +288,8 @@ define <2 x double> @test_hsubpd(<2 x do
; SKYLAKE-LABEL: test_hsubpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vhsubpd %xmm1, %xmm0, %xmm0 # sched: [6:2.00]
-; SKYLAKE-NEXT: vhsubpd (%rdi), %xmm0, %xmm0 # sched: [6:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vhsubpd (%rdi), %xmm0, %xmm0 # sched: [12:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_hsubpd:
; SKX: # BB#0:
@@ -349,8 +349,8 @@ define <4 x float> @test_hsubps(<4 x flo
; SKYLAKE-LABEL: test_hsubps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vhsubps %xmm1, %xmm0, %xmm0 # sched: [6:2.00]
-; SKYLAKE-NEXT: vhsubps (%rdi), %xmm0, %xmm0 # sched: [6:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vhsubps (%rdi), %xmm0, %xmm0 # sched: [12:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_hsubps:
; SKX: # BB#0:
@@ -406,8 +406,8 @@ define <16 x i8> @test_lddqu(i8* %a0) {
;
; SKYLAKE-LABEL: test_lddqu:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vlddqu (%rdi), %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vlddqu (%rdi), %xmm0 # sched: [6:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_lddqu:
; SKX: # BB#0:
@@ -469,7 +469,7 @@ define void @test_monitor(i8* %a0, i32 %
; SKYLAKE-NEXT: leaq (%rdi), %rax # sched: [1:0.50]
; SKYLAKE-NEXT: movl %esi, %ecx # sched: [1:0.25]
; SKYLAKE-NEXT: monitor # sched: [100:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_monitor:
; SKX: # BB#0:
@@ -536,9 +536,9 @@ define <2 x double> @test_movddup(<2 x d
; SKYLAKE-LABEL: test_movddup:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0] sched: [1:1.00]
-; SKYLAKE-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0] sched: [1:0.50]
+; SKYLAKE-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0] sched: [5:0.50]
; SKYLAKE-NEXT: vsubpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movddup:
; SKX: # BB#0:
@@ -607,9 +607,9 @@ define <4 x float> @test_movshdup(<4 x f
; SKYLAKE-LABEL: test_movshdup:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] sched: [1:1.00]
-; SKYLAKE-NEXT: vmovshdup {{.*#+}} xmm1 = mem[1,1,3,3] sched: [1:0.50]
+; SKYLAKE-NEXT: vmovshdup {{.*#+}} xmm1 = mem[1,1,3,3] sched: [6:0.50]
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movshdup:
; SKX: # BB#0:
@@ -678,9 +678,9 @@ define <4 x float> @test_movsldup(<4 x f
; SKYLAKE-LABEL: test_movsldup:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2] sched: [1:1.00]
-; SKYLAKE-NEXT: vmovsldup {{.*#+}} xmm1 = mem[0,0,2,2] sched: [1:0.50]
+; SKYLAKE-NEXT: vmovsldup {{.*#+}} xmm1 = mem[0,0,2,2] sched: [6:0.50]
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movsldup:
; SKX: # BB#0:
@@ -750,7 +750,7 @@ define void @test_mwait(i32 %a0, i32 %a1
; SKYLAKE-NEXT: movl %edi, %ecx # sched: [1:0.25]
; SKYLAKE-NEXT: movl %esi, %eax # sched: [1:0.25]
; SKYLAKE-NEXT: mwait # sched: [20:2.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_mwait:
; SKX: # BB#0:
Modified: llvm/trunk/test/CodeGen/X86/sse41-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse41-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse41-schedule.ll Mon Oct 16 23:47:04 2017
@@ -40,10 +40,10 @@ define <2 x double> @test_blendpd(<2 x d
;
; SKYLAKE-LABEL: test_blendpd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1] sched: [1:0.50]
+; SKYLAKE-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1] sched: [1:0.33]
; SKYLAKE-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],mem[1] sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],mem[1] sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_blendpd:
; SKX: # BB#0:
@@ -100,9 +100,9 @@ define <4 x float> @test_blendps(<4 x fl
;
; SKYLAKE-LABEL: test_blendps:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3] sched: [1:0.50]
-; SKYLAKE-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2,3] sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3] sched: [1:0.33]
+; SKYLAKE-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2,3] sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_blendps:
; SKX: # BB#0:
@@ -161,8 +161,8 @@ define <2 x double> @test_blendvpd(<2 x
; SKYLAKE-LABEL: test_blendvpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vblendvpd %xmm2, %xmm1, %xmm0, %xmm0 # sched: [2:0.67]
-; SKYLAKE-NEXT: vblendvpd %xmm2, (%rdi), %xmm0, %xmm0 # sched: [2:0.67]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vblendvpd %xmm2, (%rdi), %xmm0, %xmm0 # sched: [8:0.67]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_blendvpd:
; SKX: # BB#0:
@@ -222,8 +222,8 @@ define <4 x float> @test_blendvps(<4 x f
; SKYLAKE-LABEL: test_blendvps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0 # sched: [2:0.67]
-; SKYLAKE-NEXT: vblendvps %xmm2, (%rdi), %xmm0, %xmm0 # sched: [2:0.67]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vblendvps %xmm2, (%rdi), %xmm0, %xmm0 # sched: [8:0.67]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_blendvps:
; SKX: # BB#0:
@@ -277,8 +277,8 @@ define <2 x double> @test_dppd(<2 x doub
; SKYLAKE-LABEL: test_dppd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vdppd $7, %xmm1, %xmm0, %xmm0 # sched: [9:1.00]
-; SKYLAKE-NEXT: vdppd $7, (%rdi), %xmm0, %xmm0 # sched: [9:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vdppd $7, (%rdi), %xmm0, %xmm0 # sched: [15:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_dppd:
; SKX: # BB#0:
@@ -332,8 +332,8 @@ define <4 x float> @test_dpps(<4 x float
; SKYLAKE-LABEL: test_dpps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vdpps $7, %xmm1, %xmm0, %xmm0 # sched: [13:1.33]
-; SKYLAKE-NEXT: vdpps $7, (%rdi), %xmm0, %xmm0 # sched: [13:1.33]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vdpps $7, (%rdi), %xmm0, %xmm0 # sched: [19:1.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_dpps:
; SKX: # BB#0:
@@ -387,8 +387,8 @@ define <4 x float> @test_insertps(<4 x f
; SKYLAKE-LABEL: test_insertps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm1[0],xmm0[2,3] sched: [1:1.00]
-; SKYLAKE-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] sched: [7:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_insertps:
; SKX: # BB#0:
@@ -437,8 +437,8 @@ define <2 x i64> @test_movntdqa(i8* %a0)
;
; SKYLAKE-LABEL: test_movntdqa:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vmovntdqa (%rdi), %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vmovntdqa (%rdi), %xmm0 # sched: [6:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_movntdqa:
; SKX: # BB#0:
@@ -487,8 +487,8 @@ define <8 x i16> @test_mpsadbw(<16 x i8>
; SKYLAKE-LABEL: test_mpsadbw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vmpsadbw $7, %xmm1, %xmm0, %xmm0 # sched: [4:2.00]
-; SKYLAKE-NEXT: vmpsadbw $7, (%rdi), %xmm0, %xmm0 # sched: [4:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vmpsadbw $7, (%rdi), %xmm0, %xmm0 # sched: [10:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_mpsadbw:
; SKX: # BB#0:
@@ -543,8 +543,8 @@ define <8 x i16> @test_packusdw(<4 x i32
; SKYLAKE-LABEL: test_packusdw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpackusdw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpackusdw (%rdi), %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpackusdw (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_packusdw:
; SKX: # BB#0:
@@ -605,8 +605,8 @@ define <16 x i8> @test_pblendvb(<16 x i8
; SKYLAKE-LABEL: test_pblendvb:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 # sched: [2:0.67]
-; SKYLAKE-NEXT: vpblendvb %xmm2, (%rdi), %xmm0, %xmm0 # sched: [2:0.67]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpblendvb %xmm2, (%rdi), %xmm0, %xmm0 # sched: [8:0.67]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pblendvb:
; SKX: # BB#0:
@@ -660,8 +660,8 @@ define <8 x i16> @test_pblendw(<8 x i16>
; SKYLAKE-LABEL: test_pblendw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] sched: [1:1.00]
-; SKYLAKE-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],mem[2,3],xmm0[4,5,6],mem[7] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],mem[2,3],xmm0[4,5,6],mem[7] sched: [7:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pblendw:
; SKX: # BB#0:
@@ -713,9 +713,9 @@ define <2 x i64> @test_pcmpeqq(<2 x i64>
;
; SKYLAKE-LABEL: test_pcmpeqq:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpcmpeqq (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpcmpeqq (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pcmpeqq:
; SKX: # BB#0:
@@ -772,8 +772,8 @@ define i32 @test_pextrb(<16 x i8> %a0, i
; SKYLAKE-LABEL: test_pextrb:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpextrb $3, %xmm0, %eax # sched: [3:1.00]
-; SKYLAKE-NEXT: vpextrb $1, %xmm0, (%rdi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpextrb $1, %xmm0, (%rdi) # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pextrb:
; SKX: # BB#0:
@@ -827,8 +827,8 @@ define i32 @test_pextrd(<4 x i32> %a0, i
; SKYLAKE-LABEL: test_pextrd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpextrd $3, %xmm0, %eax # sched: [3:1.00]
-; SKYLAKE-NEXT: vpextrd $1, %xmm0, (%rdi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpextrd $1, %xmm0, (%rdi) # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pextrd:
; SKX: # BB#0:
@@ -881,8 +881,8 @@ define i64 @test_pextrq(<2 x i64> %a0, <
; SKYLAKE-LABEL: test_pextrq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpextrq $1, %xmm0, %rax # sched: [3:1.00]
-; SKYLAKE-NEXT: vpextrq $1, %xmm0, (%rdi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpextrq $1, %xmm0, (%rdi) # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pextrq:
; SKX: # BB#0:
@@ -935,8 +935,8 @@ define i32 @test_pextrw(<8 x i16> %a0, i
; SKYLAKE-LABEL: test_pextrw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpextrw $3, %xmm0, %eax # sched: [3:1.00]
-; SKYLAKE-NEXT: vpextrw $1, %xmm0, (%rdi) # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpextrw $1, %xmm0, (%rdi) # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pextrw:
; SKX: # BB#0:
@@ -989,9 +989,9 @@ define <8 x i16> @test_phminposuw(<8 x i
;
; SKYLAKE-LABEL: test_phminposuw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vphminposuw (%rdi), %xmm0 # sched: [4:0.50]
+; SKYLAKE-NEXT: vphminposuw (%rdi), %xmm0 # sched: [10:0.50]
; SKYLAKE-NEXT: vphminposuw %xmm0, %xmm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_phminposuw:
; SKX: # BB#0:
@@ -1045,8 +1045,8 @@ define <16 x i8> @test_pinsrb(<16 x i8>
; SKYLAKE-LABEL: test_pinsrb:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpinsrb $1, %edi, %xmm0, %xmm0 # sched: [2:2.00]
-; SKYLAKE-NEXT: vpinsrb $3, (%rsi), %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpinsrb $3, (%rsi), %xmm0, %xmm0 # sched: [6:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pinsrb:
; SKX: # BB#0:
@@ -1099,8 +1099,8 @@ define <4 x i32> @test_pinsrd(<4 x i32>
; SKYLAKE-LABEL: test_pinsrd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpinsrd $1, %edi, %xmm0, %xmm0 # sched: [2:2.00]
-; SKYLAKE-NEXT: vpinsrd $3, (%rsi), %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpinsrd $3, (%rsi), %xmm0, %xmm0 # sched: [6:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pinsrd:
; SKX: # BB#0:
@@ -1157,9 +1157,9 @@ define <2 x i64> @test_pinsrq(<2 x i64>
; SKYLAKE-LABEL: test_pinsrq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpinsrq $1, %rdi, %xmm0, %xmm0 # sched: [2:2.00]
-; SKYLAKE-NEXT: vpinsrq $1, (%rsi), %xmm1, %xmm1 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpinsrq $1, (%rsi), %xmm1, %xmm1 # sched: [6:1.00]
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pinsrq:
; SKX: # BB#0:
@@ -1215,9 +1215,9 @@ define <16 x i8> @test_pmaxsb(<16 x i8>
;
; SKYLAKE-LABEL: test_pmaxsb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpmaxsb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpmaxsb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaxsb:
; SKX: # BB#0:
@@ -1270,9 +1270,9 @@ define <4 x i32> @test_pmaxsd(<4 x i32>
;
; SKYLAKE-LABEL: test_pmaxsd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpmaxsd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpmaxsd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaxsd:
; SKX: # BB#0:
@@ -1325,9 +1325,9 @@ define <4 x i32> @test_pmaxud(<4 x i32>
;
; SKYLAKE-LABEL: test_pmaxud:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpmaxud (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpmaxud (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaxud:
; SKX: # BB#0:
@@ -1380,9 +1380,9 @@ define <8 x i16> @test_pmaxuw(<8 x i16>
;
; SKYLAKE-LABEL: test_pmaxuw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpmaxuw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpmaxuw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaxuw:
; SKX: # BB#0:
@@ -1435,9 +1435,9 @@ define <16 x i8> @test_pminsb(<16 x i8>
;
; SKYLAKE-LABEL: test_pminsb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpminsb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpminsb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpminsb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpminsb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pminsb:
; SKX: # BB#0:
@@ -1490,9 +1490,9 @@ define <4 x i32> @test_pminsd(<4 x i32>
;
; SKYLAKE-LABEL: test_pminsd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpminsd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpminsd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpminsd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpminsd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pminsd:
; SKX: # BB#0:
@@ -1545,9 +1545,9 @@ define <4 x i32> @test_pminud(<4 x i32>
;
; SKYLAKE-LABEL: test_pminud:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpminud %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpminud (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpminud %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpminud (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pminud:
; SKX: # BB#0:
@@ -1600,9 +1600,9 @@ define <8 x i16> @test_pminuw(<8 x i16>
;
; SKYLAKE-LABEL: test_pminuw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpminuw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpminuw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpminuw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpminuw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pminuw:
; SKX: # BB#0:
@@ -1661,9 +1661,9 @@ define <8 x i16> @test_pmovsxbw(<16 x i8
; SKYLAKE-LABEL: test_pmovsxbw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovsxbw %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpmovsxbw (%rdi), %xmm1 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovsxbw (%rdi), %xmm1 # sched: [6:1.00]
+; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovsxbw:
; SKX: # BB#0:
@@ -1726,9 +1726,9 @@ define <4 x i32> @test_pmovsxbd(<16 x i8
; SKYLAKE-LABEL: test_pmovsxbd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovsxbd %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpmovsxbd (%rdi), %xmm1 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovsxbd (%rdi), %xmm1 # sched: [6:1.00]
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovsxbd:
; SKX: # BB#0:
@@ -1791,9 +1791,9 @@ define <2 x i64> @test_pmovsxbq(<16 x i8
; SKYLAKE-LABEL: test_pmovsxbq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovsxbq %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpmovsxbq (%rdi), %xmm1 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovsxbq (%rdi), %xmm1 # sched: [6:1.00]
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovsxbq:
; SKX: # BB#0:
@@ -1856,9 +1856,9 @@ define <2 x i64> @test_pmovsxdq(<4 x i32
; SKYLAKE-LABEL: test_pmovsxdq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovsxdq %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpmovsxdq (%rdi), %xmm1 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovsxdq (%rdi), %xmm1 # sched: [6:1.00]
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovsxdq:
; SKX: # BB#0:
@@ -1921,9 +1921,9 @@ define <4 x i32> @test_pmovsxwd(<8 x i16
; SKYLAKE-LABEL: test_pmovsxwd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovsxwd %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpmovsxwd (%rdi), %xmm1 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovsxwd (%rdi), %xmm1 # sched: [6:1.00]
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovsxwd:
; SKX: # BB#0:
@@ -1986,9 +1986,9 @@ define <2 x i64> @test_pmovsxwq(<8 x i16
; SKYLAKE-LABEL: test_pmovsxwq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovsxwq %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpmovsxwq (%rdi), %xmm1 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovsxwq (%rdi), %xmm1 # sched: [6:1.00]
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovsxwq:
; SKX: # BB#0:
@@ -2051,9 +2051,9 @@ define <8 x i16> @test_pmovzxbw(<16 x i8
; SKYLAKE-LABEL: test_pmovzxbw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero sched: [1:1.00]
-; SKYLAKE-NEXT: vpmovzxbw {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovzxbw {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero sched: [6:1.00]
+; SKYLAKE-NEXT: vpaddw %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovzxbw:
; SKX: # BB#0:
@@ -2116,9 +2116,9 @@ define <4 x i32> @test_pmovzxbd(<16 x i8
; SKYLAKE-LABEL: test_pmovzxbd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero sched: [1:1.00]
-; SKYLAKE-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero sched: [6:1.00]
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovzxbd:
; SKX: # BB#0:
@@ -2181,9 +2181,9 @@ define <2 x i64> @test_pmovzxbq(<16 x i8
; SKYLAKE-LABEL: test_pmovzxbq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero sched: [1:1.00]
-; SKYLAKE-NEXT: vpmovzxbq {{.*#+}} xmm1 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovzxbq {{.*#+}} xmm1 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero sched: [6:1.00]
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovzxbq:
; SKX: # BB#0:
@@ -2246,9 +2246,9 @@ define <2 x i64> @test_pmovzxdq(<4 x i32
; SKYLAKE-LABEL: test_pmovzxdq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero sched: [1:1.00]
-; SKYLAKE-NEXT: vpmovzxdq {{.*#+}} xmm1 = mem[0],zero,mem[1],zero sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovzxdq {{.*#+}} xmm1 = mem[0],zero,mem[1],zero sched: [6:1.00]
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovzxdq:
; SKX: # BB#0:
@@ -2311,9 +2311,9 @@ define <4 x i32> @test_pmovzxwd(<8 x i16
; SKYLAKE-LABEL: test_pmovzxwd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero sched: [1:1.00]
-; SKYLAKE-NEXT: vpmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero sched: [6:1.00]
+; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovzxwd:
; SKX: # BB#0:
@@ -2376,9 +2376,9 @@ define <2 x i64> @test_pmovzxwq(<8 x i16
; SKYLAKE-LABEL: test_pmovzxwq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero sched: [1:1.00]
-; SKYLAKE-NEXT: vpmovzxwq {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero sched: [1:1.00]
-; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmovzxwq {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero sched: [6:1.00]
+; SKYLAKE-NEXT: vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmovzxwq:
; SKX: # BB#0:
@@ -2436,8 +2436,8 @@ define <2 x i64> @test_pmuldq(<4 x i32>
; SKYLAKE-LABEL: test_pmuldq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmuldq %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vpmuldq (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmuldq (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmuldq:
; SKX: # BB#0:
@@ -2492,8 +2492,8 @@ define <4 x i32> @test_pmulld(<4 x i32>
; SKYLAKE-LABEL: test_pmulld:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmulld %xmm1, %xmm0, %xmm0 # sched: [8:0.67]
-; SKYLAKE-NEXT: vpmulld (%rdi), %xmm0, %xmm0 # sched: [8:0.67]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmulld (%rdi), %xmm0, %xmm0 # sched: [14:0.67]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmulld:
; SKX: # BB#0:
@@ -2562,12 +2562,12 @@ define i32 @test_ptest(<2 x i64> %a0, <2
; SKYLAKE-LABEL: test_ptest:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vptest %xmm1, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: setb %al # sched: [1:1.00]
-; SKYLAKE-NEXT: vptest (%rdi), %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: setb %cl # sched: [1:1.00]
+; SKYLAKE-NEXT: setb %al # sched: [1:0.50]
+; SKYLAKE-NEXT: vptest (%rdi), %xmm0 # sched: [9:1.00]
+; SKYLAKE-NEXT: setb %cl # sched: [1:0.50]
; SKYLAKE-NEXT: andb %al, %cl # sched: [1:0.25]
; SKYLAKE-NEXT: movzbl %cl, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_ptest:
; SKX: # BB#0:
@@ -2639,9 +2639,9 @@ define <2 x double> @test_roundpd(<2 x d
; SKYLAKE-LABEL: test_roundpd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vroundpd $7, %xmm0, %xmm0 # sched: [8:0.67]
-; SKYLAKE-NEXT: vroundpd $7, (%rdi), %xmm1 # sched: [8:0.67]
+; SKYLAKE-NEXT: vroundpd $7, (%rdi), %xmm1 # sched: [14:0.67]
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_roundpd:
; SKX: # BB#0:
@@ -2704,9 +2704,9 @@ define <4 x float> @test_roundps(<4 x fl
; SKYLAKE-LABEL: test_roundps:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vroundps $7, %xmm0, %xmm0 # sched: [8:0.67]
-; SKYLAKE-NEXT: vroundps $7, (%rdi), %xmm1 # sched: [8:0.67]
+; SKYLAKE-NEXT: vroundps $7, (%rdi), %xmm1 # sched: [14:0.67]
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_roundps:
; SKX: # BB#0:
@@ -2770,9 +2770,9 @@ define <2 x double> @test_roundsd(<2 x d
; SKYLAKE-LABEL: test_roundsd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vroundsd $7, %xmm1, %xmm0, %xmm1 # sched: [8:0.67]
-; SKYLAKE-NEXT: vroundsd $7, (%rdi), %xmm0, %xmm0 # sched: [8:0.67]
+; SKYLAKE-NEXT: vroundsd $7, (%rdi), %xmm0, %xmm0 # sched: [14:0.67]
; SKYLAKE-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_roundsd:
; SKX: # BB#0:
@@ -2836,9 +2836,9 @@ define <4 x float> @test_roundss(<4 x fl
; SKYLAKE-LABEL: test_roundss:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vroundss $7, %xmm1, %xmm0, %xmm1 # sched: [8:0.67]
-; SKYLAKE-NEXT: vroundss $7, (%rdi), %xmm0, %xmm0 # sched: [8:0.67]
+; SKYLAKE-NEXT: vroundss $7, (%rdi), %xmm0, %xmm0 # sched: [14:0.67]
; SKYLAKE-NEXT: vaddps %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_roundss:
; SKX: # BB#0:
Modified: llvm/trunk/test/CodeGen/X86/sse42-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse42-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse42-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse42-schedule.ll Mon Oct 16 23:47:04 2017
@@ -43,7 +43,7 @@ define i32 @crc32_32_8(i32 %a0, i8 %a1,
; SKYLAKE-NEXT: crc32b %sil, %edi # sched: [3:1.00]
; SKYLAKE-NEXT: crc32b (%rdx), %edi # sched: [8:1.00]
; SKYLAKE-NEXT: movl %edi, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: crc32_32_8:
; SKX: # BB#0:
@@ -106,7 +106,7 @@ define i32 @crc32_32_16(i32 %a0, i16 %a1
; SKYLAKE-NEXT: crc32w %si, %edi # sched: [3:1.00]
; SKYLAKE-NEXT: crc32w (%rdx), %edi # sched: [8:1.00]
; SKYLAKE-NEXT: movl %edi, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: crc32_32_16:
; SKX: # BB#0:
@@ -169,7 +169,7 @@ define i32 @crc32_32_32(i32 %a0, i32 %a1
; SKYLAKE-NEXT: crc32l %esi, %edi # sched: [3:1.00]
; SKYLAKE-NEXT: crc32l (%rdx), %edi # sched: [8:1.00]
; SKYLAKE-NEXT: movl %edi, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: crc32_32_32:
; SKX: # BB#0:
@@ -232,7 +232,7 @@ define i64 @crc32_64_8(i64 %a0, i8 %a1,
; SKYLAKE-NEXT: crc32b %sil, %edi # sched: [3:1.00]
; SKYLAKE-NEXT: crc32b (%rdx), %edi # sched: [8:1.00]
; SKYLAKE-NEXT: movq %rdi, %rax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: crc32_64_8:
; SKX: # BB#0:
@@ -295,7 +295,7 @@ define i64 @crc32_64_64(i64 %a0, i64 %a1
; SKYLAKE-NEXT: crc32q %rsi, %rdi # sched: [3:1.00]
; SKYLAKE-NEXT: crc32q (%rdx), %rdi # sched: [8:1.00]
; SKYLAKE-NEXT: movq %rdi, %rax # sched: [1:0.25]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: crc32_64_64:
; SKX: # BB#0:
@@ -385,10 +385,10 @@ define i32 @test_pcmpestri(<16 x i8> %a0
; SKYLAKE-NEXT: movl %ecx, %esi # sched: [1:0.25]
; SKYLAKE-NEXT: movl $7, %eax # sched: [1:0.25]
; SKYLAKE-NEXT: movl $7, %edx # sched: [1:0.25]
-; SKYLAKE-NEXT: vpcmpestri $7, (%rdi), %xmm0 # sched: [18:4.00]
+; SKYLAKE-NEXT: vpcmpestri $7, (%rdi), %xmm0 # sched: [24:4.00]
; SKYLAKE-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def>
; SKYLAKE-NEXT: leal (%rcx,%rsi), %eax # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pcmpestri:
; SKX: # BB#0:
@@ -484,8 +484,8 @@ define <16 x i8> @test_pcmpestrm(<16 x i
; SKYLAKE-NEXT: vpcmpestrm $7, %xmm1, %xmm0 # sched: [19:4.00]
; SKYLAKE-NEXT: movl $7, %eax # sched: [1:0.25]
; SKYLAKE-NEXT: movl $7, %edx # sched: [1:0.25]
-; SKYLAKE-NEXT: vpcmpestrm $7, (%rdi), %xmm0 # sched: [19:4.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpcmpestrm $7, (%rdi), %xmm0 # sched: [25:4.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pcmpestrm:
; SKX: # BB#0:
@@ -564,10 +564,10 @@ define i32 @test_pcmpistri(<16 x i8> %a0
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpcmpistri $7, %xmm1, %xmm0 # sched: [10:3.00]
; SKYLAKE-NEXT: movl %ecx, %eax # sched: [1:0.25]
-; SKYLAKE-NEXT: vpcmpistri $7, (%rdi), %xmm0 # sched: [10:3.00]
+; SKYLAKE-NEXT: vpcmpistri $7, (%rdi), %xmm0 # sched: [16:3.00]
; SKYLAKE-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def>
; SKYLAKE-NEXT: leal (%rcx,%rax), %eax # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pcmpistri:
; SKX: # BB#0:
@@ -631,8 +631,8 @@ define <16 x i8> @test_pcmpistrm(<16 x i
; SKYLAKE-LABEL: test_pcmpistrm:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpcmpistrm $7, %xmm1, %xmm0 # sched: [10:3.00]
-; SKYLAKE-NEXT: vpcmpistrm $7, (%rdi), %xmm0 # sched: [10:3.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpcmpistrm $7, (%rdi), %xmm0 # sched: [16:3.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pcmpistrm:
; SKX: # BB#0:
@@ -686,8 +686,8 @@ define <2 x i64> @test_pcmpgtq(<2 x i64>
; SKYLAKE-LABEL: test_pcmpgtq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: vpcmpgtq (%rdi), %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpcmpgtq (%rdi), %xmm0, %xmm0 # sched: [9:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pcmpgtq:
; SKX: # BB#0:
@@ -744,8 +744,8 @@ define <2 x i64> @test_pclmulqdq(<2 x i6
; SKYLAKE-LABEL: test_pclmulqdq:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpclmulqdq $0, %xmm1, %xmm0, %xmm0 # sched: [6:1.00]
-; SKYLAKE-NEXT: vpclmulqdq $0, (%rdi), %xmm0, %xmm0 # sched: [6:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpclmulqdq $0, (%rdi), %xmm0, %xmm0 # sched: [12:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pclmulqdq:
; SKX: # BB#0:
Modified: llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll?rev=315978&r1=315977&r2=315978&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/ssse3-schedule.ll Mon Oct 16 23:47:04 2017
@@ -49,10 +49,10 @@ define <16 x i8> @test_pabsb(<16 x i8> %
;
; SKYLAKE-LABEL: test_pabsb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpabsb %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpabsb (%rdi), %xmm1 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpabsb %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpabsb (%rdi), %xmm1 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pabsb:
; SKX: # BB#0:
@@ -121,10 +121,10 @@ define <4 x i32> @test_pabsd(<4 x i32> %
;
; SKYLAKE-LABEL: test_pabsd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpabsd %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpabsd (%rdi), %xmm1 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpabsd %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpabsd (%rdi), %xmm1 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pabsd:
; SKX: # BB#0:
@@ -193,10 +193,10 @@ define <8 x i16> @test_pabsw(<8 x i16> %
;
; SKYLAKE-LABEL: test_pabsw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpabsw %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpabsw (%rdi), %xmm1 # sched: [1:0.50]
-; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpabsw %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpabsw (%rdi), %xmm1 # sched: [7:0.50]
+; SKYLAKE-NEXT: vpor %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pabsw:
; SKX: # BB#0:
@@ -265,8 +265,8 @@ define <8 x i16> @test_palignr(<8 x i16>
; SKYLAKE-LABEL: test_palignr:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4,5] sched: [1:1.00]
-; SKYLAKE-NEXT: vpalignr {{.*#+}} xmm0 = mem[14,15],xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13] sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpalignr {{.*#+}} xmm0 = mem[14,15],xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13] sched: [7:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_palignr:
; SKX: # BB#0:
@@ -325,8 +325,8 @@ define <4 x i32> @test_phaddd(<4 x i32>
; SKYLAKE-LABEL: test_phaddd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vphaddd %xmm1, %xmm0, %xmm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: vphaddd (%rdi), %xmm0, %xmm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vphaddd (%rdi), %xmm0, %xmm0 # sched: [9:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_phaddd:
; SKX: # BB#0:
@@ -386,8 +386,8 @@ define <8 x i16> @test_phaddsw(<8 x i16>
; SKYLAKE-LABEL: test_phaddsw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vphaddsw %xmm1, %xmm0, %xmm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: vphaddsw (%rdi), %xmm0, %xmm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vphaddsw (%rdi), %xmm0, %xmm0 # sched: [9:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_phaddsw:
; SKX: # BB#0:
@@ -447,8 +447,8 @@ define <8 x i16> @test_phaddw(<8 x i16>
; SKYLAKE-LABEL: test_phaddw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vphaddw %xmm1, %xmm0, %xmm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: vphaddw (%rdi), %xmm0, %xmm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vphaddw (%rdi), %xmm0, %xmm0 # sched: [9:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_phaddw:
; SKX: # BB#0:
@@ -508,8 +508,8 @@ define <4 x i32> @test_phsubd(<4 x i32>
; SKYLAKE-LABEL: test_phsubd:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vphsubd %xmm1, %xmm0, %xmm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: vphsubd (%rdi), %xmm0, %xmm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vphsubd (%rdi), %xmm0, %xmm0 # sched: [9:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_phsubd:
; SKX: # BB#0:
@@ -569,8 +569,8 @@ define <8 x i16> @test_phsubsw(<8 x i16>
; SKYLAKE-LABEL: test_phsubsw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vphsubsw %xmm1, %xmm0, %xmm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: vphsubsw (%rdi), %xmm0, %xmm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vphsubsw (%rdi), %xmm0, %xmm0 # sched: [9:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_phsubsw:
; SKX: # BB#0:
@@ -630,8 +630,8 @@ define <8 x i16> @test_phsubw(<8 x i16>
; SKYLAKE-LABEL: test_phsubw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vphsubw %xmm1, %xmm0, %xmm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: vphsubw (%rdi), %xmm0, %xmm0 # sched: [3:2.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vphsubw (%rdi), %xmm0, %xmm0 # sched: [9:2.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_phsubw:
; SKX: # BB#0:
@@ -691,8 +691,8 @@ define <8 x i16> @test_pmaddubsw(<16 x i
; SKYLAKE-LABEL: test_pmaddubsw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmaddubsw %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vpmaddubsw (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmaddubsw (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmaddubsw:
; SKX: # BB#0:
@@ -753,8 +753,8 @@ define <8 x i16> @test_pmulhrsw(<8 x i16
; SKYLAKE-LABEL: test_pmulhrsw:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpmulhrsw %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
-; SKYLAKE-NEXT: vpmulhrsw (%rdi), %xmm0, %xmm0 # sched: [4:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpmulhrsw (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pmulhrsw:
; SKX: # BB#0:
@@ -814,8 +814,8 @@ define <16 x i8> @test_pshufb(<16 x i8>
; SKYLAKE-LABEL: test_pshufb:
; SKYLAKE: # BB#0:
; SKYLAKE-NEXT: vpshufb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpshufb (%rdi), %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpshufb (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_pshufb:
; SKX: # BB#0:
@@ -878,9 +878,9 @@ define <16 x i8> @test_psignb(<16 x i8>
;
; SKYLAKE-LABEL: test_psignb:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsignb %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsignb (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsignb %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsignb (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psignb:
; SKX: # BB#0:
@@ -943,9 +943,9 @@ define <4 x i32> @test_psignd(<4 x i32>
;
; SKYLAKE-LABEL: test_psignd:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsignd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsignd (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsignd %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsignd (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psignd:
; SKX: # BB#0:
@@ -1008,9 +1008,9 @@ define <8 x i16> @test_psignw(<8 x i16>
;
; SKYLAKE-LABEL: test_psignw:
; SKYLAKE: # BB#0:
-; SKYLAKE-NEXT: vpsignw %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
-; SKYLAKE-NEXT: vpsignw (%rdi), %xmm0, %xmm0 # sched: [1:0.50]
-; SKYLAKE-NEXT: retq # sched: [2:1.00]
+; SKYLAKE-NEXT: vpsignw %xmm1, %xmm0, %xmm0 # sched: [1:0.50]
+; SKYLAKE-NEXT: vpsignw (%rdi), %xmm0, %xmm0 # sched: [7:0.50]
+; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_psignw:
; SKX: # BB#0:
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