[llvm] r315972 - [globalisel][tablegen] Add a GIM_CheckIsSameOperand test where OtherInsnID and OtherOpIdx differ

[Daniel Sanders via llvm-commits]

Author: dsanders
Date: Mon Oct 16 22:24:44 2017
New Revision: 315972

URL: http://llvm.org/viewvc/llvm-project?rev=315972&view=rev
Log:
[globalisel][tablegen] Add a GIM_CheckIsSameOperand test where OtherInsnID and OtherOpIdx differ

Added:
    llvm/trunk/test/CodeGen/X86/GlobalISel/select-blsi.mir

Added: llvm/trunk/test/CodeGen/X86/GlobalISel/select-blsi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-blsi.mir?rev=315972&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-blsi.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-blsi.mir Mon Oct 16 22:24:44 2017
@@ -0,0 +1,61 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+bmi -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+#
+# Test that rules where multiple operands must be the same operand successfully
+# match. Also test that the rules do not match when they're not the same
+# operand.
+#
+# This test covers the case when OtherInsnID and OtherOpIdx are different in a
+# GIM_CheckIsSameOperand.
+
+---
+name:            test_blsi32rr
+# CHECK-LABEL: name:  test_blsi32rr
+alignment:       4
+legalized:       true
+regBankSelected: true
+# CHECK:       registers:
+# CHECK-NEXT:     - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT:     - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:     - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:     - { id: 3, class: gr32, preferred-register: '' }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+# G_SUB and G_AND both use %0 so we should match this.
+# CHECK: %3 = BLSI32rr %0
+body:             |
+  bb.1:
+    liveins: %edi
+
+    %0(s32) = COPY %edi
+    %1(s32) = G_CONSTANT i32 0
+    %2(s32) = G_SUB %1, %0
+    %3(s32) = G_AND %2, %0
+    %edi = COPY %3
+
+...
+---
+name:            test_blsi32rr_nomatch
+# CHECK-LABEL: name:  test_blsi32rr_nomatch
+alignment:       4
+legalized:       true
+regBankSelected: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+# G_SUB and G_AND use different operands so we shouldn't match this.
+# CHECK-NOT: BLSI32rr
+body:             |
+  bb.1:
+    liveins: %edi
+
+    %0(s32) = COPY %edi
+    %1(s32) = G_CONSTANT i32 0
+    %2(s32) = G_SUB %1, %1
+    %3(s32) = G_AND %2, %0
+    %edi = COPY %3
+...