[PATCH] D38736: [X86] test/testn intrinsics lowering to IR. llvm part.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 16 16:27:18 PDT 2017
craig.topper added inline comments.
================
Comment at: lib/IR/AutoUpgrade.cpp:828
+// Applying mask on vector of i1's and make sure result is atleast 8 bits wide.
+static Value *ApplyX86MaskOn1BitsVec(IRBuilder<> &Builder,Value *Vec, Value *Mask,
----------------
'atleast' should be two words
================
Comment at: lib/IR/AutoUpgrade.cpp:830
+static Value *ApplyX86MaskOn1BitsVec(IRBuilder<> &Builder,Value *Vec, Value *Mask,
+ unsigned NumElts) {
+ const auto *C = dyn_cast<Constant>(Mask);
----------------
Line up the last argument with the end of the opening parenthese above
================
Comment at: lib/IR/AutoUpgrade.cpp:842
+ Vec = Builder.CreateShuffleVector(Vec,
+ Constant::getNullValue(Vec->getType()),
+ Indices);
----------------
These two lines are indented one space too far.
================
Comment at: lib/IR/AutoUpgrade.cpp:875
- if (NumElts < 8) {
- uint32_t Indices[8];
- for (unsigned i = 0; i != NumElts; ++i)
- Indices[i] = i;
- for (unsigned i = NumElts; i != 8; ++i)
- Indices[i] = NumElts + i % NumElts;
- Cmp = Builder.CreateShuffleVector(Cmp,
- Constant::getNullValue(Cmp->getType()),
- Indices);
- }
return Builder.CreateBitCast(Cmp, IntegerType::get(CI.getContext(),
std::max(NumElts, 8U)));
----------------
Move this bitcast into the ApplyX86MaskOn1BitsVec. The same one appears at the second call site.
================
Comment at: lib/IR/AutoUpgrade.cpp:1050
+ Name.startswith("avx512.ptestm") ? ICmpInst::ICMP_NE : ICmpInst::ICMP_EQ;
+ Rep = Builder.CreateICmp(Pred , Rep, Zero);
+ unsigned NumElts = Op0->getType()->getVectorNumElements();
----------------
Extract space between Pred and comma
https://reviews.llvm.org/D38736
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