[PATCH] D38942: [DAG] Promote ADDCARRY / SUBCARRY

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 created this revision.
Herald added a subscriber: javed.absar.

Add missing case that was not implemented yet.


https://reviews.llvm.org/D38942

Files:
  lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  test/CodeGen/ARM/addsubcarry-promotion.ll


Index: test/CodeGen/ARM/addsubcarry-promotion.ll
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/addsubcarry-promotion.ll
@@ -0,0 +1,57 @@
+; RUN: llc -O2 -mtriple armv7a < %s | FileCheck --check-prefix=ARM %s
+
+; RUN: llc -O2 -mtriple thumbv6m < %s | FileCheck --check-prefix=THUMB1 %s
+; RUN: llc -O2 -mtriple thumbv8m.base < %s | FileCheck --check-prefix=THUMB1 %s
+
+; RUN: llc -O2 -mtriple thumbv7a < %s | FileCheck --check-prefix=THUMB %s
+; RUN: llc -O2 -mtriple thumbv8m.main < %s | FileCheck --check-prefix=THUMB %s
+
+define void @fn1(i32 %a, i32 %b, i32 %c) local_unnamed_addr #0 {
+entry:
+
+; ARM: adds	r0, r1, r0
+; ARM: rsb	r2, r2, #1
+; ARM: adc	r0, r2, #0
+; ARM: movw	r1, #65535
+; ARM: tst	r0, r1
+; ARM: bxeq	lr
+; ARM: .LBB0_1:
+; ARM: b	.LBB0_1
+
+; THUMB1: movs	r3, #1
+; THUMB1: subs	r2, r3, r2
+; THUMB1: movs	r3, #0
+; THUMB1: adds	r0, r1, r0
+; THUMB1: adcs	r3, r2
+; THUMB1: lsls	r0, r3, #16
+; THUMB1: beq	.LBB0_2
+; THUMB1: .LBB0_1:
+; THUMB1: b	.LBB0_1
+
+; THUMB: rsb.w	r2, r2, #1
+; THUMB: adds	r0, r0, r1
+; THUMB: adc	r0, r2, #0
+; THUMB: lsls	r0, r0, #16
+; THUMB: it	eq
+; THUMB: bxeq	lr
+; THUMB: .LBB0_1:
+; THUMB: b	.LBB0_1
+
+  %add = add i32 %b, %a
+  %cmp = icmp ult i32 %add, %b
+  %conv = zext i1 %cmp to i32
+  %sub = sub i32 1, %c
+  %add1 = add i32 %sub, %conv
+  %conv2 = trunc i32 %add1 to i16
+  %tobool = icmp eq i16 %conv2, 0
+  br i1 %tobool, label %if.end, label %for.cond.preheader
+
+for.cond.preheader:                               ; preds = %entry
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.cond.preheader, %for.cond
+  br label %for.cond
+
+if.end:                                           ; preds = %entry
+  ret void
+}
Index: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -773,7 +773,18 @@
 SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBCARRY(SDNode *N, unsigned ResNo) {
   if (ResNo == 1)
     return PromoteIntRes_Overflow(N);
-  llvm_unreachable("Not implemented");
+
+  SDValue LHS = GetPromotedInteger(N->getOperand(0));
+  SDValue RHS = GetPromotedInteger(N->getOperand(1));
+
+  EVT ValueVTs[] = { LHS.getValueType(), N->getValueType(1) };
+
+  SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
+                     DAG.getVTList(ValueVTs), LHS, RHS, N->getOperand(2));
+
+  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
+
+  return SDValue(Res.getNode(), 0);
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {


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