[llvm] r315686 - [X86] Stop creating CMOV nodes with a second MVT::Glue result
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 13 08:28:35 PDT 2017
Author: ctopper
Date: Fri Oct 13 08:28:35 2017
New Revision: 315686
URL: http://llvm.org/viewvc/llvm-project?rev=315686&view=rev
Log:
[X86] Stop creating CMOV nodes with a second MVT::Glue result
Summary: We seem to inconsistently create CMOV nodes some with a Glue result and some without. But I can't find any cases that use the Glue result. So I've tried to remove all the place that did this.
Reviewers: RKSimon, spatel, zvi
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38664
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=315686&r1=315685&r2=315686&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Oct 13 08:28:35 2017
@@ -17971,17 +17971,16 @@ SDValue X86TargetLowering::LowerSELECT(S
if (T1.getValueType() == T2.getValueType() &&
// Blacklist CopyFromReg to avoid partial register stalls.
T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
- SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
- SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
+ SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, T1.getValueType(), T2, T1,
+ CC, Cond);
return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
}
}
// X86ISD::CMOV means set the result (which is operand 1) to the RHS if
// condition is true.
- SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
SDValue Ops[] = { Op2, Op1, CC, Cond };
- return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
+ return DAG.getNode(X86ISD::CMOV, DL, Op.getValueType(), Ops);
}
static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
@@ -20598,9 +20597,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SD
DAG.getConstant(1, dl, Op->getValueType(1)),
DAG.getConstant(X86::COND_B, dl, MVT::i8),
SDValue(Result.getNode(), 1) };
- SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
- DAG.getVTList(Op->getValueType(1), MVT::Glue),
- Ops);
+ SDValue isValid = DAG.getNode(X86ISD::CMOV, dl, Op->getValueType(1), Ops);
// Return { result, isValid, chain }.
return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
@@ -31166,10 +31163,6 @@ static SDValue combineCMov(SDNode *N, Se
const X86Subtarget &Subtarget) {
SDLoc DL(N);
- // If the flag operand isn't dead, don't touch this CMOV.
- if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
- return SDValue();
-
SDValue FalseOp = N->getOperand(0);
SDValue TrueOp = N->getOperand(1);
X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
@@ -31192,7 +31185,7 @@ static SDValue combineCMov(SDNode *N, Se
if (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC)) {
SDValue Ops[] = {FalseOp, TrueOp, DAG.getConstant(CC, DL, MVT::i8),
Flags};
- return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
+ return DAG.getNode(X86ISD::CMOV, DL, N->getValueType(0), Ops);
}
}
@@ -31221,8 +31214,6 @@ static SDValue combineCMov(SDNode *N, Se
unsigned ShAmt = TrueC->getAPIntValue().logBase2();
Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
DAG.getConstant(ShAmt, DL, MVT::i8));
- if (N->getNumValues() == 2) // Dead flag value?
- return DCI.CombineTo(N, Cond, SDValue());
return Cond;
}
@@ -31236,9 +31227,6 @@ static SDValue combineCMov(SDNode *N, Se
FalseC->getValueType(0), Cond);
Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
SDValue(FalseC, 0));
-
- if (N->getNumValues() == 2) // Dead flag value?
- return DCI.CombineTo(N, Cond, SDValue());
return Cond;
}
@@ -31279,8 +31267,6 @@ static SDValue combineCMov(SDNode *N, Se
if (FalseC->getAPIntValue() != 0)
Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
SDValue(FalseC, 0));
- if (N->getNumValues() == 2) // Dead flag value?
- return DCI.CombineTo(N, Cond, SDValue());
return Cond;
}
}
@@ -31320,7 +31306,7 @@ static SDValue combineCMov(SDNode *N, Se
CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
SDValue Ops[] = { FalseOp, Cond.getOperand(0),
DAG.getConstant(CC, DL, MVT::i8), Cond };
- return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
+ return DAG.getNode(X86ISD::CMOV, DL, N->getValueType(0), Ops);
}
}
}
@@ -31355,10 +31341,9 @@ static SDValue combineCMov(SDNode *N, Se
SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
Flags};
- SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
+ SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getValueType(0), LOps);
SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
- SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
- DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
+ SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getValueType(0), Ops);
return CMOV;
}
}
@@ -32821,7 +32806,7 @@ static SDValue combineIntegerAbs(SDNode
SDValue Ops[] = {N0.getOperand(0), Neg,
DAG.getConstant(X86::COND_GE, DL, MVT::i8),
SDValue(Neg.getNode(), 1)};
- return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
+ return DAG.getNode(X86ISD::CMOV, DL, VT, Ops);
}
}
return SDValue();
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