[PATCH] D35625: Removal of microMIPS64R6

[Simon Dardis via Phabricator via llvm-commits]

sdardis requested changes to this revision.
sdardis added a comment.
This revision now requires changes to proceed.

Probably my last round of comments on this, also can you add a trivial test case showing that microMIPS64R6 is not supported?



================
Comment at: lib/Target/Mips/MicroMipsInstrInfo.td:590-602
+    ARITH_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6;
 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
-    LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6_64R6;
+    LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6;
 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>,
-    ISA_MICROMIPS_NOT_32R6_64R6;
+    ISA_MICROMIPS_NOT_32R6;
 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>,
+    ISA_MICROMIPS_NOT_32R6;
----------------
Align the format class instantiations / ISA predicates under instruction codegen description instantiations.


================
Comment at: lib/Target/Mips/MicroMipsInstrInfo.td:649-651
+    ISA_MICROMIPS_NOT_32R6;
 def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, BRKSDBBP16_FM_MM<0x2C>,
+    ISA_MICROMIPS_NOT_32R6;
----------------
The ISA_MICROMIPS_NOT_32R6 needs to be aligned under the BrkSdbbp16MM.


================
Comment at: lib/Target/Mips/MicroMipsSizeReduction.cpp:498
 
-  // TODO: Add support for other subtargets:
-  // microMIPS32r6 and microMIPS64r6
+  // TODO: Add support for subtarget microMIPS32r6
   if (!Subtarget->inMicroMipsMode() || !Subtarget->hasMips32r2() ||
----------------
for the subtarget microMIPS32R6.


================
Comment at: lib/Target/Mips/MipsTargetMachine.cpp:188-192
+  if (CPU == "mips64r6" && HasMicroMipsAttr) {
+    errs() << "LLVM currently does not support microMIPS for '" << CPU << "'.\n";
+    HasMicroMipsAttr = false;
+    HasNoMicroMipsAttr = true;
+  }
----------------
Take the context from the current Function and use emitError giving the function name + error message.

See include/llvm/IR/LLVMContext.h:300~ for emitError.


================
Comment at: test/CodeGen/Mips/llvm-ir/and.ll:43
 
   ; MM64:         and     $1, $4, $5
 
----------------
Remove this.


================
Comment at: test/CodeGen/Mips/llvm-ir/and.ll:60
 
   ; MM64:         and     $1, $4, $5
 
----------------
Remove this.


================
Comment at: test/CodeGen/Mips/llvm-ir/and.ll:77
 
   ; MM64:         and     $1, $4, $5
 
----------------
Remove this.


================
Comment at: test/CodeGen/Mips/llvm-ir/mul.ll:249-254
   ; MM64R6-DAG:     dmul    $[[T1:[0-9]+]], $5, $6
   ; MM64R6:         dmuhu   $[[T2:[0-9]+]], $5, $7
   ; MM64R6:         daddu   $[[T3:[0-9]+]], $[[T2]], $[[T1]]
   ; MM64R6-DAG:     dmul    $[[T0:[0-9]+]], $4, $7
   ; MM64R6:         daddu   $2, $[[T1]], $[[T0]]
   ; MM64R6-DAG:     dmul    $3, $5, $7
----------------
Remove this.


================
Comment at: test/CodeGen/Mips/llvm-ir/not.ll:132
   ; MM32:         nor     $2, $5, $4
   ; MM64:         or      $1, $5, $4
 
----------------
Remove this.


================
Comment at: test/CodeGen/Mips/llvm-ir/not.ll:146
   ; MM32:         nor     $2, $5, $4
   ; MM64:         or      $1, $5, $4
 
----------------
Remove this.


================
Comment at: test/CodeGen/Mips/llvm-ir/not.ll:160
   ; MM32:         nor     $2, $5, $4
   ; MM64:         or      $1, $5, $4
 
----------------
Remove this.


================
Comment at: test/CodeGen/Mips/llvm-ir/or.ll:32
 
   ; MM64:         or      $1, $4, $5
 
----------------
Remove this.


================
Comment at: test/CodeGen/Mips/llvm-ir/or.ll:47
 
   ; MM64:         or      $1, $4, $5
 
----------------
Remove this.


================
Comment at: test/CodeGen/Mips/llvm-ir/or.ll:64
 
   ; MM64:         or      $1, $4, $5
 
----------------
Remove this.


================
Comment at: test/CodeGen/Mips/llvm-ir/xor.ll:43
 
   ; MM64:         xor     $1, $4, $5
 
----------------
Remove this.


================
Comment at: test/CodeGen/Mips/llvm-ir/xor.ll:58
 
   ; MM64:         xor     $1, $4, $5
 
----------------
Remove this.


================
Comment at: test/CodeGen/Mips/llvm-ir/xor.ll:75
 
   ; MM64:         xor     $1, $4, $5
 
----------------
Remove this.


https://reviews.llvm.org/D35625