[llvm] r315674 - [X86] Remove patterns that select unmasked vbroadcastf2x32/vbroadcasti2x32. Prefer vbroadcastsd/vpbroadcastq instead.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 12 23:07:10 PDT 2017
Author: ctopper
Date: Thu Oct 12 23:07:10 2017
New Revision: 315674
URL: http://llvm.org/viewvc/llvm-project?rev=315674&view=rev
Log:
[X86] Remove patterns that select unmasked vbroadcastf2x32/vbroadcasti2x32. Prefer vbroadcastsd/vpbroadcastq instead.
There's no advantage to using these instructions when they aren't masked. This enables some additional execution domain switching without needing to update the table.
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/test/CodeGen/X86/avx512-shuffles/broadcast-vector-fp.ll
llvm/trunk/test/CodeGen/X86/avx512-shuffles/broadcast-vector-int.ll
llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v8.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=315674&r1=315673&r2=315674&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Thu Oct 12 23:07:10 2017
@@ -1110,19 +1110,31 @@ multiclass avx512_broadcast_scalar<bits<
multiclass avx512_broadcast_rm_split<bits<8> opc, string OpcodeStr,
X86VectorVTInfo MaskInfo,
X86VectorVTInfo DestInfo,
- X86VectorVTInfo SrcInfo> {
- let ExeDomain = DestInfo.ExeDomain in {
- defm r : AVX512_maskable<opc, MRMSrcReg, MaskInfo, (outs MaskInfo.RC:$dst),
+ X86VectorVTInfo SrcInfo,
+ SDPatternOperator UnmaskedOp = X86VBroadcast> {
+ let ExeDomain = DestInfo.ExeDomain, hasSideEffects = 0 in {
+ defm r : AVX512_maskable_split<opc, MRMSrcReg, MaskInfo,
+ (outs MaskInfo.RC:$dst),
(ins SrcInfo.RC:$src), OpcodeStr, "$src", "$src",
(MaskInfo.VT
(bitconvert
(DestInfo.VT
+ (UnmaskedOp (SrcInfo.VT SrcInfo.RC:$src))))),
+ (MaskInfo.VT
+ (bitconvert
+ (DestInfo.VT
(X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src)))))>,
T8PD, EVEX;
- defm m : AVX512_maskable<opc, MRMSrcMem, MaskInfo, (outs MaskInfo.RC:$dst),
+ let mayLoad = 1 in
+ defm m : AVX512_maskable_split<opc, MRMSrcMem, MaskInfo,
+ (outs MaskInfo.RC:$dst),
(ins SrcInfo.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
(MaskInfo.VT
(bitconvert
+ (DestInfo.VT (UnmaskedOp
+ (SrcInfo.ScalarLdFrag addr:$src))))),
+ (MaskInfo.VT
+ (bitconvert
(DestInfo.VT (X86VBroadcast
(SrcInfo.ScalarLdFrag addr:$src)))))>,
T8PD, EVEX, EVEX_CD8<SrcInfo.EltSize, CD8VT1>;
@@ -1130,7 +1142,7 @@ multiclass avx512_broadcast_rm_split<bit
def : Pat<(MaskInfo.VT
(bitconvert
- (DestInfo.VT (X86VBroadcast
+ (DestInfo.VT (UnmaskedOp
(SrcInfo.VT (scalar_to_vector
(SrcInfo.ScalarLdFrag addr:$src))))))),
(!cast<Instruction>(NAME#MaskInfo.ZSuffix#m) addr:$src)>;
@@ -1486,11 +1498,11 @@ multiclass avx512_common_broadcast_32x2<
AVX512VLVectorVTInfo _Dst, AVX512VLVectorVTInfo _Src> {
let Predicates = [HasDQI] in
defm Z : avx512_broadcast_rm_split<opc, OpcodeStr, _Dst.info512,
- _Src.info512, _Src.info128>,
+ _Src.info512, _Src.info128, null_frag>,
EVEX_V512;
let Predicates = [HasDQI, HasVLX] in
defm Z256 : avx512_broadcast_rm_split<opc, OpcodeStr, _Dst.info256,
- _Src.info256, _Src.info128>,
+ _Src.info256, _Src.info128, null_frag>,
EVEX_V256;
}
@@ -1500,7 +1512,7 @@ multiclass avx512_common_broadcast_i32x2
let Predicates = [HasDQI, HasVLX] in
defm Z128 : avx512_broadcast_rm_split<opc, OpcodeStr, _Dst.info128,
- _Src.info128, _Src.info128>,
+ _Src.info128, _Src.info128, null_frag>,
EVEX_V128;
}
Modified: llvm/trunk/test/CodeGen/X86/avx512-shuffles/broadcast-vector-fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-shuffles/broadcast-vector-fp.ll?rev=315674&r1=315673&r2=315674&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-shuffles/broadcast-vector-fp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-shuffles/broadcast-vector-fp.ll Thu Oct 12 23:07:10 2017
@@ -108,7 +108,7 @@ define <8 x float> @test_masked_z_2xfloa
define <16 x float> @test_2xfloat_to_16xfloat(<16 x float> %vec) {
; CHECK-LABEL: test_2xfloat_to_16xfloat:
; CHECK: # BB#0:
-; CHECK-NEXT: vbroadcastf32x2 {{.*#+}} zmm0 = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
+; CHECK-NEXT: vbroadcastsd %xmm0, %zmm0
; CHECK-NEXT: retq
%res = shufflevector <16 x float> %vec, <16 x float> undef, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
ret <16 x float> %res
@@ -658,7 +658,7 @@ define <16 x float> @test_2xfloat_to_16x
; CHECK-LABEL: test_2xfloat_to_16xfloat_mem:
; CHECK: # BB#0:
; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; CHECK-NEXT: vbroadcastf32x2 {{.*#+}} zmm0 = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
+; CHECK-NEXT: vbroadcastsd %xmm0, %zmm0
; CHECK-NEXT: retq
%vec = load <2 x float>, <2 x float>* %vp
%res = shufflevector <2 x float> %vec, <2 x float> undef, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
Modified: llvm/trunk/test/CodeGen/X86/avx512-shuffles/broadcast-vector-int.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-shuffles/broadcast-vector-int.ll?rev=315674&r1=315673&r2=315674&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-shuffles/broadcast-vector-int.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-shuffles/broadcast-vector-int.ll Thu Oct 12 23:07:10 2017
@@ -110,7 +110,7 @@ define <4 x i32> @test_masked_z_2xi32_to
define <8 x i32> @test_2xi32_to_8xi32(<8 x i32> %vec) {
; CHECK-LABEL: test_2xi32_to_8xi32:
; CHECK: # BB#0:
-; CHECK-NEXT: vpbroadcastq %xmm0, %ymm0
+; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0
; CHECK-NEXT: retq
%res = shufflevector <8 x i32> %vec, <8 x i32> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
ret <8 x i32> %res
@@ -214,7 +214,7 @@ define <8 x i32> @test_masked_z_2xi32_to
define <16 x i32> @test_2xi32_to_16xi32(<16 x i32> %vec) {
; CHECK-LABEL: test_2xi32_to_16xi32:
; CHECK: # BB#0:
-; CHECK-NEXT: vbroadcasti32x2 {{.*#+}} zmm0 = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
+; CHECK-NEXT: vbroadcastsd %xmm0, %zmm0
; CHECK-NEXT: retq
%res = shufflevector <16 x i32> %vec, <16 x i32> undef, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
ret <16 x i32> %res
Modified: llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v8.ll?rev=315674&r1=315673&r2=315674&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v8.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v8.ll Thu Oct 12 23:07:10 2017
@@ -1120,17 +1120,11 @@ define <8 x i32> @shuffle_v8i32_08080808
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: retq
;
-; AVX2-LABEL: shuffle_v8i32_08080808:
-; AVX2: # BB#0:
-; AVX2-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; AVX2-NEXT: vbroadcastsd %xmm0, %ymm0
-; AVX2-NEXT: retq
-;
-; AVX512VL-LABEL: shuffle_v8i32_08080808:
-; AVX512VL: # BB#0:
-; AVX512VL-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; AVX512VL-NEXT: vpbroadcastq %xmm0, %ymm0
-; AVX512VL-NEXT: retq
+; AVX2OR512VL-LABEL: shuffle_v8i32_08080808:
+; AVX2OR512VL: # BB#0:
+; AVX2OR512VL-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; AVX2OR512VL-NEXT: vbroadcastsd %xmm0, %ymm0
+; AVX2OR512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 8, i32 0, i32 8, i32 0, i32 8, i32 0, i32 8>
ret <8 x i32> %shuffle
}
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