[llvm] r315671 - [SelectionDAG] Cleanup the SIGN_EXTEND_INREG handling in computeKnownBits. NFCI
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 12 22:35:35 PDT 2017
Author: ctopper
Date: Thu Oct 12 22:35:35 2017
New Revision: 315671
URL: http://llvm.org/viewvc/llvm-project?rev=315671&view=rev
Log:
[SelectionDAG] Cleanup the SIGN_EXTEND_INREG handling in computeKnownBits. NFCI
Use less temporary APInts. Use bit counting more. Don't call getScalarSizeInBits so many places, just capture it once.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=315671&r1=315670&r2=315671&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Oct 12 22:35:35 2017
@@ -986,15 +986,13 @@ bool TargetLowering::SimplifyDemandedBit
break;
case ISD::SIGN_EXTEND_INREG: {
EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
+ unsigned ExVTBits = ExVT.getScalarSizeInBits();
- APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
// If we only care about the highest bit, don't bother shifting right.
- if (MsbMask == NewMask) {
- unsigned ShAmt = ExVT.getScalarSizeInBits();
+ if (NewMask.isSignMask()) {
SDValue InOp = Op.getOperand(0);
- unsigned VTBits = Op->getValueType(0).getScalarSizeInBits();
bool AlreadySignExtended =
- TLO.DAG.ComputeNumSignBits(InOp) >= VTBits-ShAmt+1;
+ TLO.DAG.ComputeNumSignBits(InOp) >= BitWidth-ExVTBits+1;
// However if the input is already sign extended we expect the sign
// extension to be dropped altogether later and do not simplify.
if (!AlreadySignExtended) {
@@ -1004,7 +1002,7 @@ bool TargetLowering::SimplifyDemandedBit
if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
ShiftAmtTy = getShiftAmountTy(ShiftAmtTy, DL);
- SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, dl,
+ SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ExVTBits, dl,
ShiftAmtTy);
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
Op.getValueType(), InOp,
@@ -1012,26 +1010,15 @@ bool TargetLowering::SimplifyDemandedBit
}
}
- // Sign extension. Compute the demanded bits in the result that are not
- // present in the input.
- APInt NewBits =
- APInt::getHighBitsSet(BitWidth,
- BitWidth - ExVT.getScalarSizeInBits());
-
// If none of the extended bits are demanded, eliminate the sextinreg.
- if ((NewBits & NewMask) == 0)
+ if (NewMask.getActiveBits() <= ExVTBits)
return TLO.CombineTo(Op, Op.getOperand(0));
- APInt InSignBit =
- APInt::getSignMask(ExVT.getScalarSizeInBits()).zext(BitWidth);
- APInt InputDemandedBits =
- APInt::getLowBitsSet(BitWidth,
- ExVT.getScalarSizeInBits()) &
- NewMask;
+ APInt InputDemandedBits = NewMask.getLoBits(ExVTBits);
// Since the sign extended bits are demanded, we know that the sign
// bit is demanded.
- InputDemandedBits |= InSignBit;
+ InputDemandedBits.setBit(ExVTBits - 1);
if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
Known, TLO, Depth+1))
@@ -1042,16 +1029,17 @@ bool TargetLowering::SimplifyDemandedBit
// top bits of the result.
// If the input sign bit is known zero, convert this into a zero extension.
- if (Known.Zero.intersects(InSignBit))
+ if (Known.Zero[ExVTBits - 1])
return TLO.CombineTo(Op, TLO.DAG.getZeroExtendInReg(
Op.getOperand(0), dl, ExVT.getScalarType()));
- if (Known.One.intersects(InSignBit)) { // Input sign bit known set
- Known.One |= NewBits;
- Known.Zero &= ~NewBits;
+ APInt Mask = APInt::getLowBitsSet(BitWidth, ExVTBits);
+ if (Known.One[ExVTBits - 1]) { // Input sign bit known set
+ Known.One.setBitsFrom(ExVTBits);
+ Known.Zero &= Mask;
} else { // Input sign bit unknown
- Known.Zero &= ~NewBits;
- Known.One &= ~NewBits;
+ Known.Zero &= Mask;
+ Known.One &= Mask;
}
break;
}
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