[PATCH] D38196: [AArch64] Avoid interleaved SIMD store instructions for Exynos

[Abderrazek Zaafrani via Phabricator via llvm-commits]

az marked 3 inline comments as done.
az added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64VectorByElementOpt.cpp:492-554
+  switch (MI.getOpcode()) {
+  default:
+    return false;
+  // ST2 case
+  case AArch64::ST2Twov2d:
+    prepareStmtParam(AArch64::ZIP1v2i64, AArch64::ZIP2v2i64, RC128, ReplInstrMCID,
+      ZipDest, TwoVectors);
----------------
kristof.beyls wrote:
> I think this code might get easier to understand/maintain if the `prepareStmtParam` call happened after the switch, and in the switch, there would only be functionality where the different case statements actually differ. e.g. something like:
> 
> 
> ```
> switch (...) {
>   case A:
>      Zip1 = Zip1v16i8; Zip2=ZIP2v16i8; RC=RC64; NumVec = FourVectors;
>   case B:
>      Zip1 = Zip1v8i8; Zip2=ZIP2v8i8; RC=RC64; NumVec = FourVectors;
>   ...
> }
> prepareStmtParam(Zip1, Zip2, RC, NumVec)
> ```
> 
> Or maybe it would be even easier if this switch would be pulled apart into 4 switch statements, each setting one of Zip1/Zip2/RC/NumVec variables in the example above?
> What do you think?
Went with the first suggestion. The code already has two switch statements to handle common code and non-common code. Prefer not subdivide more. 


https://reviews.llvm.org/D38196