[llvm] r315523 - AMDGPU/NFC: Minor clean ups in PAL metadata
Konstantin Zhuravlyov via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 11 15:41:09 PDT 2017
Author: kzhuravl
Date: Wed Oct 11 15:41:09 2017
New Revision: 315523
URL: http://llvm.org/viewvc/llvm-project?rev=315523&view=rev
Log:
AMDGPU/NFC: Minor clean ups in PAL metadata
- Move PAL metadata definitions to AMDGPUMetadata
- Make naming consistent with HSA metadata
Differential Revision: https://reviews.llvm.org/D38745
Modified:
llvm/trunk/include/llvm/Support/AMDGPUMetadata.h
llvm/trunk/lib/Support/AMDGPUMetadata.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
llvm/trunk/lib/Target/AMDGPU/AMDGPUPTNote.h
llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
llvm/trunk/test/CodeGen/AMDGPU/amdpal-cs.ll
llvm/trunk/test/CodeGen/AMDGPU/amdpal-es.ll
llvm/trunk/test/CodeGen/AMDGPU/amdpal-gs.ll
llvm/trunk/test/CodeGen/AMDGPU/amdpal-hs.ll
llvm/trunk/test/CodeGen/AMDGPU/amdpal-ls.ll
llvm/trunk/test/CodeGen/AMDGPU/amdpal-ps.ll
llvm/trunk/test/CodeGen/AMDGPU/amdpal-vs.ll
llvm/trunk/test/MC/AMDGPU/pal.s
Modified: llvm/trunk/include/llvm/Support/AMDGPUMetadata.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/AMDGPUMetadata.h?rev=315523&r1=315522&r2=315523&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/AMDGPUMetadata.h (original)
+++ llvm/trunk/include/llvm/Support/AMDGPUMetadata.h Wed Oct 11 15:41:09 2017
@@ -417,6 +417,49 @@ struct Metadata final {
};
} // end namespace HSAMD
+
+//===----------------------------------------------------------------------===//
+// PAL metadata.
+//===----------------------------------------------------------------------===//
+namespace PALMD {
+
+/// \brief PAL metadata assembler directive.
+constexpr char AssemblerDirective[] = ".amd_amdgpu_pal_metadata";
+
+/// \brief PAL metadata keys.
+enum Key : uint32_t {
+ LS_NUM_USED_VGPRS = 0x10000015,
+ HS_NUM_USED_VGPRS = 0x10000016,
+ ES_NUM_USED_VGPRS = 0x10000017,
+ GS_NUM_USED_VGPRS = 0x10000018,
+ VS_NUM_USED_VGPRS = 0x10000019,
+ PS_NUM_USED_VGPRS = 0x1000001a,
+ CS_NUM_USED_VGPRS = 0x1000001b,
+
+ LS_NUM_USED_SGPRS = 0x1000001c,
+ HS_NUM_USED_SGPRS = 0x1000001d,
+ ES_NUM_USED_SGPRS = 0x1000001e,
+ GS_NUM_USED_SGPRS = 0x1000001f,
+ VS_NUM_USED_SGPRS = 0x10000020,
+ PS_NUM_USED_SGPRS = 0x10000021,
+ CS_NUM_USED_SGPRS = 0x10000022,
+
+ LS_SCRATCH_SIZE = 0x10000038,
+ HS_SCRATCH_SIZE = 0x10000039,
+ ES_SCRATCH_SIZE = 0x1000003a,
+ GS_SCRATCH_SIZE = 0x1000003b,
+ VS_SCRATCH_SIZE = 0x1000003c,
+ PS_SCRATCH_SIZE = 0x1000003d,
+ CS_SCRATCH_SIZE = 0x1000003e
+};
+
+/// \brief PAL metadata represented as a vector.
+typedef std::vector<uint32_t> Metadata;
+
+/// \brief Converts \p PALMetadata to \p String.
+std::error_code toString(const Metadata &PALMetadata, std::string &String);
+
+} // end namespace PALMD
} // end namespace AMDGPU
} // end namespace llvm
Modified: llvm/trunk/lib/Support/AMDGPUMetadata.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/AMDGPUMetadata.cpp?rev=315523&r1=315522&r2=315523&view=diff
==============================================================================
--- llvm/trunk/lib/Support/AMDGPUMetadata.cpp (original)
+++ llvm/trunk/lib/Support/AMDGPUMetadata.cpp Wed Oct 11 15:41:09 2017
@@ -13,6 +13,7 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/ADT/Twine.h"
#include "llvm/Support/AMDGPUMetadata.h"
#include "llvm/Support/YAMLTraits.h"
@@ -213,5 +214,19 @@ std::error_code Metadata::toYamlString(
}
} // end namespace HSAMD
+
+namespace PALMD {
+
+std::error_code toString(const Metadata &PALMetadata, std::string &String) {
+ raw_string_ostream Stream(String);
+ for (auto I = PALMetadata.begin(), E = PALMetadata.end(); I != E; ++I) {
+ Stream << Twine(I == PALMetadata.begin() ? " 0x" : ",0x");
+ Stream << Twine::utohexstr(*I);
+ }
+ Stream.flush();
+ return std::error_code();
+}
+
+} // end namespace PALMD
} // end namespace AMDGPU
} // end namespace llvm
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp?rev=315523&r1=315522&r2=315523&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp Wed Oct 11 15:41:09 2017
@@ -36,11 +36,13 @@
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCSectionELF.h"
#include "llvm/MC/MCStreamer.h"
+#include "llvm/Support/AMDGPUMetadata.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
using namespace llvm;
+using namespace llvm::AMDGPU;
// TODO: This should get the default rounding mode from the kernel. We just set
// the default here, but this could change if the OpenCL rounding mode pragmas
@@ -114,7 +116,7 @@ void AMDGPUAsmPrinter::EmitStartOfAsmFil
AMDGPU::IsaInfo::getIsaVersion(getSTI()->getFeatureBits());
if (TM.getTargetTriple().getOS() == Triple::AMDPAL) {
- readPalMetadata(M);
+ readPALMetadata(M);
// AMDPAL wants an HSA_ISA .note.
getTargetStreamer().EmitDirectiveHSACodeObjectISA(
ISA.Major, ISA.Minor, ISA.Stepping, "AMD", "AMDGPU");
@@ -132,12 +134,12 @@ void AMDGPUAsmPrinter::EmitEndOfAsmFile(
if (TM.getTargetTriple().getOS() == Triple::AMDPAL) {
// Copy the PAL metadata from the map where we collected it into a vector,
// then write it as a .note.
- std::vector<uint32_t> Data;
- for (auto i : PalMetadata) {
- Data.push_back(i.first);
- Data.push_back(i.second);
+ PALMD::Metadata PALMetadataVector;
+ for (auto i : PALMetadataMap) {
+ PALMetadataVector.push_back(i.first);
+ PALMetadataVector.push_back(i.second);
}
- getTargetStreamer().EmitPalMetadata(Data);
+ getTargetStreamer().EmitPALMetadata(PALMetadataVector);
}
if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
@@ -207,11 +209,11 @@ bool AMDGPUAsmPrinter::doFinalization(Mo
}
// For the amdpal OS type, read the amdgpu.pal.metadata supplied by the
-// frontend into our PalMetadata map, ready for per-function modification. It
+// frontend into our PALMetadataMap, ready for per-function modification. It
// is a NamedMD containing an MDTuple containing a number of MDNodes each of
// which is an integer value, and each two integer values forms a key=value
-// pair that we store as PalMetadata[key]=value in the map.
-void AMDGPUAsmPrinter::readPalMetadata(Module &M) {
+// pair that we store as PALMetadataMap[key]=value in the map.
+void AMDGPUAsmPrinter::readPALMetadata(Module &M) {
auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
if (!NamedMD || !NamedMD->getNumOperands())
return;
@@ -223,7 +225,7 @@ void AMDGPUAsmPrinter::readPalMetadata(M
auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1));
if (!Key || !Val)
continue;
- PalMetadata[Key->getZExtValue()] = Val->getZExtValue();
+ PALMetadataMap[Key->getZExtValue()] = Val->getZExtValue();
}
}
@@ -270,7 +272,7 @@ bool AMDGPUAsmPrinter::runOnMachineFunct
}
if (STM.isAmdPalOS())
- EmitPalMetadata(MF, CurrentProgramInfo);
+ EmitPALMetadata(MF, CurrentProgramInfo);
if (!STM.isAmdHsaOS()) {
EmitProgramInfoSI(MF, CurrentProgramInfo);
}
@@ -964,10 +966,10 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI
// This is the equivalent of EmitProgramInfoSI above, but for when the OS type
// is AMDPAL. It stores each compute/SPI register setting and other PAL
-// metadata items into the PalMetadata map, combining with any provided by the
-// frontend as LLVM metadata. Once all functions are written, PalMetadata is
+// metadata items into the PALMetadataMap, combining with any provided by the
+// frontend as LLVM metadata. Once all functions are written, PALMetadataMap is
// then written as a single block in the .note section.
-void AMDGPUAsmPrinter::EmitPalMetadata(const MachineFunction &MF,
+void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
const SIProgramInfo &CurrentProgramInfo) {
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
// Given the calling convention, calculate the register number for rsrc1. In
@@ -981,52 +983,53 @@ void AMDGPUAsmPrinter::EmitPalMetadata(c
// Also calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
// with a constant offset to access any non-register shader-specific PAL
// metadata key.
- unsigned ScratchSizeKey = AMDGPU::ElfNote::AMDGPU_PAL_METADATA_CS_SCRATCH_SIZE;
+ unsigned ScratchSizeKey = PALMD::Key::CS_SCRATCH_SIZE;
switch (MF.getFunction()->getCallingConv()) {
case CallingConv::AMDGPU_PS:
- ScratchSizeKey = AMDGPU::ElfNote::AMDGPU_PAL_METADATA_PS_SCRATCH_SIZE;
+ ScratchSizeKey = PALMD::Key::PS_SCRATCH_SIZE;
break;
case CallingConv::AMDGPU_VS:
- ScratchSizeKey = AMDGPU::ElfNote::AMDGPU_PAL_METADATA_VS_SCRATCH_SIZE;
+ ScratchSizeKey = PALMD::Key::VS_SCRATCH_SIZE;
break;
case CallingConv::AMDGPU_GS:
- ScratchSizeKey = AMDGPU::ElfNote::AMDGPU_PAL_METADATA_GS_SCRATCH_SIZE;
+ ScratchSizeKey = PALMD::Key::GS_SCRATCH_SIZE;
break;
case CallingConv::AMDGPU_ES:
- ScratchSizeKey = AMDGPU::ElfNote::AMDGPU_PAL_METADATA_ES_SCRATCH_SIZE;
+ ScratchSizeKey = PALMD::Key::ES_SCRATCH_SIZE;
break;
case CallingConv::AMDGPU_HS:
- ScratchSizeKey = AMDGPU::ElfNote::AMDGPU_PAL_METADATA_HS_SCRATCH_SIZE;
+ ScratchSizeKey = PALMD::Key::HS_SCRATCH_SIZE;
break;
case CallingConv::AMDGPU_LS:
- ScratchSizeKey = AMDGPU::ElfNote::AMDGPU_PAL_METADATA_LS_SCRATCH_SIZE;
+ ScratchSizeKey = PALMD::Key::LS_SCRATCH_SIZE;
break;
}
- unsigned NumUsedVgprsKey = ScratchSizeKey
- + AMDGPU::ElfNote::AMDGPU_PAL_METADATA_VS_NUM_USED_VGPRS
- - AMDGPU::ElfNote::AMDGPU_PAL_METADATA_VS_SCRATCH_SIZE;
- unsigned NumUsedSgprsKey = ScratchSizeKey
- + AMDGPU::ElfNote::AMDGPU_PAL_METADATA_VS_NUM_USED_SGPRS
- - AMDGPU::ElfNote::AMDGPU_PAL_METADATA_VS_SCRATCH_SIZE;
- PalMetadata[NumUsedVgprsKey] = CurrentProgramInfo.NumVGPRsForWavesPerEU;
- PalMetadata[NumUsedSgprsKey] = CurrentProgramInfo.NumSGPRsForWavesPerEU;
+ unsigned NumUsedVgprsKey = ScratchSizeKey +
+ PALMD::Key::VS_NUM_USED_VGPRS - PALMD::Key::VS_SCRATCH_SIZE;
+ unsigned NumUsedSgprsKey = ScratchSizeKey +
+ PALMD::Key::VS_NUM_USED_SGPRS - PALMD::Key::VS_SCRATCH_SIZE;
+ PALMetadataMap[NumUsedVgprsKey] = CurrentProgramInfo.NumVGPRsForWavesPerEU;
+ PALMetadataMap[NumUsedSgprsKey] = CurrentProgramInfo.NumSGPRsForWavesPerEU;
if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
- PalMetadata[Rsrc1Reg] |= CurrentProgramInfo.ComputePGMRSrc1;
- PalMetadata[Rsrc2Reg] |= CurrentProgramInfo.ComputePGMRSrc2;
+ PALMetadataMap[Rsrc1Reg] |= CurrentProgramInfo.ComputePGMRSrc1;
+ PALMetadataMap[Rsrc2Reg] |= CurrentProgramInfo.ComputePGMRSrc2;
// ScratchSize is in bytes, 16 aligned.
- PalMetadata[ScratchSizeKey] |= alignTo(CurrentProgramInfo.ScratchSize, 16);
+ PALMetadataMap[ScratchSizeKey] |=
+ alignTo(CurrentProgramInfo.ScratchSize, 16);
} else {
- PalMetadata[Rsrc1Reg] |= S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks)
- | S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks);
+ PALMetadataMap[Rsrc1Reg] |= S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
+ S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks);
if (CurrentProgramInfo.ScratchBlocks > 0)
- PalMetadata[Rsrc2Reg] |= S_00B84C_SCRATCH_EN(1);
+ PALMetadataMap[Rsrc2Reg] |= S_00B84C_SCRATCH_EN(1);
// ScratchSize is in bytes, 16 aligned.
- PalMetadata[ScratchSizeKey] |= alignTo(CurrentProgramInfo.ScratchSize, 16);
+ PALMetadataMap[ScratchSizeKey] |=
+ alignTo(CurrentProgramInfo.ScratchSize, 16);
}
if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
- PalMetadata[Rsrc2Reg] |= S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks);
- PalMetadata[R_0286CC_SPI_PS_INPUT_ENA / 4] |= MFI->getPSInputEnable();
- PalMetadata[R_0286D0_SPI_PS_INPUT_ADDR / 4] |= MFI->getPSInputAddr();
+ PALMetadataMap[Rsrc2Reg] |=
+ S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks);
+ PALMetadataMap[R_0286CC_SPI_PS_INPUT_ENA / 4] |= MFI->getPSInputEnable();
+ PALMetadataMap[R_0286D0_SPI_PS_INPUT_ADDR / 4] |= MFI->getPSInputAddr();
}
}
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.h?rev=315523&r1=315522&r2=315523&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.h Wed Oct 11 15:41:09 2017
@@ -112,12 +112,12 @@ private:
SIProgramInfo CurrentProgramInfo;
DenseMap<const Function *, SIFunctionResourceInfo> CallGraphResourceInfo;
- std::map<uint32_t, uint32_t> PalMetadata;
+ std::map<uint32_t, uint32_t> PALMetadataMap;
uint64_t getFunctionCodeSize(const MachineFunction &MF) const;
SIFunctionResourceInfo analyzeResourceUsage(const MachineFunction &MF) const;
- void readPalMetadata(Module &M);
+ void readPALMetadata(Module &M);
void getSIProgramInfo(SIProgramInfo &Out, const MachineFunction &MF);
void getAmdKernelCode(amd_kernel_code_t &Out, const SIProgramInfo &KernelInfo,
const MachineFunction &MF) const;
@@ -128,8 +128,10 @@ private:
/// \brief Emit register usage information so that the GPU driver
/// can correctly setup the GPU state.
void EmitProgramInfoR600(const MachineFunction &MF);
- void EmitProgramInfoSI(const MachineFunction &MF, const SIProgramInfo &KernelInfo);
- void EmitPalMetadata(const MachineFunction &MF, const SIProgramInfo &KernelInfo);
+ void EmitProgramInfoSI(const MachineFunction &MF,
+ const SIProgramInfo &KernelInfo);
+ void EmitPALMetadata(const MachineFunction &MF,
+ const SIProgramInfo &KernelInfo);
void emitCommonFunctionComments(uint32_t NumVGPR,
uint32_t NumSGPR,
uint32_t ScratchSize,
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUPTNote.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUPTNote.h?rev=315523&r1=315522&r2=315523&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUPTNote.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUPTNote.h Wed Oct 11 15:41:09 2017
@@ -44,32 +44,6 @@ enum NoteType{
NT_AMDGPU_HSA_HLDEBUG_TARGET = 102
};
-enum NoteAmdGpuPalMetadataKey {
- AMDGPU_PAL_METADATA_LS_NUM_USED_VGPRS = 0x10000015,
- AMDGPU_PAL_METADATA_HS_NUM_USED_VGPRS = 0x10000016,
- AMDGPU_PAL_METADATA_ES_NUM_USED_VGPRS = 0x10000017,
- AMDGPU_PAL_METADATA_GS_NUM_USED_VGPRS = 0x10000018,
- AMDGPU_PAL_METADATA_VS_NUM_USED_VGPRS = 0x10000019,
- AMDGPU_PAL_METADATA_PS_NUM_USED_VGPRS = 0x1000001a,
- AMDGPU_PAL_METADATA_CS_NUM_USED_VGPRS = 0x1000001b,
-
- AMDGPU_PAL_METADATA_LS_NUM_USED_SGPRS = 0x1000001c,
- AMDGPU_PAL_METADATA_HS_NUM_USED_SGPRS = 0x1000001d,
- AMDGPU_PAL_METADATA_ES_NUM_USED_SGPRS = 0x1000001e,
- AMDGPU_PAL_METADATA_GS_NUM_USED_SGPRS = 0x1000001f,
- AMDGPU_PAL_METADATA_VS_NUM_USED_SGPRS = 0x10000020,
- AMDGPU_PAL_METADATA_PS_NUM_USED_SGPRS = 0x10000021,
- AMDGPU_PAL_METADATA_CS_NUM_USED_SGPRS = 0x10000022,
-
- AMDGPU_PAL_METADATA_LS_SCRATCH_SIZE = 0x10000038,
- AMDGPU_PAL_METADATA_HS_SCRATCH_SIZE = 0x10000039,
- AMDGPU_PAL_METADATA_ES_SCRATCH_SIZE = 0x1000003a,
- AMDGPU_PAL_METADATA_GS_SCRATCH_SIZE = 0x1000003b,
- AMDGPU_PAL_METADATA_VS_SCRATCH_SIZE = 0x1000003c,
- AMDGPU_PAL_METADATA_PS_SCRATCH_SIZE = 0x1000003d,
- AMDGPU_PAL_METADATA_CS_SCRATCH_SIZE = 0x1000003e,
-};
-
}
}
Modified: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=315523&r1=315522&r2=315523&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Wed Oct 11 15:41:09 2017
@@ -832,7 +832,9 @@ private:
bool ParseDirectiveAMDKernelCodeT();
bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo) const;
bool ParseDirectiveAMDGPUHsaKernel();
- bool ParseDirectivePalMetadata();
+
+ bool ParseDirectivePALMetadata();
+
bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth,
RegisterKind RegKind, unsigned Reg1,
unsigned RegNum);
@@ -2493,18 +2495,20 @@ bool AMDGPUAsmParser::ParseDirectiveAMDG
return false;
}
-bool AMDGPUAsmParser::ParseDirectivePalMetadata() {
- std::vector<uint32_t> Data;
+bool AMDGPUAsmParser::ParseDirectivePALMetadata() {
+ PALMD::Metadata PALMetadata;
for (;;) {
uint32_t Value;
- if (ParseAsAbsoluteExpression(Value))
- return TokError("invalid value in .amdgpu_pal_metadata");
- Data.push_back(Value);
+ if (ParseAsAbsoluteExpression(Value)) {
+ return TokError(Twine("invalid value in ") +
+ Twine(PALMD::AssemblerDirective));
+ }
+ PALMetadata.push_back(Value);
if (getLexer().isNot(AsmToken::Comma))
break;
Lex();
}
- getTargetStreamer().EmitPalMetadata(Data);
+ getTargetStreamer().EmitPALMetadata(PALMetadata);
return false;
}
@@ -2526,8 +2530,8 @@ bool AMDGPUAsmParser::ParseDirective(Asm
if (IDVal == ".amdgpu_hsa_kernel")
return ParseDirectiveAMDGPUHsaKernel();
- if (IDVal == ".amdgpu_pal_metadata")
- return ParseDirectivePalMetadata();
+ if (IDVal == PALMD::AssemblerDirective)
+ return ParseDirectivePALMetadata();
return true;
}
Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp?rev=315523&r1=315522&r2=315523&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp Wed Oct 11 15:41:09 2017
@@ -112,11 +112,14 @@ bool AMDGPUTargetAsmStreamer::EmitHSAMet
return true;
}
-bool AMDGPUTargetAsmStreamer::EmitPalMetadata(ArrayRef<uint32_t> Data) {
- OS << "\t.amdgpu_pal_metadata";
- for (auto I = Data.begin(), E = Data.end(); I != E; ++I)
- OS << (I == Data.begin() ? " 0x" : ",0x") << Twine::utohexstr(*I);
- OS << "\n";
+bool AMDGPUTargetAsmStreamer::EmitPALMetadata(
+ const PALMD::Metadata &PALMetadata) {
+ std::string PALMetadataString;
+ auto Error = PALMD::toString(PALMetadata, PALMetadataString);
+ if (Error)
+ return false;
+
+ OS << '\t' << PALMD::AssemblerDirective << PALMetadataString << '\n';
return true;
}
@@ -239,15 +242,15 @@ bool AMDGPUTargetELFStreamer::EmitHSAMet
return true;
}
-bool AMDGPUTargetELFStreamer::EmitPalMetadata(ArrayRef<uint32_t> Data) {
+bool AMDGPUTargetELFStreamer::EmitPALMetadata(
+ const PALMD::Metadata &PALMetadata) {
EmitAMDGPUNote(
- MCConstantExpr::create(Data.size() * sizeof(uint32_t), getContext()),
+ MCConstantExpr::create(PALMetadata.size() * sizeof(uint32_t), getContext()),
ElfNote::NT_AMDGPU_PAL_METADATA,
[&](MCELFStreamer &OS){
- for (auto I : Data)
+ for (auto I : PALMetadata)
OS.EmitIntValue(I, sizeof(uint32_t));
}
);
return true;
}
-
Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h?rev=315523&r1=315522&r2=315523&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h Wed Oct 11 15:41:09 2017
@@ -54,7 +54,8 @@ public:
/// \returns True on success, false on failure.
virtual bool EmitHSAMetadata(StringRef YamlString) = 0;
- virtual bool EmitPalMetadata(ArrayRef<uint32_t> Data) = 0;
+ /// \returns True on success, false on failure.
+ virtual bool EmitPALMetadata(const AMDGPU::PALMD::Metadata &PALMetadata) = 0;
};
class AMDGPUTargetAsmStreamer final : public AMDGPUTargetStreamer {
@@ -75,7 +76,8 @@ public:
/// \returns True on success, false on failure.
bool EmitHSAMetadata(StringRef YamlString) override;
- bool EmitPalMetadata(ArrayRef<uint32_t> data) override;
+ /// \returns True on success, false on failure.
+ bool EmitPALMetadata(const AMDGPU::PALMD::Metadata &PALMetadata) override;
};
class AMDGPUTargetELFStreamer final : public AMDGPUTargetStreamer {
@@ -104,7 +106,8 @@ public:
/// \returns True on success, false on failure.
bool EmitHSAMetadata(StringRef YamlString) override;
- bool EmitPalMetadata(ArrayRef<uint32_t> data) override;
+ /// \returns True on success, false on failure.
+ bool EmitPALMetadata(const AMDGPU::PALMD::Metadata &PALMetadata) override;
};
}
Modified: llvm/trunk/test/CodeGen/AMDGPU/amdpal-cs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/amdpal-cs.ll?rev=315523&r1=315522&r2=315523&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/amdpal-cs.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/amdpal-cs.ll Wed Oct 11 15:41:09 2017
@@ -4,7 +4,7 @@
; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata
; GCN-LABEL: {{^}}cs_amdpal:
-; GCN: .amdgpu_pal_metadata{{.*}}0x2e12,
+; GCN: .amd_amdgpu_pal_metadata{{.*}}0x2e12,
define amdgpu_cs half @cs_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
Modified: llvm/trunk/test/CodeGen/AMDGPU/amdpal-es.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/amdpal-es.ll?rev=315523&r1=315522&r2=315523&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/amdpal-es.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/amdpal-es.ll Wed Oct 11 15:41:09 2017
@@ -3,7 +3,7 @@
; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata
; GCN-LABEL: {{^}}es_amdpal:
-; GCN: .amdgpu_pal_metadata{{.*}}0x2cca,
+; GCN: .amd_amdgpu_pal_metadata{{.*}}0x2cca,
define amdgpu_es half @es_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
Modified: llvm/trunk/test/CodeGen/AMDGPU/amdpal-gs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/amdpal-gs.ll?rev=315523&r1=315522&r2=315523&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/amdpal-gs.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/amdpal-gs.ll Wed Oct 11 15:41:09 2017
@@ -4,7 +4,7 @@
; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata
; GCN-LABEL: {{^}}gs_amdpal:
-; GCN: .amdgpu_pal_metadata{{.*}}0x2c8a,
+; GCN: .amd_amdgpu_pal_metadata{{.*}}0x2c8a,
define amdgpu_gs half @gs_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
Modified: llvm/trunk/test/CodeGen/AMDGPU/amdpal-hs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/amdpal-hs.ll?rev=315523&r1=315522&r2=315523&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/amdpal-hs.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/amdpal-hs.ll Wed Oct 11 15:41:09 2017
@@ -4,7 +4,7 @@
; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata
; GCN-LABEL: {{^}}hs_amdpal:
-; GCN: .amdgpu_pal_metadata{{.*}}0x2d0a,
+; GCN: .amd_amdgpu_pal_metadata{{.*}}0x2d0a,
define amdgpu_hs half @hs_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
Modified: llvm/trunk/test/CodeGen/AMDGPU/amdpal-ls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/amdpal-ls.ll?rev=315523&r1=315522&r2=315523&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/amdpal-ls.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/amdpal-ls.ll Wed Oct 11 15:41:09 2017
@@ -3,7 +3,7 @@
; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata
; GCN-LABEL: {{^}}ls_amdpal:
-; GCN: .amdgpu_pal_metadata{{.*}}0x2d4a,
+; GCN: .amd_amdgpu_pal_metadata{{.*}}0x2d4a,
define amdgpu_ls half @ls_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
Modified: llvm/trunk/test/CodeGen/AMDGPU/amdpal-ps.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/amdpal-ps.ll?rev=315523&r1=315522&r2=315523&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/amdpal-ps.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/amdpal-ps.ll Wed Oct 11 15:41:09 2017
@@ -7,7 +7,7 @@
; it has a value starting 0x42 as it is set to 0x42000000 in the metadata
; below. Also check that key 0x10000000 value 0x12345678 is propagated.
; GCN-LABEL: {{^}}ps_amdpal:
-; GCN: .amdgpu_pal_metadata{{.*0x2c0a,[^,]*,0x2c0b,0x42.*,0x10000000,0x12345678}}
+; GCN: .amd_amdgpu_pal_metadata{{.*0x2c0a,[^,]*,0x2c0b,0x42.*,0x10000000,0x12345678}}
define amdgpu_ps half @ps_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
Modified: llvm/trunk/test/CodeGen/AMDGPU/amdpal-vs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/amdpal-vs.ll?rev=315523&r1=315522&r2=315523&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/amdpal-vs.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/amdpal-vs.ll Wed Oct 11 15:41:09 2017
@@ -4,7 +4,7 @@
; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata
; GCN-LABEL: {{^}}vs_amdpal:
-; GCN: .amdgpu_pal_metadata{{.*}}0x2c4a,
+; GCN: .amd_amdgpu_pal_metadata{{.*}}0x2c4a,
define amdgpu_vs half @vs_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
Modified: llvm/trunk/test/MC/AMDGPU/pal.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/pal.s?rev=315523&r1=315522&r2=315523&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/pal.s (original)
+++ llvm/trunk/test/MC/AMDGPU/pal.s Wed Oct 11 15:41:09 2017
@@ -1,8 +1,8 @@
// RUN: llvm-mc -triple amdgcn--amdpal -mcpu=kaveri -show-encoding %s | FileCheck %s --check-prefix=ASM
// RUN: llvm-mc -filetype=obj -triple amdgcn--amdpal -mcpu=kaveri -show-encoding %s | llvm-readobj -symbols -s -sd | FileCheck %s --check-prefix=ELF
-.amdgpu_pal_metadata 0x12345678, 0xfedcba98, 0x2468ace0, 0xfdb97531
-// ASM: .amdgpu_pal_metadata 0x12345678,0xfedcba98,0x2468ace0,0xfdb97531
+.amd_amdgpu_pal_metadata 0x12345678, 0xfedcba98, 0x2468ace0, 0xfdb97531
+// ASM: .amd_amdgpu_pal_metadata 0x12345678,0xfedcba98,0x2468ace0,0xfdb97531
// ELF: SHT_NOTE
// ELF: 0000: 04000000 10000000 0C000000 414D4400
// ELF: 0010: 78563412 98BADCFE E0AC6824 3175B9FD
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