[llvm] r315510 - [Hexagon] Make sure that new-value jump is packetized with producer

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Wed Oct 11 14:20:43 2017
New Revision: 315510

URL: http://llvm.org/viewvc/llvm-project?rev=315510&view=rev
Log:
[Hexagon] Make sure that new-value jump is packetized with producer

Added:
    llvm/trunk/test/CodeGen/Hexagon/packetize-nvj-no-prune.mir
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp?rev=315510&r1=315509&r2=315510&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp Wed Oct 11 14:20:43 2017
@@ -1338,11 +1338,9 @@ bool HexagonPacketizerList::isLegalToPac
     if (NOp1.isReg() && I.getOperand(0).getReg() == NOp1.getReg())
       secondRegMatch = true;
 
-    for (auto T : CurrentPacketMIs) {
-      SUnit *PacketSU = MIToSUnit.find(T)->second;
-      MachineInstr &PI = *PacketSU->getInstr();
+    for (MachineInstr *PI : CurrentPacketMIs) {
       // NVJ can not be part of the dual jump - Arch Spec: section 7.8.
-      if (PI.isCall()) {
+      if (PI->isCall()) {
         Dependence = true;
         break;
       }
@@ -1354,22 +1352,22 @@ bool HexagonPacketizerList::isLegalToPac
       // 3. If the second operand of the nvj is newified, (which means
       //    first operand is also a reg), first reg is not defined in
       //    the same packet.
-      if (PI.getOpcode() == Hexagon::S2_allocframe || PI.mayStore() ||
-          HII->isLoopN(PI)) {
+      if (PI->getOpcode() == Hexagon::S2_allocframe || PI->mayStore() ||
+          HII->isLoopN(*PI)) {
         Dependence = true;
         break;
       }
       // Check #2/#3.
       const MachineOperand &OpR = secondRegMatch ? NOp0 : NOp1;
-      if (OpR.isReg() && PI.modifiesRegister(OpR.getReg(), HRI)) {
+      if (OpR.isReg() && PI->modifiesRegister(OpR.getReg(), HRI)) {
         Dependence = true;
         break;
       }
     }
 
+    GlueToNewValueJump = true;
     if (Dependence)
       return false;
-    GlueToNewValueJump = true;
   }
 
   // There no dependency between a prolog instruction and its successor.
@@ -1613,7 +1611,15 @@ bool HexagonPacketizerList::isLegalToPru
 
   if (ChangedOffset != INT64_MAX)
     undoChangedOffset(I);
-  else if (updateOffset(SUI, SUJ)) {
+
+  if (GlueToNewValueJump) {
+    // Putting I and J together would prevent the new-value jump from being
+    // packetized with the producer. In that case I and J must be separated.
+    GlueToNewValueJump = false;
+    return false;
+  }
+
+  if (ChangedOffset == INT64_MAX && updateOffset(SUI, SUJ)) {
     FoundSequentialDependence = false;
     Dependence = false;
     return true;

Added: llvm/trunk/test/CodeGen/Hexagon/packetize-nvj-no-prune.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/packetize-nvj-no-prune.mir?rev=315510&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/packetize-nvj-no-prune.mir (added)
+++ llvm/trunk/test/CodeGen/Hexagon/packetize-nvj-no-prune.mir Wed Oct 11 14:20:43 2017
@@ -0,0 +1,31 @@
+# RUN: llc -march=hexagon -run-pass hexagon-packetizer %s -o - | FileCheck %s
+
+# Make sure that the new-value jump is packetized with the producer. In this
+# case, the loads cold be packetized together (with updating the offset in
+# the second load), but then the new-value jump would not be possible to
+# put in the same packet.
+
+# CHECK-LABEL: name: fred
+# CHECK: BUNDLE
+# CHECK-NEXT: %r3 = L2_loadri_io %r1, 0
+# CHECK-NEXT: J4_cmpgtu_f_jumpnv_t internal killed %r3
+
+
+--- |
+  define void @fred() { ret void }
+  @array = external global [256 x i32], align 8
+...
+
+---
+name: fred
+tracksRegLiveness: true
+body: |
+  bb.0:
+    successors: %bb.1
+    %r1 = A2_tfrsi @array
+    %r2, %r1 = L2_loadri_pi %r1, 4
+    %r3 = L2_loadri_io %r1, 0
+    J4_cmpgtu_f_jumpnv_t killed %r3, killed %r2, %bb.1, implicit-def %pc
+
+  bb.1:
+...