[llvm] r315468 - [Pipeliner] Fix offset value for instrs dependent on post-inc load/stores

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Wed Oct 11 08:59:51 2017
New Revision: 315468

URL: http://llvm.org/viewvc/llvm-project?rev=315468&view=rev
Log:
[Pipeliner] Fix offset value for instrs dependent on post-inc load/stores

The software pipeliner and the packetizer try to break dependence
between the post-increment instruction and the dependent memory
instructions by changing the base register and the offset value.
However, in some cases, the existing logic didn't work properly
and created incorrect offset value.

Patch by Jyotsna Verma.

Modified:
    llvm/trunk/lib/CodeGen/MachinePipeliner.cpp
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp

Modified: llvm/trunk/lib/CodeGen/MachinePipeliner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachinePipeliner.cpp?rev=315468&r1=315467&r2=315468&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachinePipeliner.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachinePipeliner.cpp Wed Oct 11 08:59:51 2017
@@ -3892,9 +3892,14 @@ void SwingSchedulerDAG::fixupRegisterOve
           unsigned BasePos, OffsetPos;
           // Update the base register and adjust the offset.
           if (TII->getBaseAndOffsetPosition(*MI, BasePos, OffsetPos)) {
-            MI->getOperand(BasePos).setReg(NewBaseReg);
-            int64_t Offset = MI->getOperand(OffsetPos).getImm();
-            MI->getOperand(OffsetPos).setImm(Offset - It->second.second);
+            MachineInstr *NewMI = MF.CloneMachineInstr(MI);
+            NewMI->getOperand(BasePos).setReg(NewBaseReg);
+            int64_t NewOffset =
+                MI->getOperand(OffsetPos).getImm() - It->second.second;
+            NewMI->getOperand(OffsetPos).setImm(NewOffset);
+            SU->setInstr(NewMI);
+            MISUnitMap[NewMI] = SU;
+            NewMIs.insert(NewMI);
           }
         }
         OverlapReg = 0;

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=315468&r1=315467&r2=315468&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Wed Oct 11 08:59:51 2017
@@ -1651,13 +1651,14 @@ bool HexagonInstrInfo::areMemAccessesTri
 bool HexagonInstrInfo::getIncrementValue(const MachineInstr &MI,
       int &Value) const {
   if (isPostIncrement(MI)) {
-    // For a post-increment, the offset is zero and the increment value is
-    // determined by the instruction's access size.
-    int Zero;
-    unsigned AccessSize;
-    bool RetVal = getBaseAndOffset(MI, Zero, AccessSize);
-    Value = (int) AccessSize;
-    return RetVal;
+    unsigned BasePos = 0, OffsetPos = 0;
+    if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
+      return false;
+    const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
+    if (OffsetOp.isImm()) {
+      Value = OffsetOp.getImm();
+      return true;
+    }
   }
   if (MI.getOpcode() == Hexagon::A2_addi) {
     Value = MI.getOperand(2).getImm();