[PATCH] D38771: [x86] avoid infinite loop from SoftenFloatOperand (PR34866)

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
Herald added a subscriber: mcrosier.

I don't have any knowledge of fp128 (why do we need -mattr=mmx?) or what's supposed to be happening in these tests, so I assumed we should just run away from this possibility.


https://reviews.llvm.org/D38771

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/fp128-cast.ll


Index: test/CodeGen/X86/fp128-cast.ll
===================================================================
--- test/CodeGen/X86/fp128-cast.ll
+++ test/CodeGen/X86/fp128-cast.ll
@@ -359,6 +359,58 @@
 ; X64:       retq
 }
 
+; This would inf-loop: https://bugs.llvm.org/show_bug.cgi?id=34866
+
+define i1 @PR34866(i128 %x) {
+; X64-LABEL: PR34866:
+; X64:       # BB#0:
+; X64-NEXT:    movaps {{.*}}(%rip), %xmm0
+; X64-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    xorq -{{[0-9]+}}(%rsp), %rsi
+; X64-NEXT:    xorq -{{[0-9]+}}(%rsp), %rdi
+; X64-NEXT:    orq %rsi, %rdi
+; X64-NEXT:    sete %al
+; X64-NEXT:    retq
+;
+; X32-LABEL: PR34866:
+; X32:       # BB#0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    orl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    orl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    orl %ecx, %eax
+; X32-NEXT:    sete %al
+; X32-NEXT:    retl
+  %bc_mmx = bitcast fp128 0xL00000000000000000000000000000000 to i128
+  %cmp = icmp eq i128 %bc_mmx, %x
+  ret i1 %cmp
+}
+
+define i1 @PR34866_commute(i128 %x) {
+; X64-LABEL: PR34866_commute:
+; X64:       # BB#0:
+; X64-NEXT:    movaps {{.*}}(%rip), %xmm0
+; X64-NEXT:    movaps %xmm0, -{{[0-9]+}}(%rsp)
+; X64-NEXT:    xorq -{{[0-9]+}}(%rsp), %rsi
+; X64-NEXT:    xorq -{{[0-9]+}}(%rsp), %rdi
+; X64-NEXT:    orq %rsi, %rdi
+; X64-NEXT:    sete %al
+; X64-NEXT:    retq
+;
+; X32-LABEL: PR34866_commute:
+; X32:       # BB#0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    orl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    orl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    orl %ecx, %eax
+; X32-NEXT:    sete %al
+; X32-NEXT:    retl
+  %bc_mmx = bitcast fp128 0xL00000000000000000000000000000000 to i128
+  %cmp = icmp eq i128 %x, %bc_mmx
+  ret i1 %cmp
+}
+
 declare double @copysign(double, double) #1
 
 attributes #2 = { nounwind readnone }
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -35222,6 +35222,13 @@
   if (!OpVT.isScalarInteger() || OpSize < 128 || isNullConstant(Y))
     return SDValue();
 
+  // Bail out if we know that this is not really just an oversized integer.
+  if ((X.getOpcode() == ISD::BITCAST &&
+       X.getOperand(0).getValueType() == MVT::f128) ||
+      (Y.getOpcode() == ISD::BITCAST &&
+       Y.getOperand(0).getValueType() == MVT::f128))
+    return SDValue();
+
   // TODO: Use PXOR + PTEST for SSE4.1 or later?
   // TODO: Add support for AVX-512.
   EVT VT = SetCC->getValueType(0);


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