[llvm] r315318 - [mips] Duplicate the reciprocal instruction definitions for FP32
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 10 07:41:12 PDT 2017
Author: sdardis
Date: Tue Oct 10 07:41:11 2017
New Revision: 315318
URL: http://llvm.org/viewvc/llvm-project?rev=315318&view=rev
Log:
[mips] Duplicate the reciprocal instruction definitions for FP32
Add instruction definitions for FP32 mode for recip.d and rsqrt.d.
Previously these instructions were only defined when targeting the
full 64-bit FPU model but were not guarded properly.
Reviewers: nitesh.jain, atanasyan
Differential Revision: https://reviews.llvm.org/D38400
Modified:
llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td
llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
llvm/trunk/test/MC/Mips/mips32r2/valid.s
llvm/trunk/test/MC/Mips/mips32r3/valid.s
llvm/trunk/test/MC/Mips/mips32r5/valid.s
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td?rev=315318&r1=315317&r2=315318&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td Tue Oct 10 07:41:11 2017
@@ -169,16 +169,28 @@ let AdditionalPredicates = [InMicroMips]
def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd,
II_RECIP_S>,
ROUND_W_FM_MM<0b0, 0b01001000>;
- def RECIP_D_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd,
- II_RECIP_D>,
- ROUND_W_FM_MM<0b1, 0b01001000>;
+ def RECIP_D32_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd,
+ II_RECIP_D>,
+ ROUND_W_FM_MM<0b1, 0b01001000>, FGR_32 {
+ let BaseOpcode = "RECIP_D32";
+ }
+ let DecoderNamespace = "MicroMipsFP64" in
+ def RECIP_D64_MM : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd,
+ II_RECIP_D>,
+ ROUND_W_FM_MM<0b1, 0b01001000>, FGR_64;
def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd,
II_RECIP_S>,
ROUND_W_FM_MM<0b0, 0b00001000>;
- def RSQRT_D_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd,
+ def RSQRT_D32_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd,
II_RECIP_D>,
- ROUND_W_FM_MM<0b1, 0b00001000>;
- }
+ ROUND_W_FM_MM<0b1, 0b00001000>, FGR_32 {
+ let BaseOpcode = "RSQRT_D32";
+ }
+ let DecoderNamespace = "MicroMipsFP64" in
+ def RSQRT_D64_MM : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd,
+ II_RECIP_D>,
+ ROUND_W_FM_MM<0b1, 0b00001000>, FGR_64;
+ }
let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeFMemMMR2" in {
def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>,
LW_FM_MM<0x2f>, FGR_32 {
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=315318&r1=315317&r2=315318&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Tue Oct 10 07:41:11 2017
@@ -369,12 +369,24 @@ defm CVT_W : ROUND_M<"cvt.w.d", II_CVT
let AdditionalPredicates = [NotInMicroMips] in {
def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>,
ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2;
- def RECIP_D : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, II_RECIP_D>,
- ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2;
+ def RECIP_D32 : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, II_RECIP_D>,
+ ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2, FGR_32 {
+ let BaseOpcode = "RECIP_D32";
+ }
+ let DecoderNamespace = "MipsFP64" in
+ def RECIP_D64 : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd,
+ II_RECIP_D>, ABSS_FM<0b010101, 0x11>,
+ INSN_MIPS4_32R2, FGR_64;
def RSQRT_S : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RSQRT_S>,
ABSS_FM<0b010110, 0x10>, INSN_MIPS4_32R2;
- def RSQRT_D : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, II_RSQRT_D>,
- ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2;
+ def RSQRT_D32 : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, II_RSQRT_D>,
+ ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2, FGR_32 {
+ let BaseOpcode = "RSQRT_D32";
+ }
+ let DecoderNamespace = "MipsFP64" in
+ def RSQRT_D64 : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd,
+ II_RSQRT_D>, ABSS_FM<0b010110, 0x11>,
+ INSN_MIPS4_32R2, FGR_64;
}
let DecoderNamespace = "MipsFP64" in {
let AdditionalPredicates = [NotInMicroMips] in {
Modified: llvm/trunk/test/MC/Mips/mips32r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/valid.s?rev=315318&r1=315317&r2=315318&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r2/valid.s Tue Oct 10 07:41:11 2017
@@ -197,7 +197,7 @@ a:
# CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
- recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
+ recip.d $f14,$f6 # CHECK: recip.d $f14, $f6 # encoding: [0x46,0x20,0x33,0x95]
recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2]
rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
Modified: llvm/trunk/test/MC/Mips/mips32r3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r3/valid.s?rev=315318&r1=315317&r2=315318&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r3/valid.s Tue Oct 10 07:41:11 2017
@@ -197,7 +197,7 @@ a:
# CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
- recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
+ recip.d $f14,$f6 # CHECK: recip.d $f14, $f6 # encoding: [0x46,0x20,0x33,0x95]
recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2]
rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
Modified: llvm/trunk/test/MC/Mips/mips32r5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r5/valid.s?rev=315318&r1=315317&r2=315318&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r5/valid.s Tue Oct 10 07:41:11 2017
@@ -198,7 +198,7 @@ a:
# CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
- recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
+ recip.d $f14,$f6 # CHECK: recip.d $f14, $f6 # encoding: [0x46,0x20,0x33,0x95]
recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2]
rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
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