[PATCH] D38732: [X86][AVX512] Improve lowering of AVX512 test intrinsics

[Uriel Korach via Phabricator via llvm-commits]

uriel.k created this revision.

Added TESTM and TESTNM to the list of instructions that already zeroing unused upper bits and does not need the redundant shift left and shift right instructions afterwards.

Added a pattern for TESTM and TESTNM in iselLowering, so now icmp(neq,and(X,Y), 0) goes folds into TESTM and icmp(eq,and(X,Y), 0) goes folds into TESTNM

This commit is a preparation for lowering the test and testn X86 intrinsics to IR.


https://reviews.llvm.org/D38732

Files:
  lib/Target/X86/X86ISelDAGToDAG.cpp
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/avx512-skx-insert-subvec.ll
  test/CodeGen/X86/avx512bw-vec-test-testn.ll
  test/CodeGen/X86/avx512bwvl-vec-test-testn.ll
  test/CodeGen/X86/avx512f-vec-test-testn.ll
  test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
  test/CodeGen/X86/avx512vl-vec-test-testn.ll
  test/CodeGen/X86/compress_expand.ll
  test/CodeGen/X86/masked_gather_scatter.ll
  test/CodeGen/X86/masked_memop.ll
  test/CodeGen/X86/setcc-lowering.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D38732.118386.patch
Type: text/x-patch
Size: 53214 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20171010/ee072c4e/attachment-0001.bin>