[llvm] r315311 - after fixing the i386 case

[Uriel Korach via llvm-commits]

Author: uriel.k
Date: Tue Oct 10 06:43:09 2017
New Revision: 315311

URL: http://llvm.org/viewvc/llvm-project?rev=315311&view=rev
Log:
after fixing the i386 case

Change-Id: If6fe0b6ec01f111115fb734fe31c0e152dbc165f

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=315311&r1=315310&r2=315311&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Oct 10 06:43:09 2017
@@ -8028,8 +8028,8 @@ static SDValue LowerCONCAT_VECTORSvXi1(S
   // output register, mark it as legal and catch the pattern in instruction
   // selection to avoid emitting extra insturctions (for zeroing upper bits).
   if (SDValue Promoted = isTypePromotionOfi1ZeroUpBits(Op)) {
-    SDValue ZeroC = DAG.getConstant(0, dl, MVT::i64);
-    SDValue AllZeros = DAG.getSplatBuildVector(ResVT, dl, ZeroC);
+    SDValue ZeroC = DAG.getIntPtrConstant(0, dl);
+    SDValue AllZeros = getZeroVector(ResVT, Subtarget, DAG, dl);
     return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, AllZeros, Promoted,
                        ZeroC);
   }