[PATCH] D38689: [X86] Fix a bug with i386 subtarget in LowerCONCAT_VECTORSvXi1 func

[Uriel Korach via Phabricator via llvm-commits]

uriel.k updated this revision to Diff 118326.
uriel.k added a comment.

Changed function to be DAG.getIntPtrConstant(0, dl) instead.

Test case is not possible right now as it crashes only after another patch that will add TESTM to 
the list of instructions that zeroing the upper bits by default (much like PCMPEQ).


https://reviews.llvm.org/D38689

Files:
  lib/Target/X86/X86ISelLowering.cpp


Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -8028,7 +8028,7 @@
   // output register, mark it as legal and catch the pattern in instruction
   // selection to avoid emitting extra insturctions (for zeroing upper bits).
   if (SDValue Promoted = isTypePromotionOfi1ZeroUpBits(Op)) {
-    SDValue ZeroC = DAG.getConstant(0, dl, MVT::i64);
+    SDValue ZeroC =  DAG.getIntPtrConstant(0, dl); 
     SDValue AllZeros = DAG.getSplatBuildVector(ResVT, dl, ZeroC);
     return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, AllZeros, Promoted,
                        ZeroC);


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