[llvm] r315206 - [DAG] combine assertsexts around a trunc
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 9 08:22:21 PDT 2017
Author: spatel
Date: Mon Oct 9 08:22:20 2017
New Revision: 315206
URL: http://llvm.org/viewvc/llvm-project?rev=315206&view=rev
Log:
[DAG] combine assertsexts around a trunc
This was a suggested follow-up to:
D37017 / https://reviews.llvm.org/rL313577
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/not.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll
llvm/trunk/test/CodeGen/X86/select_const.ll
llvm/trunk/test/CodeGen/X86/sext-i1.ll
llvm/trunk/test/CodeGen/X86/split-store.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=315206&r1=315205&r2=315206&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Oct 9 08:22:20 2017
@@ -328,7 +328,7 @@ namespace {
SDValue visitSIGN_EXTEND(SDNode *N);
SDValue visitZERO_EXTEND(SDNode *N);
SDValue visitANY_EXTEND(SDNode *N);
- SDValue visitAssertZext(SDNode *N);
+ SDValue visitAssertExt(SDNode *N);
SDValue visitSIGN_EXTEND_INREG(SDNode *N);
SDValue visitSIGN_EXTEND_VECTOR_INREG(SDNode *N);
SDValue visitZERO_EXTEND_VECTOR_INREG(SDNode *N);
@@ -1553,7 +1553,8 @@ SDValue DAGCombiner::visit(SDNode *N) {
case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
- case ISD::AssertZext: return visitAssertZext(N);
+ case ISD::AssertSext:
+ case ISD::AssertZext: return visitAssertExt(N);
case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N);
case ISD::ZERO_EXTEND_VECTOR_INREG: return visitZERO_EXTEND_VECTOR_INREG(N);
@@ -7978,20 +7979,19 @@ SDValue DAGCombiner::visitANY_EXTEND(SDN
return SDValue();
}
-// TODO: These transforms should work with AssertSext too.
-// Change the function name, comments, opcode references, and caller.
-SDValue DAGCombiner::visitAssertZext(SDNode *N) {
+SDValue DAGCombiner::visitAssertExt(SDNode *N) {
+ unsigned Opcode = N->getOpcode();
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT AssertVT = cast<VTSDNode>(N1)->getVT();
- // fold (assertzext (assertzext x, vt), vt) -> (assertzext x, vt)
- if (N0.getOpcode() == ISD::AssertZext &&
+ // fold (assert?ext (assert?ext x, vt), vt) -> (assert?ext x, vt)
+ if (N0.getOpcode() == Opcode &&
AssertVT == cast<VTSDNode>(N0.getOperand(1))->getVT())
return N0;
if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
- N0.getOperand(0).getOpcode() == ISD::AssertZext) {
+ N0.getOperand(0).getOpcode() == Opcode) {
// We have an assert, truncate, assert sandwich. Make one stronger assert
// by asserting on the smallest asserted type to the larger source type.
// This eliminates the later assert:
@@ -8000,13 +8000,13 @@ SDValue DAGCombiner::visitAssertZext(SDN
SDValue BigA = N0.getOperand(0);
EVT BigA_AssertVT = cast<VTSDNode>(BigA.getOperand(1))->getVT();
assert(BigA_AssertVT.bitsLE(N0.getValueType()) &&
- "Asserting zero/sign-extended bits from a type larger than the "
+ "Asserting zero/sign-extended bits to a type larger than the "
"truncated destination does not provide information");
SDLoc DL(N);
EVT MinAssertVT = AssertVT.bitsLT(BigA_AssertVT) ? AssertVT : BigA_AssertVT;
SDValue MinAssertVTVal = DAG.getValueType(MinAssertVT);
- SDValue NewAssert = DAG.getNode(ISD::AssertZext, DL, BigA.getValueType(),
+ SDValue NewAssert = DAG.getNode(Opcode, DL, BigA.getValueType(),
BigA.getOperand(0), MinAssertVTVal);
return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewAssert);
}
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll?rev=315206&r1=315205&r2=315206&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll Mon Oct 9 08:22:20 2017
@@ -37,10 +37,12 @@ entry:
; GP32: and $2, $4, $5
- ; GP64: and $2, $4, $5
+ ; GP64: and $1, $4, $5
- ; MM: and16 $[[T0:[0-9]+]], $5
- ; MM: move $2, $[[T0]]
+ ; MM32: and16 $[[T0:[0-9]+]], $5
+ ; MM32: move $2, $[[T0]]
+
+ ; MM64: and $1, $4, $5
%r = and i1 %a, %b
ret i1 %r
@@ -52,10 +54,12 @@ entry:
; GP32: and $2, $4, $5
- ; GP64: and $2, $4, $5
+ ; GP64: and $1, $4, $5
+
+ ; MM32: and16 $[[T0:[0-9]+]], $5
+ ; MM32: move $2, $[[T0]]
- ; MM: and16 $[[T0:[0-9]+]], $5
- ; MM: move $2, $[[T0]]
+ ; MM64: and $1, $4, $5
%r = and i8 %a, %b
ret i8 %r
@@ -67,10 +71,12 @@ entry:
; GP32: and $2, $4, $5
- ; GP64: and $2, $4, $5
+ ; GP64: and $1, $4, $5
+
+ ; MM32: and16 $[[T0:[0-9]+]], $5
+ ; MM32 move $2, $[[T0]]
- ; MM: and16 $[[T0:[0-9]+]], $5
- ; MM: move $2, $[[T0]]
+ ; MM64: and $1, $4, $5
%r = and i16 %a, %b
ret i16 %r
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/not.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/not.ll?rev=315206&r1=315205&r2=315206&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/not.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/not.ll Mon Oct 9 08:22:20 2017
@@ -135,7 +135,10 @@ define signext i1 @nor_i1(i1 signext %a,
entry:
; ALL-LABEL: nor_i1:
- ; ALL: nor $2, $5, $4
+ ; GP32: nor $2, $5, $4
+ ; GP64: or $1, $5, $4
+ ; MM32: nor $2, $5, $4
+ ; MM64: or $1, $5, $4
%or = or i1 %b, %a
%r = xor i1 %or, -1
@@ -146,7 +149,10 @@ define signext i8 @nor_i8(i8 signext %a,
entry:
; ALL-LABEL: nor_i8:
- ; ALL: nor $2, $5, $4
+ ; GP32: nor $2, $5, $4
+ ; GP64: or $1, $5, $4
+ ; MM32: nor $2, $5, $4
+ ; MM64: or $1, $5, $4
%or = or i8 %b, %a
%r = xor i8 %or, -1
@@ -157,7 +163,10 @@ define signext i16 @nor_i16(i16 signext
entry:
; ALL-LABEL: nor_i16:
- ; ALL: nor $2, $5, $4
+ ; GP32: nor $2, $5, $4
+ ; GP64: or $1, $5, $4
+ ; MM32: nor $2, $5, $4
+ ; MM64: or $1, $5, $4
%or = or i16 %b, %a
%r = xor i16 %or, -1
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll?rev=315206&r1=315205&r2=315206&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll Mon Oct 9 08:22:20 2017
@@ -24,10 +24,12 @@ entry:
; GP32: or $2, $4, $5
- ; GP64: or $2, $4, $5
+ ; GP64: or $1, $4, $5
- ; MM: or16 $[[T0:[0-9]+]], $5
- ; MM: move $2, $[[T0]]
+ ; MM32: or16 $[[T0:[0-9]+]], $5
+ ; MM32 move $2, $[[T0]]
+
+ ; MM64: or $1, $4, $5
%r = or i1 %a, %b
ret i1 %r
@@ -39,10 +41,12 @@ entry:
; GP32: or $2, $4, $5
- ; GP64: or $2, $4, $5
+ ; GP64: or $1, $4, $5
+
+ ; MM32: or16 $[[T0:[0-9]+]], $5
+ ; MM32 move $2, $[[T0]]
- ; MM: or16 $[[T0:[0-9]+]], $5
- ; MM: move $2, $[[T0]]
+ ; MM64: or $1, $4, $5
%r = or i8 %a, %b
ret i8 %r
@@ -54,10 +58,12 @@ entry:
; GP32: or $2, $4, $5
- ; GP64: or $2, $4, $5
+ ; GP64: or $1, $4, $5
+
+ ; MM32: or16 $[[T0:[0-9]+]], $5
+ ; MM32 move $2, $[[T0]]
- ; MM: or16 $[[T0:[0-9]+]], $5
- ; MM: move $2, $[[T0]]
+ ; MM64: or $1, $4, $5
%r = or i16 %a, %b
ret i16 %r
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll?rev=315206&r1=315205&r2=315206&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll Mon Oct 9 08:22:20 2017
@@ -35,10 +35,12 @@ entry:
; GP32: xor $2, $4, $5
- ; GP64: xor $2, $4, $5
+ ; GP64: xor $1, $4, $5
- ; MM: xor16 $[[T0:[0-9]+]], $5
- ; MM: move $2, $[[T0]]
+ ; MM32: xor16 $[[T0:[0-9]+]], $5
+ ; MM32: move $2, $[[T0]]
+
+ ; MM64: xor $1, $4, $5
%r = xor i1 %a, %b
ret i1 %r
@@ -50,10 +52,12 @@ entry:
; GP32: xor $2, $4, $5
- ; GP64: xor $2, $4, $5
+ ; GP64: xor $1, $4, $5
+
+ ; MM32: xor16 $[[T0:[0-9]+]], $5
+ ; MM32: move $2, $[[T0]]
- ; MM: xor16 $[[T0:[0-9]+]], $5
- ; MM: move $2, $[[T0]]
+ ; MM64: xor $1, $4, $5
%r = xor i8 %a, %b
ret i8 %r
@@ -65,10 +69,12 @@ entry:
; GP32: xor $2, $4, $5
- ; GP64: xor $2, $4, $5
+ ; GP64: xor $1, $4, $5
+
+ ; MM32: xor16 $[[T0:[0-9]+]], $5
+ ; MM32: move $2, $[[T0]]
- ; MM: xor16 $[[T0:[0-9]+]], $5
- ; MM: move $2, $[[T0]]
+ ; MM64: xor $1, $4, $5
%r = xor i16 %a, %b
ret i16 %r
Modified: llvm/trunk/test/CodeGen/X86/select_const.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/select_const.ll?rev=315206&r1=315205&r2=315206&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/select_const.ll (original)
+++ llvm/trunk/test/CodeGen/X86/select_const.ll Mon Oct 9 08:22:20 2017
@@ -62,8 +62,8 @@ define i32 @select_1_or_0_zeroext(i1 zer
define i32 @select_1_or_0_signext(i1 signext %cond) {
; CHECK-LABEL: select_1_or_0_signext:
; CHECK: # BB#0:
-; CHECK-NEXT: andb $1, %dil
-; CHECK-NEXT: movzbl %dil, %eax
+; CHECK-NEXT: andl $1, %edi
+; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
%sel = select i1 %cond, i32 1, i32 0
ret i32 %sel
@@ -95,9 +95,8 @@ define i32 @select_0_or_neg1_zeroext(i1
define i32 @select_0_or_neg1_signext(i1 signext %cond) {
; CHECK-LABEL: select_0_or_neg1_signext:
; CHECK: # BB#0:
-; CHECK-NEXT: andb $1, %dil
-; CHECK-NEXT: movzbl %dil, %eax
-; CHECK-NEXT: decl %eax
+; CHECK-NEXT: notl %edi
+; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
%sel = select i1 %cond, i32 0, i32 -1
ret i32 %sel
@@ -129,7 +128,7 @@ define i32 @select_neg1_or_0_zeroext(i1
define i32 @select_neg1_or_0_signext(i1 signext %cond) {
; CHECK-LABEL: select_neg1_or_0_signext:
; CHECK: # BB#0:
-; CHECK-NEXT: movsbl %dil, %eax
+; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
%sel = select i1 %cond, i32 -1, i32 0
ret i32 %sel
@@ -161,9 +160,8 @@ define i32 @select_Cplus1_C_zeroext(i1 z
define i32 @select_Cplus1_C_signext(i1 signext %cond) {
; CHECK-LABEL: select_Cplus1_C_signext:
; CHECK: # BB#0:
-; CHECK-NEXT: andb $1, %dil
-; CHECK-NEXT: movzbl %dil, %eax
-; CHECK-NEXT: addl $41, %eax
+; CHECK-NEXT: movl $41, %eax
+; CHECK-NEXT: subl %edi, %eax
; CHECK-NEXT: retq
%sel = select i1 %cond, i32 42, i32 41
ret i32 %sel
@@ -195,10 +193,9 @@ define i32 @select_C_Cplus1_zeroext(i1 z
define i32 @select_C_Cplus1_signext(i1 signext %cond) {
; CHECK-LABEL: select_C_Cplus1_signext:
; CHECK: # BB#0:
-; CHECK-NEXT: andb $1, %dil
-; CHECK-NEXT: movzbl %dil, %ecx
+; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: movl $42, %eax
-; CHECK-NEXT: subl %ecx, %eax
+; CHECK-NEXT: subl %edi, %eax
; CHECK-NEXT: retq
%sel = select i1 %cond, i32 41, i32 42
ret i32 %sel
Modified: llvm/trunk/test/CodeGen/X86/sext-i1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sext-i1.ll?rev=315206&r1=315205&r2=315206&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sext-i1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sext-i1.ll Mon Oct 9 08:22:20 2017
@@ -165,9 +165,8 @@ define i32 @select_0_or_1s_signext(i1 si
;
; X64-LABEL: select_0_or_1s_signext:
; X64: # BB#0:
-; X64-NEXT: andb $1, %dil
-; X64-NEXT: movzbl %dil, %eax
-; X64-NEXT: decl %eax
+; X64-NEXT: notl %edi
+; X64-NEXT: movl %edi, %eax
; X64-NEXT: retq
%not = xor i1 %cond, 1
%sext = sext i1 %not to i32
Modified: llvm/trunk/test/CodeGen/X86/split-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/split-store.ll?rev=315206&r1=315205&r2=315206&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/split-store.ll (original)
+++ llvm/trunk/test/CodeGen/X86/split-store.ll Mon Oct 9 08:22:20 2017
@@ -197,13 +197,11 @@ define void @int12_int12_pair(i12 signex
define void @int7_int7_pair(i7 signext %tmp1, i7 signext %tmp2, i14* %ref.tmp) {
; CHECK-LABEL: int7_int7_pair:
; CHECK: # BB#0:
-; CHECK-NEXT: movzbl %sil, %eax
-; CHECK-NEXT: shll $7, %eax
-; CHECK-NEXT: andb $127, %dil
-; CHECK-NEXT: movzbl %dil, %ecx
-; CHECK-NEXT: orl %eax, %ecx
-; CHECK-NEXT: andl $16383, %ecx # imm = 0x3FFF
-; CHECK-NEXT: movw %cx, (%rdx)
+; CHECK-NEXT: shll $7, %esi
+; CHECK-NEXT: andl $127, %edi
+; CHECK-NEXT: orl %esi, %edi
+; CHECK-NEXT: andl $16383, %edi # imm = 0x3FFF
+; CHECK-NEXT: movw %di, (%rdx)
; CHECK-NEXT: retq
%t1 = zext i7 %tmp2 to i14
%t2 = shl nuw i14 %t1, 7
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