[llvm] r315160 - [X86] Remove ISD::INSERT_SUBVECTOR handling from combineBitcastForMaskedOp. Add isel patterns to make up for it.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Oct 7 18:33:40 PDT 2017
Author: ctopper
Date: Sat Oct 7 18:33:40 2017
New Revision: 315160
URL: http://llvm.org/viewvc/llvm-project?rev=315160&view=rev
Log:
[X86] Remove ISD::INSERT_SUBVECTOR handling from combineBitcastForMaskedOp. Add isel patterns to make up for it.
This will allow for some flexibility in canonicalizing bitcasts around insert_subvector.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=315160&r1=315159&r2=315160&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Oct 7 18:33:40 2017
@@ -30465,29 +30465,6 @@ static bool combineBitcastForMaskedOp(SD
return BitcastAndCombineShuffle(Opcode, Op.getOperand(0), Op.getOperand(1),
Op.getOperand(2));
}
- case ISD::INSERT_SUBVECTOR: {
- unsigned EltSize = EltVT.getSizeInBits();
- if (EltSize != 32 && EltSize != 64)
- return false;
- MVT OpEltVT = Op.getSimpleValueType().getVectorElementType();
- // Only change element size, not type.
- if (EltVT.isInteger() != OpEltVT.isInteger())
- return false;
- uint64_t Imm = Op.getConstantOperandVal(2);
- Imm = (Imm * OpEltVT.getSizeInBits()) / EltSize;
- SDValue Op0 = DAG.getBitcast(VT, Op.getOperand(0));
- DCI.AddToWorklist(Op0.getNode());
- // Op1 needs to be bitcasted to a smaller vector with the same element type.
- SDValue Op1 = Op.getOperand(1);
- MVT Op1VT = MVT::getVectorVT(EltVT,
- Op1.getSimpleValueType().getSizeInBits() / EltSize);
- Op1 = DAG.getBitcast(Op1VT, Op1);
- DCI.AddToWorklist(Op1.getNode());
- DCI.CombineTo(OrigOp.getNode(),
- DAG.getNode(Opcode, DL, VT, Op0, Op1,
- DAG.getIntPtrConstant(Imm, DL)));
- return true;
- }
case X86ISD::SUBV_BROADCAST: {
unsigned EltSize = EltVT.getSizeInBits();
if (EltSize != 32 && EltSize != 64)
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=315160&r1=315159&r2=315160&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Sat Oct 7 18:33:40 2017
@@ -615,6 +615,139 @@ defm : vinsert_for_size_lowering<"VINSER
defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v32i8x_info, v64i8_info,
vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
+
+multiclass vinsert_for_mask_cast<string InstrStr, X86VectorVTInfo From,
+ X86VectorVTInfo To, X86VectorVTInfo Cast,
+ PatFrag vinsert_insert,
+ SDNodeXForm INSERT_get_vinsert_imm,
+ list<Predicate> p> {
+let Predicates = p in {
+ def : Pat<(Cast.VT
+ (vselect Cast.KRCWM:$mask,
+ (bitconvert
+ (vinsert_insert:$ins (To.VT To.RC:$src1),
+ (From.VT From.RC:$src2),
+ (iPTR imm))),
+ Cast.RC:$src0)),
+ (!cast<Instruction>(InstrStr#"rrk")
+ Cast.RC:$src0, Cast.KRCWM:$mask, To.RC:$src1, From.RC:$src2,
+ (INSERT_get_vinsert_imm To.RC:$ins))>;
+ def : Pat<(Cast.VT
+ (vselect Cast.KRCWM:$mask,
+ (bitconvert
+ (vinsert_insert:$ins (To.VT To.RC:$src1),
+ (From.VT
+ (bitconvert
+ (From.LdFrag addr:$src2))),
+ (iPTR imm))),
+ Cast.RC:$src0)),
+ (!cast<Instruction>(InstrStr#"rmk")
+ Cast.RC:$src0, Cast.KRCWM:$mask, To.RC:$src1, addr:$src2,
+ (INSERT_get_vinsert_imm To.RC:$ins))>;
+
+ def : Pat<(Cast.VT
+ (vselect Cast.KRCWM:$mask,
+ (bitconvert
+ (vinsert_insert:$ins (To.VT To.RC:$src1),
+ (From.VT From.RC:$src2),
+ (iPTR imm))),
+ Cast.ImmAllZerosV)),
+ (!cast<Instruction>(InstrStr#"rrkz")
+ Cast.KRCWM:$mask, To.RC:$src1, From.RC:$src2,
+ (INSERT_get_vinsert_imm To.RC:$ins))>;
+ def : Pat<(Cast.VT
+ (vselect Cast.KRCWM:$mask,
+ (bitconvert
+ (vinsert_insert:$ins (To.VT To.RC:$src1),
+ (From.VT
+ (bitconvert
+ (From.LdFrag addr:$src2))),
+ (iPTR imm))),
+ Cast.ImmAllZerosV)),
+ (!cast<Instruction>(InstrStr#"rmkz")
+ Cast.KRCWM:$mask, To.RC:$src1, addr:$src2,
+ (INSERT_get_vinsert_imm To.RC:$ins))>;
+}
+}
+
+defm : vinsert_for_mask_cast<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info,
+ v8f32x_info, vinsert128_insert,
+ INSERT_get_vinsert128_imm, [HasVLX]>;
+defm : vinsert_for_mask_cast<"VINSERTF64x2Z256", v4f32x_info, v8f32x_info,
+ v4f64x_info, vinsert128_insert,
+ INSERT_get_vinsert128_imm, [HasDQI, HasVLX]>;
+
+defm : vinsert_for_mask_cast<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info,
+ v8i32x_info, vinsert128_insert,
+ INSERT_get_vinsert128_imm, [HasVLX]>;
+defm : vinsert_for_mask_cast<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info,
+ v8i32x_info, vinsert128_insert,
+ INSERT_get_vinsert128_imm, [HasVLX]>;
+defm : vinsert_for_mask_cast<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info,
+ v8i32x_info, vinsert128_insert,
+ INSERT_get_vinsert128_imm, [HasVLX]>;
+defm : vinsert_for_mask_cast<"VINSERTF64x2Z256", v4i32x_info, v8i32x_info,
+ v4i64x_info, vinsert128_insert,
+ INSERT_get_vinsert128_imm, [HasDQI, HasVLX]>;
+defm : vinsert_for_mask_cast<"VINSERTF64x2Z256", v8i16x_info, v16i16x_info,
+ v4i64x_info, vinsert128_insert,
+ INSERT_get_vinsert128_imm, [HasDQI, HasVLX]>;
+defm : vinsert_for_mask_cast<"VINSERTF64x2Z256", v16i8x_info, v32i8x_info,
+ v4i64x_info, vinsert128_insert,
+ INSERT_get_vinsert128_imm, [HasDQI, HasVLX]>;
+
+defm : vinsert_for_mask_cast<"VINSERTF32x4Z", v2f64x_info, v8f64_info,
+ v16f32_info, vinsert128_insert,
+ INSERT_get_vinsert128_imm, [HasAVX512]>;
+defm : vinsert_for_mask_cast<"VINSERTF64x2Z", v4f32x_info, v16f32_info,
+ v8f64_info, vinsert128_insert,
+ INSERT_get_vinsert128_imm, [HasDQI]>;
+
+defm : vinsert_for_mask_cast<"VINSERTI32x4Z", v2i64x_info, v8i64_info,
+ v16i32_info, vinsert128_insert,
+ INSERT_get_vinsert128_imm, [HasAVX512]>;
+defm : vinsert_for_mask_cast<"VINSERTI32x4Z", v8i16x_info, v32i16_info,
+ v16i32_info, vinsert128_insert,
+ INSERT_get_vinsert128_imm, [HasAVX512]>;
+defm : vinsert_for_mask_cast<"VINSERTI32x4Z", v16i8x_info, v64i8_info,
+ v16i32_info, vinsert128_insert,
+ INSERT_get_vinsert128_imm, [HasAVX512]>;
+defm : vinsert_for_mask_cast<"VINSERTI64x2Z", v4i32x_info, v16i32_info,
+ v8i64_info, vinsert128_insert,
+ INSERT_get_vinsert128_imm, [HasDQI]>;
+defm : vinsert_for_mask_cast<"VINSERTI64x2Z", v8i16x_info, v32i16_info,
+ v8i64_info, vinsert128_insert,
+ INSERT_get_vinsert128_imm, [HasDQI]>;
+defm : vinsert_for_mask_cast<"VINSERTI64x2Z", v16i8x_info, v64i8_info,
+ v8i64_info, vinsert128_insert,
+ INSERT_get_vinsert128_imm, [HasDQI]>;
+
+defm : vinsert_for_mask_cast<"VINSERTF32x8Z", v4f64x_info, v8f64_info,
+ v16f32_info, vinsert256_insert,
+ INSERT_get_vinsert256_imm, [HasDQI]>;
+defm : vinsert_for_mask_cast<"VINSERTF64x4Z", v8f32x_info, v16f32_info,
+ v8f64_info, vinsert256_insert,
+ INSERT_get_vinsert256_imm, [HasAVX512]>;
+
+defm : vinsert_for_mask_cast<"VINSERTI32x8Z", v4i64x_info, v8i64_info,
+ v16i32_info, vinsert256_insert,
+ INSERT_get_vinsert256_imm, [HasDQI]>;
+defm : vinsert_for_mask_cast<"VINSERTI32x8Z", v16i16x_info, v32i16_info,
+ v16i32_info, vinsert256_insert,
+ INSERT_get_vinsert256_imm, [HasDQI]>;
+defm : vinsert_for_mask_cast<"VINSERTI32x8Z", v32i8x_info, v64i8_info,
+ v16i32_info, vinsert256_insert,
+ INSERT_get_vinsert256_imm, [HasDQI]>;
+defm : vinsert_for_mask_cast<"VINSERTI64x4Z", v8i32x_info, v16i32_info,
+ v8i64_info, vinsert256_insert,
+ INSERT_get_vinsert256_imm, [HasAVX512]>;
+defm : vinsert_for_mask_cast<"VINSERTI64x4Z", v16i16x_info, v32i16_info,
+ v8i64_info, vinsert256_insert,
+ INSERT_get_vinsert256_imm, [HasAVX512]>;
+defm : vinsert_for_mask_cast<"VINSERTI64x4Z", v32i8x_info, v64i8_info,
+ v8i64_info, vinsert256_insert,
+ INSERT_get_vinsert256_imm, [HasAVX512]>;
+
// vinsertps - insert f32 to XMM
let ExeDomain = SSEPackedSingle in {
def VINSERTPSZrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
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