[llvm] r314976 - [mips] Place certain 64 bit FPU instructions in their own decoder namespace
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 5 03:27:37 PDT 2017
Author: sdardis
Date: Thu Oct 5 03:27:37 2017
New Revision: 314976
URL: http://llvm.org/viewvc/llvm-project?rev=314976&view=rev
Log:
[mips] Place certain 64 bit FPU instructions in their own decoder namespace
Previously, instructions that were defined to use the FGR64 register class
were associated with the Mips64 table which was incorrect.
Reviewers: nitesh.jain, atanasyan
Differential Revision: https://reviews.llvm.org/D38454
Modified:
llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsCondMov.td
llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
Modified: llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=314976&r1=314975&r2=314976&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Thu Oct 5 03:27:37 2017
@@ -1283,9 +1283,9 @@ DecodeStatus MipsDisassembler::getInstru
return Result;
}
- if (hasMips32r6() && isFP64()) {
- DEBUG(dbgs() << "Trying MicroMips32r6FP64 table (32-bit opcodes):\n");
- Result = decodeInstruction(DecoderTableMicroMips32r6FP6432, Instr, Insn,
+ if (isFP64()) {
+ DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n");
+ Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn,
Address, this, STI);
if (Result != MCDisassembler::Fail) {
Size = 4;
@@ -1366,6 +1366,14 @@ DecodeStatus MipsDisassembler::getInstru
Address, this, STI);
if (Result != MCDisassembler::Fail)
return Result;
+ }
+
+ if (isFP64()) {
+ DEBUG(dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n");
+ Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn,
+ Address, this, STI);
+ if (Result != MCDisassembler::Fail)
+ return Result;
}
DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=314976&r1=314975&r2=314976&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Thu Oct 5 03:27:37 2017
@@ -1485,7 +1485,7 @@ def MTC1_MMR6 : StdMMR6Rel, MTC1_MMR6_DE
def MTC2_MMR6 : StdMMR6Rel, MTC2_MMR6_ENC, MTC2_MMR6_DESC, ISA_MICROMIPS32R6;
def MTHC0_MMR6 : R6MMR6Rel, MTHC0_MMR6_ENC, MTHC0_MMR6_DESC, ISA_MICROMIPS32R6;
def MTHC1_D32_MMR6 : StdMMR6Rel, MTHC1_D32_MMR6_DESC, MTHC1_MMR6_ENC, ISA_MICROMIPS32R6;
-let DecoderNamespace = "MicroMips32r6FP64" in {
+let DecoderNamespace = "MicroMipsFP64" in {
def MTHC1_D64_MMR6 : R6MMR6Rel, MTHC1_D64_MMR6_DESC, MTHC1_MMR6_ENC,
ISA_MICROMIPS32R6;
}
@@ -1496,7 +1496,7 @@ def MFC2_MMR6 : StdMMR6Rel, MFC2_MMR6_EN
def MFHC0_MMR6 : R6MMR6Rel, MFHC0_MMR6_ENC, MFHC0_MMR6_DESC, ISA_MICROMIPS32R6;
def MFHC1_D32_MMR6 : StdMMR6Rel, MFHC1_D32_MMR6_DESC, MFHC1_MMR6_ENC,
ISA_MICROMIPS32R6;
-let DecoderNamespace = "MicroMips32r6FP64" in {
+let DecoderNamespace = "MicroMipsFP64" in {
def MFHC1_D64_MMR6 : StdMMR6Rel, MFHC1_D64_MMR6_DESC, MFHC1_MMR6_ENC,
ISA_MICROMIPS32R6;
}
@@ -1729,7 +1729,7 @@ def BC2EQZC_MMR6 : R6MMR6Rel, MipsR6Inst
ISA_MICROMIPS32R6;
def BC2NEZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2NEZC_MMR6_ENC, BC2NEZC_MMR6_DESC,
ISA_MICROMIPS32R6;
-let DecoderNamespace = "MicroMips32r6FP64" in {
+let DecoderNamespace = "MicroMipsFP64" in {
def LDC1_D64_MMR6 : StdMMR6Rel, LDC1_D64_MMR6_DESC, LDC1_MMR6_ENC,
ISA_MICROMIPS32R6 {
let BaseOpcode = "LDC164";
Modified: llvm/trunk/lib/Target/Mips/MipsCondMov.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCondMov.td?rev=314976&r1=314975&r2=314976&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsCondMov.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsCondMov.td Thu Oct 5 03:27:37 2017
@@ -149,7 +149,7 @@ def MOVN_I_D32 : MMRel, CMov_I_F_FT<"mov
II_MOVN_D>, CMov_I_F_FM<19, 17>,
INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
-let DecoderNamespace = "Mips64" in {
+let DecoderNamespace = "MipsFP64" in {
def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>,
CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>,
@@ -188,7 +188,7 @@ def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.
MipsCMovFP_F>, CMov_F_F_FM<17, 0>,
INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
-let DecoderNamespace = "Mips64" in {
+let DecoderNamespace = "MipsFP64" in {
def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>,
CMov_F_F_FM<17, 1>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>,
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=314976&r1=314975&r2=314976&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Thu Oct 5 03:27:37 2017
@@ -119,7 +119,7 @@ multiclass ADDS_M<string opstr, InstrIti
SDPatternOperator OpNode = null_frag> {
def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32;
def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
- string DecoderNamespace = "Mips64";
+ string DecoderNamespace = "MipsFP64";
}
}
@@ -135,14 +135,14 @@ multiclass ABSS_M<string opstr, InstrIti
def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
FGR_32;
def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 {
- string DecoderNamespace = "Mips64";
+ string DecoderNamespace = "MipsFP64";
}
}
multiclass ROUND_M<string opstr, InstrItinClass Itin> {
def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, FGR_32;
def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, FGR_64 {
- let DecoderNamespace = "Mips64";
+ let DecoderNamespace = "MipsFP64";
}
}
@@ -342,7 +342,7 @@ let AdditionalPredicates = [NotInMicroMi
defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6;
defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
FGR_32;
-let DecoderNamespace = "Mips64" in
+let DecoderNamespace = "MipsFP64" in
defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
FGR_64;
}
@@ -376,7 +376,7 @@ let AdditionalPredicates = [NotInMicroMi
def RSQRT_D : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, II_RSQRT_D>,
ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2;
}
-let DecoderNamespace = "Mips64" in {
+let DecoderNamespace = "MipsFP64" in {
let AdditionalPredicates = [NotInMicroMips] in {
def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
ABSS_FM<0x8, 16>, FGR_64;
@@ -413,7 +413,7 @@ def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w"
def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x21, 16>, FGR_32;
-let DecoderNamespace = "Mips64" in {
+let DecoderNamespace = "MipsFP64" in {
def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x20, 17>, FGR_64;
let AdditionalPredicates = [NotInMicroMips] in{
@@ -461,13 +461,13 @@ def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32O
bitconvert>, MFC1_FM<0>;
def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>,
FGR_64 {
- let DecoderNamespace = "Mips64";
+ let DecoderNamespace = "MipsFP64";
}
def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
bitconvert>, MFC1_FM<4>;
def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>,
FGR_64 {
- let DecoderNamespace = "Mips64";
+ let DecoderNamespace = "MipsFP64";
}
let AdditionalPredicates = [NotInMicroMips] in {
@@ -475,7 +475,7 @@ let AdditionalPredicates = [NotInMicroMi
MFC1_FM<3>, ISA_MIPS32R2, FGR_32;
def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
MFC1_FM<3>, ISA_MIPS32R2, FGR_64 {
- let DecoderNamespace = "Mips64";
+ let DecoderNamespace = "MipsFP64";
}
}
let AdditionalPredicates = [NotInMicroMips] in {
@@ -483,7 +483,7 @@ let AdditionalPredicates = [NotInMicroMi
MFC1_FM<7>, ISA_MIPS32R2, FGR_32;
def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
MFC1_FM<7>, ISA_MIPS32R2, FGR_64 {
- let DecoderNamespace = "Mips64";
+ let DecoderNamespace = "MipsFP64";
}
}
let AdditionalPredicates = [NotInMicroMips] in {
@@ -499,7 +499,7 @@ def FMOV_D32 : MMRel, ABSS_FT<"mov.d", A
ABSS_FM<0x6, 17>, FGR_32;
def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>,
ABSS_FM<0x6, 17>, FGR_64 {
- let DecoderNamespace = "Mips64";
+ let DecoderNamespace = "MipsFP64";
}
/// Floating Point Memory Instructions
@@ -510,7 +510,7 @@ let AdditionalPredicates = [NotInMicroMi
LW_FM<0x39>;
}
-let DecoderNamespace = "Mips64", AdditionalPredicates = [NotInMicroMips] in {
+let DecoderNamespace = "MipsFP64", AdditionalPredicates = [NotInMicroMips] in {
def LDC164 : StdMMR6Rel, LW_FT<"ldc1", FGR64Opnd, mem_simm16, II_LDC1, load>,
LW_FM<0x35>, ISA_MIPS2, FGR_64 {
let BaseOpcode = "LDC164";
@@ -545,7 +545,7 @@ let AdditionalPredicates = [NotInMicroMi
INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
}
-let DecoderNamespace="Mips64" in {
+let DecoderNamespace="MipsFP64" in {
def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
@@ -553,6 +553,7 @@ let DecoderNamespace="Mips64" in {
}
// Load/store doubleword indexed unaligned.
+// FIXME: This instruction should not be defined for FGR_32.
let AdditionalPredicates = [IsNotNaCl] in {
def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
@@ -560,7 +561,7 @@ let AdditionalPredicates = [IsNotNaCl] i
INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
}
-let DecoderNamespace="Mips64" in {
+let DecoderNamespace="MipsFP64" in {
def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
@@ -605,7 +606,7 @@ let AdditionalPredicates = [NoNaNsFPMath
MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
}
-let DecoderNamespace = "Mips64" in {
+let DecoderNamespace = "MipsFP64" in {
def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4;
def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
@@ -613,7 +614,7 @@ let DecoderNamespace = "Mips64" in {
}
let AdditionalPredicates = [NoNaNsFPMath, HasMadd4],
- DecoderNamespace = "Mips64" in {
+ DecoderNamespace = "MipsFP64" in {
def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>,
@@ -655,7 +656,7 @@ let AdditionalPredicates = [NotInMicroMi
bits<3> fcc = 0;
}
}
-let DecoderNamespace = "Mips64" in
+let DecoderNamespace = "MipsFP64" in
def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
ISA_MIPS1_NOT_32R6_64R6, FGR_64 {
// FIXME: This is a required to work around the fact that thiese instructions
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt?rev=314976&r1=314975&r2=314976&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt Thu Oct 5 03:27:37 2017
@@ -1,4 +1,5 @@
# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r2 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -mattr=+fp64 | FileCheck %s
# Try a mips64* triple to confirm that mips* vs mips64* triples no longer have
# an effect on the disassembler behaviour.
# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mcpu=mips32r2 | FileCheck %s
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt?rev=314976&r1=314975&r2=314976&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt Thu Oct 5 03:27:37 2017
@@ -1,4 +1,5 @@
# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+fp64 | FileCheck %s
# Try a mips64* triple to confirm that mips* vs mips64* triples no longer have
# an effect on the disassembler behaviour.
# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips32r2 | FileCheck %s
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt?rev=314976&r1=314975&r2=314976&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt Thu Oct 5 03:27:37 2017
@@ -1,4 +1,5 @@
# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r3 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r3 -mattr=+fp64 | FileCheck %s
0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
0x20 0x48 0xc7 0x00 # CHECK: add $9, $6, $7
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt?rev=314976&r1=314975&r2=314976&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt Thu Oct 5 03:27:37 2017
@@ -1,4 +1,5 @@
# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r3 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r3 -mattr=+fp64 | FileCheck %s
0x00 0x00 0x00 0x00 # CHECK: nop
0x00 0x00 0x00 0x09 # CHECK: jr $zero
0x00 0x00 0x00 0x0c # CHECK: syscall
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt?rev=314976&r1=314975&r2=314976&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt Thu Oct 5 03:27:37 2017
@@ -1,4 +1,5 @@
# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r5 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r5 -mattr=+fp64 | FileCheck %s
0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
0x20 0x48 0xc7 0x00 # CHECK: add $9, $6, $7
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt?rev=314976&r1=314975&r2=314976&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt Thu Oct 5 03:27:37 2017
@@ -1,4 +1,5 @@
# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r5 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r5 -mattr=+fp64 | FileCheck %s
0x00 0x00 0x00 0x00 # CHECK: nop
0x00 0x00 0x00 0x09 # CHECK: jr $zero
0x00 0x00 0x00 0x0c # CHECK: syscall
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