[PATCH] D38560: [PowerPC] Add missing record form instructions to the P9 Scheduling Model

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp created this revision.

Some record form instructions were missing from the https://reviews.llvm.org/P9 Scheduling model. Got compilation errors when we tried to compile anything that used those instructions. 
Those instructions have been added and the model has been marked as complete again.


https://reviews.llvm.org/D38560

Files:
  lib/Target/PowerPC/P9InstrResources.td
  lib/Target/PowerPC/PPCScheduleP9.td


Index: lib/Target/PowerPC/PPCScheduleP9.td
===================================================================
--- lib/Target/PowerPC/PPCScheduleP9.td
+++ lib/Target/PowerPC/PPCScheduleP9.td
@@ -22,7 +22,7 @@
   // Try to make sure we have at least 10 dispatch groups in a loop.
   let LoopMicroOpBufferSize = 60;
 
-  let CompleteModel = 0;
+  let CompleteModel = 1;
 
   let UnsupportedFeatures = [HasQPX];
 
@@ -301,6 +301,9 @@
   def P9_IntDivAndALUOp_42C_8 : WriteSequence<[P9_DIV_40C_8, P9_ALU_2C]>;
   def P9_StoreAndALUOp_4C : WriteSequence<[P9_LS_1C, P9_ALU_3C]>;
   def P9_ALUOpAndALUOp_4C : WriteSequence<[P9_ALU_2C, P9_ALU_2C]>;
+  def P9_DPOpAndALUOp_9C : WriteSequence<[P9_DP_7C, P9_ALU_2C]>;
+  def P9_DPOpAndALUOp_24C_5 : WriteSequence<[P9_DP_22C_5, P9_ALU_2C]>;
+  def P9_DPOpAndALUOp_35C_8 : WriteSequence<[P9_DP_33C_8, P9_ALU_2C]>;
 
   // ***************** Defining Itinerary Class Resources *****************
 
Index: lib/Target/PowerPC/P9InstrResources.td
===================================================================
--- lib/Target/PowerPC/P9InstrResources.td
+++ lib/Target/PowerPC/P9InstrResources.td
@@ -495,6 +495,18 @@
     XSNMSUBMSP
 )>;
 
+// 7 cycle Restricted DP operation and one 2 cycle ALU operation.
+//  The DP is restricted so we need a full 5 dispatches.
+def : InstRW<[P9_DPOpAndALUOp_9C, IP_EXEC_1C, IP_EXEC_1C,
+              DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
+      (instrs
+    FMULo,
+    FMADDo,
+    FMSUBo,
+    FNMADDo,
+    FNMSUBo
+)>;
+
 // 7 cycle DP operation. One DP unit, one EXEC pipeline and two dispatch units.
 def : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_1C, DISP_1C],
       (instrs
@@ -823,6 +835,8 @@
 def : InstRW<[P9_IntDivAndALUOp_26C_8, IP_EXECE_1C, IP_EXECO_1C, IP_EXEC_1C,
               DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
       (instrs
+    DIVDo,
+    DIVDUo,
     DIVWEo,
     DIVWEUo
 )>;
@@ -872,6 +886,13 @@
     FDIV
 )>;
 
+// 33 Cycle DP Instruction Restricted and Cracked with 2 Cycle ALU.
+def : InstRW<[P9_DPOpAndALUOp_35C_8, IP_EXEC_1C, IP_EXEC_1C,
+              DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
+      (instrs
+    FDIVo
+)>;
+
 // 33 Cycle DP Instruction. Takes one slice and 2 dispatches.
 def : InstRW<[P9_DP_33C_8, IP_EXEC_1C, DISP_1C, DISP_1C],
       (instrs
@@ -884,6 +905,13 @@
     FDIVS
 )>;
 
+// 22 Cycle DP Instruction Restricted and Cracked with 2 Cycle ALU.
+def : InstRW<[P9_DPOpAndALUOp_24C_5, IP_EXEC_1C, IP_EXEC_1C,
+              DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
+      (instrs
+    FDIVSo
+)>;
+
 // 22 Cycle DP Instruction. Takes one slice and 2 dispatches.
 def : InstRW<[P9_DP_22C_5, IP_EXEC_1C, DISP_1C, DISP_1C],
       (instrs


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