[PATCH] D38449: [X86] Redefine MOVSS/MOVSD instructions to take VR128 regclass as input instead of FR32/FR64

[Phabricator via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL314914: [X86] Redefine MOVSS/MOVSD instructions to take VR128 regclass as input instead… (authored by ctopper).

Changed prior to commit:
  https://reviews.llvm.org/D38449?vs=117455&id=117693#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D38449

Files:
  llvm/trunk/lib/Target/X86/X86InstrAVX512.td
  llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
  llvm/trunk/lib/Target/X86/X86InstrSSE.td
  llvm/trunk/test/CodeGen/X86/buildvec-insertvec.ll
  llvm/trunk/test/CodeGen/X86/lower-vec-shift.ll
  llvm/trunk/test/CodeGen/X86/psubus.ll
  llvm/trunk/test/CodeGen/X86/vector-blend.ll
  llvm/trunk/test/CodeGen/X86/vector-compare-results.ll
  llvm/trunk/test/CodeGen/X86/vector-rotate-128.ll
  llvm/trunk/test/CodeGen/X86/vector-shift-ashr-128.ll
  llvm/trunk/test/CodeGen/X86/vector-shift-lshr-128.ll
  llvm/trunk/test/CodeGen/X86/vector-shift-shl-128.ll
  llvm/trunk/test/CodeGen/X86/vector-trunc-math.ll
  llvm/trunk/test/CodeGen/X86/vector-trunc.ll
  llvm/trunk/test/CodeGen/X86/vshift-4.ll
  llvm/trunk/test/CodeGen/X86/x86-shifts.ll

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