[llvm] r314896 - [AVR] Elaborate LDWRdPtr into `ld r, X++; ld r+1, X`
Dylan McKay via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 4 03:33:36 PDT 2017
Author: dylanmckay
Date: Wed Oct 4 03:33:36 2017
New Revision: 314896
URL: http://llvm.org/viewvc/llvm-project?rev=314896&view=rev
Log:
[AVR] Elaborate LDWRdPtr into `ld r, X++; ld r+1, X`
Patch by Gergo Erdi.
Modified:
llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp
llvm/trunk/lib/Target/AVR/AVRInstrInfo.td
llvm/trunk/test/CodeGen/AVR/atomics/load16.ll
llvm/trunk/test/CodeGen/AVR/load.ll
llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
Modified: llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp?rev=314896&r1=314895&r2=314896&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp Wed Oct 4 03:33:36 2017
@@ -583,8 +583,8 @@ bool AVRExpandPseudo::expand<AVR::LDWRdP
unsigned TmpReg = 0; // 0 for no temporary register
unsigned SrcReg = MI.getOperand(1).getReg();
bool SrcIsKill = MI.getOperand(1).isKill();
- OpLo = AVR::LDRdPtr;
- OpHi = AVR::LDDRdPtrQ;
+ OpLo = AVR::LDRdPtrPi;
+ OpHi = AVR::LDRdPtr;
TRI->splitReg(DstReg, DstLoReg, DstHiReg);
// Use a temporary register if src and dst registers are the same.
@@ -597,6 +597,7 @@ bool AVRExpandPseudo::expand<AVR::LDWRdP
// Load low byte.
auto MIBLO = buildMI(MBB, MBBI, OpLo)
.addReg(CurDstLoReg, RegState::Define)
+ .addReg(SrcReg, RegState::Define)
.addReg(SrcReg);
// Push low byte onto stack if necessary.
@@ -606,8 +607,7 @@ bool AVRExpandPseudo::expand<AVR::LDWRdP
// Load high byte.
auto MIBHI = buildMI(MBB, MBBI, OpHi)
.addReg(CurDstHiReg, RegState::Define)
- .addReg(SrcReg, getKillRegState(SrcIsKill))
- .addImm(1);
+ .addReg(SrcReg, getKillRegState(SrcIsKill));
if (TmpReg) {
// Move the high byte into the final destination.
Modified: llvm/trunk/lib/Target/AVR/AVRInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRInstrInfo.td?rev=314896&r1=314895&r2=314896&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AVR/AVRInstrInfo.td Wed Oct 4 03:33:36 2017
@@ -1152,10 +1152,10 @@ isReMaterializable = 1 in
//
// Expands to:
// ld Rd, P+
- // ld Rd+1, P+
+ // ld Rd+1, P
let Constraints = "@earlyclobber $reg" in
def LDWRdPtr : Pseudo<(outs DREGS:$reg),
- (ins PTRDISPREGS:$ptrreg),
+ (ins PTRREGS:$ptrreg),
"ldw\t$reg, $ptrreg",
[(set i16:$reg, (load i16:$ptrreg))]>,
Requires<[HasSRAM]>;
@@ -1164,7 +1164,7 @@ isReMaterializable = 1 in
// Indirect loads (with postincrement or predecrement).
let mayLoad = 1,
hasSideEffects = 0,
-Constraints = "$ptrreg = $base_wb, at earlyclobber $reg, at earlyclobber $base_wb" in
+Constraints = "$ptrreg = $base_wb, at earlyclobber $reg" in
{
def LDRdPtrPi : FSTLD<0,
0b01,
Modified: llvm/trunk/test/CodeGen/AVR/atomics/load16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/atomics/load16.ll?rev=314896&r1=314895&r2=314896&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/atomics/load16.ll (original)
+++ llvm/trunk/test/CodeGen/AVR/atomics/load16.ll Wed Oct 4 03:33:36 2017
@@ -3,8 +3,8 @@
; CHECK-LABEL: atomic_load16
; CHECK: in r0, 63
; CHECK-NEXT: cli
+; CHECK-NEXT: ld [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]+
; CHECK-NEXT: ld [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]
-; CHECK-NEXT: ldd [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]+
; CHECK-NEXT: out 63, r0
define i16 @atomic_load16(i16* %foo) {
%val = load atomic i16, i16* %foo unordered, align 2
@@ -29,8 +29,8 @@ define i16 @atomic_load_cmp_swap16(i16*
; CHECK-LABEL: atomic_load_add16
; CHECK: in r0, 63
; CHECK-NEXT: cli
-; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]
-; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]+
+; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]+
+; CHECK-NEXT: ld [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]
; CHECK-NEXT: add [[RR1]], [[TMP:r[0-9]+]]
; CHECK-NEXT: adc [[RR2]], [[TMP:r[0-9]+]]
; CHECK-NEXT: st [[RD1]], [[RR1]]
@@ -44,8 +44,8 @@ define i16 @atomic_load_add16(i16* %foo)
; CHECK-LABEL: atomic_load_sub16
; CHECK: in r0, 63
; CHECK-NEXT: cli
-; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]
-; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]+
+; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]+
+; CHECK-NEXT: ld [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]
; CHECK-NEXT: sub [[RR1]], [[TMP:r[0-9]+]]
; CHECK-NEXT: sbc [[RR2]], [[TMP:r[0-9]+]]
; CHECK-NEXT: st [[RD1]], [[RR1]]
@@ -59,8 +59,8 @@ define i16 @atomic_load_sub16(i16* %foo)
; CHECK-LABEL: atomic_load_and16
; CHECK: in r0, 63
; CHECK-NEXT: cli
-; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]
-; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]+
+; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]+
+; CHECK-NEXT: ld [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]
; CHECK-NEXT: and [[RR1]], [[TMP:r[0-9]+]]
; CHECK-NEXT: and [[RR2]], [[TMP:r[0-9]+]]
; CHECK-NEXT: st [[RD1]], [[RR1]]
@@ -74,8 +74,8 @@ define i16 @atomic_load_and16(i16* %foo)
; CHECK-LABEL: atomic_load_or16
; CHECK: in r0, 63
; CHECK-NEXT: cli
-; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]
-; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]+
+; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]+
+; CHECK-NEXT: ld [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]
; CHECK-NEXT: or [[RR1]], [[TMP:r[0-9]+]]
; CHECK-NEXT: or [[RR2]], [[TMP:r[0-9]+]]
; CHECK-NEXT: st [[RD1]], [[RR1]]
@@ -89,8 +89,8 @@ define i16 @atomic_load_or16(i16* %foo)
; CHECK-LABEL: atomic_load_xor16
; CHECK: in r0, 63
; CHECK-NEXT: cli
-; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]
-; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]+
+; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]+
+; CHECK-NEXT: ld [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]
; CHECK-NEXT: eor [[RR1]], [[TMP:r[0-9]+]]
; CHECK-NEXT: eor [[RR2]], [[TMP:r[0-9]+]]
; CHECK-NEXT: st [[RD1]], [[RR1]]
Modified: llvm/trunk/test/CodeGen/AVR/load.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/load.ll?rev=314896&r1=314895&r2=314896&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/load.ll (original)
+++ llvm/trunk/test/CodeGen/AVR/load.ll Wed Oct 4 03:33:36 2017
@@ -9,8 +9,8 @@ define i8 @load8(i8* %x) {
define i16 @load16(i16* %x) {
; CHECK-LABEL: load16:
-; CHECK: ld r24, {{[YZ]}}
-; CHECK: ldd r25, {{[YZ]}}+1
+; CHECK: ld r24, {{[XYZ]}}+
+; CHECK: ld r25, {{[XYZ]}}
%1 = load i16, i16* %x
ret i16 %1
}
@@ -45,11 +45,11 @@ define i16 @load16disp(i16* %x) {
define i16 @load16nodisp(i16* %x) {
; CHECK-LABEL: load16nodisp:
-; CHECK: movw r30, r24
-; CHECK: subi r30, 192
-; CHECK: sbci r31, 255
-; CHECK: ld r24, {{[YZ]}}
-; CHECK: ldd r25, {{[YZ]}}+1
+; CHECK: movw r26, r24
+; CHECK: subi r26, 192
+; CHECK: sbci r27, 255
+; CHECK: ld r24, {{[XYZ]}}+
+; CHECK: ld r25, {{[XYZ]}}
%1 = getelementptr inbounds i16, i16* %x, i64 32
%2 = load i16, i16* %1
ret i16 %2
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir?rev=314896&r1=314895&r2=314896&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir Wed Oct 4 03:33:36 2017
@@ -18,9 +18,9 @@ body: |
; CHECK-LABEL: test_ldwrdptr
- ; CHECK: ld [[SCRATCH:r[0-9]+]], Z
+ ; CHECK: ld [[SCRATCH:r[0-9]+]], Z+
; CHECK-NEXT: push [[SCRATCH]]
- ; CHECK-NEXT: ldd [[SCRATCH]], Z+1
+ ; CHECK-NEXT: ld [[SCRATCH]], Z
; CHECK-NEXT: mov r31, [[SCRATCH]]
; CHECK-NEXT: pop r30
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr.mir?rev=314896&r1=314895&r2=314896&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr.mir Wed Oct 4 03:33:36 2017
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_ldwrdptr
- ; CHECK: %r0 = LDRdPtr %r31r30
- ; CHECK-NEXT: early-clobber %r1 = LDDRdPtrQ %r31r30, 1
+ ; CHECK: %r0, %r31r30 = LDRdPtrPi %r31r30
+ ; CHECK-NEXT: %r1 = LDRdPtr %r31r30
%r1r0 = LDWRdPtr %r31r30
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir?rev=314896&r1=314895&r2=314896&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir Wed Oct 4 03:33:36 2017
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_ldwrdptrpd
- ; CHECK: early-clobber %r1, early-clobber %r31r30 = LDRdPtrPd killed %r31r30
- ; CHECK-NEXT: early-clobber %r0, early-clobber %r31r30 = LDRdPtrPd killed %r31r30
+ ; CHECK: early-clobber %r1, %r31r30 = LDRdPtrPd killed %r31r30
+ ; CHECK-NEXT: early-clobber %r0, %r31r30 = LDRdPtrPd killed %r31r30
%r1r0, %r31r30 = LDWRdPtrPd %r31r30
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir?rev=314896&r1=314895&r2=314896&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir Wed Oct 4 03:33:36 2017
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_ldwrdptrpi
- ; CHECK: early-clobber %r0, early-clobber %r31r30 = LDRdPtrPi killed %r31r30
- ; CHECK-NEXT: early-clobber %r1, early-clobber %r31r30 = LDRdPtrPi killed %r31r30
+ ; CHECK: early-clobber %r0, %r31r30 = LDRdPtrPi killed %r31r30
+ ; CHECK-NEXT: early-clobber %r1, %r31r30 = LDRdPtrPi killed %r31r30
%r1r0, %r31r30 = LDWRdPtrPi %r31r30
...
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