[PATCH] D38275: [X86] Imiprove handling of UDIVREM8_ZEXT_HREG/UDIVREM8_SEXT_HREG to support 64-bit extensions.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 3 14:22:59 PDT 2017
craig.topper updated this revision to Diff 117585.
craig.topper retitled this revision from "[X86] Remove dead code from X86DAGToDAGISel's handling of DIV" to "[X86] Imiprove handling of UDIVREM8_ZEXT_HREG/UDIVREM8_SEXT_HREG to support 64-bit extensions.".
craig.topper added a comment.
If the extend type is 64-bits, emit a 32-bit -> 64-bit extend after the UDIVREM8_ZEXT_HREG/UDIVREM8_SEXT_HREG operation.
This gives a shorter encoding for the second extend in the sext case, and allows us to completely remove the second extend in the zext case.
https://reviews.llvm.org/D38275
Files:
lib/Target/X86/X86ISelDAGToDAG.cpp
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/X86/divrem8_ext.ll
Index: test/CodeGen/X86/divrem8_ext.ll
===================================================================
--- test/CodeGen/X86/divrem8_ext.ll
+++ test/CodeGen/X86/divrem8_ext.ll
@@ -92,7 +92,6 @@
; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
; X64-NEXT: divb %sil
; X64-NEXT: movzbl %ah, %eax # NOREX
-; X64-NEXT: movzbl %al, %eax
; X64-NEXT: retq
%1 = urem i8 %x, %y
%2 = zext i8 %1 to i64
@@ -190,7 +189,7 @@
; X64-NEXT: cbtw
; X64-NEXT: idivb %sil
; X64-NEXT: movsbl %ah, %eax # NOREX
-; X64-NEXT: movsbq %al, %rax
+; X64-NEXT: cltq
; X64-NEXT: retq
%1 = srem i8 %x, %y
%2 = sext i8 %1 to i64
@@ -205,17 +204,17 @@
; X32-NEXT: divb {{[0-9]+}}(%esp)
; X32-NEXT: movzbl %ah, %ecx # NOREX
; X32-NEXT: movzbl %al, %eax
-; X32-NEXT: addl %ecx, %eax
; X32-NEXT: xorl %edx, %edx
+; X32-NEXT: addl %ecx, %eax
+; X32-NEXT: setb %dl
; X32-NEXT: retl
;
; X64-LABEL: pr25754:
; X64: # BB#0:
; X64-NEXT: movzbl %dil, %eax
; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
; X64-NEXT: divb %sil
; X64-NEXT: movzbl %ah, %ecx # NOREX
-; X64-NEXT: movzbl %cl, %ecx
; X64-NEXT: movzbl %al, %eax
; X64-NEXT: addq %rcx, %rax
; X64-NEXT: retq
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -34681,15 +34681,19 @@
EVT VT = N->getValueType(0);
EVT InVT = N0.getValueType();
- if (N0.getResNo() != 1 || InVT != MVT::i8 || VT != MVT::i32)
+ if (N0.getResNo() != 1 || InVT != MVT::i8 ||
+ !(VT == MVT::i32 || VT == MVT::i64))
return SDValue();
- SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
+ SDVTList NodeTys = DAG.getVTList(MVT::i8, MVT::i32);
auto DivRemOpcode = OpcodeN0 == ISD::SDIVREM ? X86ISD::SDIVREM8_SEXT_HREG
: X86ISD::UDIVREM8_ZEXT_HREG;
SDValue R = DAG.getNode(DivRemOpcode, SDLoc(N), NodeTys, N0.getOperand(0),
N0.getOperand(1));
DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
+ // If this was a 64-bit extend, complete it.
+ if (VT == MVT::i64)
+ return DAG.getNode(OpcodeN, SDLoc(N), VT, R.getValue(1));
return R.getValue(1);
}
Index: lib/Target/X86/X86ISelDAGToDAG.cpp
===================================================================
--- lib/Target/X86/X86ISelDAGToDAG.cpp
+++ lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -2914,19 +2914,7 @@
if (Opcode == X86ISD::UDIVREM8_ZEXT_HREG ||
Opcode == X86ISD::SDIVREM8_SEXT_HREG) {
- if (Node->getValueType(1) == MVT::i64) {
- // It's not possible to directly movsx AH to a 64bit register, because
- // the latter needs the REX prefix, but the former can't have it.
- assert(Opcode != X86ISD::SDIVREM8_SEXT_HREG &&
- "Unexpected i64 sext of h-register");
- Result =
- SDValue(CurDAG->getMachineNode(
- TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
- CurDAG->getTargetConstant(0, dl, MVT::i64), Result,
- CurDAG->getTargetConstant(X86::sub_32bit, dl,
- MVT::i32)),
- 0);
- }
+ assert(Node->getValueType(1) == MVT::i32 && "Unexpected result type!");
} else {
Result =
CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result);
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