[llvm] r314788 - [X86][SSE] Add support for lowering shuffles to PACKSS/PACKUS
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 3 05:01:31 PDT 2017
Author: rksimon
Date: Tue Oct 3 05:01:31 2017
New Revision: 314788
URL: http://llvm.org/viewvc/llvm-project?rev=314788&view=rev
Log:
[X86][SSE] Add support for lowering shuffles to PACKSS/PACKUS
If the upper bits of a truncation shuffle patterns have at least the minimum number of sign/zero bits on their inputs then we can safely use PACKSS/PACKUS as shuffles.
Partial fix for https://bugs.llvm.org/show_bug.cgi?id=34773
Differential Revision: https://reviews.llvm.org/D38472
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/CodeGen/X86/avx-cvt-2.ll
llvm/trunk/test/CodeGen/X86/avx2-shift.ll
llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll
llvm/trunk/test/CodeGen/X86/avx2-vector-shifts.ll
llvm/trunk/test/CodeGen/X86/avx512-any_extend_load.ll
llvm/trunk/test/CodeGen/X86/avx512-trunc.ll
llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-256.ll
llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-512.ll
llvm/trunk/test/CodeGen/X86/bitcast-setcc-128.ll
llvm/trunk/test/CodeGen/X86/psubus.ll
llvm/trunk/test/CodeGen/X86/shuffle-strided-with-offset-256.ll
llvm/trunk/test/CodeGen/X86/vector-compare-results.ll
llvm/trunk/test/CodeGen/X86/vector-shift-ashr-128.ll
llvm/trunk/test/CodeGen/X86/vector-trunc.ll
llvm/trunk/test/CodeGen/X86/vselect-avx.ll
llvm/trunk/test/CodeGen/X86/widen_arith-2.ll
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=314788&r1=314787&r2=314788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Oct 3 05:01:31 2017
@@ -8664,6 +8664,39 @@ static SDValue lowerVectorShuffleWithUNP
return SDValue();
}
+// X86 has dedicated pack instructions that can handle specific truncation
+// operations: PACKSS and PACKUS.
+static SDValue lowerVectorShuffleWithPACK(const SDLoc &DL, MVT VT,
+ ArrayRef<int> Mask, SDValue V1,
+ SDValue V2, SelectionDAG &DAG,
+ const X86Subtarget &Subtarget) {
+ unsigned NumElts = VT.getVectorNumElements();
+ unsigned BitSize = VT.getScalarSizeInBits();
+ MVT PackSVT = MVT::getIntegerVT(BitSize * 2);
+ MVT PackVT = MVT::getVectorVT(PackSVT, NumElts / 2);
+
+ // TODO - Add support for unary packs.
+ SmallVector<int, 32> BinaryMask;
+ createPackShuffleMask(VT, BinaryMask, false);
+
+ if (isShuffleEquivalent(V1, V2, Mask, BinaryMask)) {
+ SDValue VV1 = DAG.getBitcast(PackVT, V1);
+ SDValue VV2 = DAG.getBitcast(PackVT, V2);
+ if ((V1.isUndef() || DAG.ComputeNumSignBits(VV1) > BitSize) &&
+ (V2.isUndef() || DAG.ComputeNumSignBits(VV2) > BitSize))
+ return DAG.getNode(X86ISD::PACKSS, DL, VT, VV1, VV2);
+
+ if (Subtarget.hasSSE41() || PackSVT == MVT::i16) {
+ APInt ZeroMask = APInt::getHighBitsSet(BitSize * 2, BitSize);
+ if ((V1.isUndef() || DAG.MaskedValueIsZero(VV1, ZeroMask)) &&
+ (V2.isUndef() || DAG.MaskedValueIsZero(VV2, ZeroMask)))
+ return DAG.getNode(X86ISD::PACKUS, DL, VT, VV1, VV2);
+ }
+ }
+
+ return SDValue();
+}
+
/// \brief Try to emit a bitmask instruction for a shuffle.
///
/// This handles cases where we can model a blend exactly as a bitmask due to
@@ -11403,6 +11436,11 @@ static SDValue lowerV8I16VectorShuffle(c
lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
return V;
+ // Use dedicated pack instructions for masks that match their pattern.
+ if (SDValue V = lowerVectorShuffleWithPACK(DL, MVT::v8i16, Mask, V1, V2,
+ DAG, Subtarget))
+ return V;
+
// Try to use byte rotation instructions.
if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
Mask, Subtarget, DAG))
@@ -11573,6 +11611,11 @@ static SDValue lowerV16I8VectorShuffle(c
DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
return Rotate;
+ // Use dedicated pack instructions for masks that match their pattern.
+ if (SDValue V = lowerVectorShuffleWithPACK(DL, MVT::v16i8, Mask, V1, V2, DAG,
+ Subtarget))
+ return V;
+
// Try to use a zext lowering.
if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
DL, MVT::v16i8, V1, V2, Mask, Zeroable, Subtarget, DAG))
@@ -13067,6 +13110,11 @@ static SDValue lowerV16I16VectorShuffle(
lowerVectorShuffleWithUNPCK(DL, MVT::v16i16, Mask, V1, V2, DAG))
return V;
+ // Use dedicated pack instructions for masks that match their pattern.
+ if (SDValue V = lowerVectorShuffleWithPACK(DL, MVT::v16i16, Mask, V1, V2, DAG,
+ Subtarget))
+ return V;
+
// Try to use shift instructions.
if (SDValue Shift = lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask,
Zeroable, Subtarget, DAG))
@@ -13153,6 +13201,11 @@ static SDValue lowerV32I8VectorShuffle(c
lowerVectorShuffleWithUNPCK(DL, MVT::v32i8, Mask, V1, V2, DAG))
return V;
+ // Use dedicated pack instructions for masks that match their pattern.
+ if (SDValue V = lowerVectorShuffleWithPACK(DL, MVT::v32i8, Mask, V1, V2, DAG,
+ Subtarget))
+ return V;
+
// Try to use shift instructions.
if (SDValue Shift = lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask,
Zeroable, Subtarget, DAG))
Modified: llvm/trunk/test/CodeGen/X86/avx-cvt-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-cvt-2.ll?rev=314788&r1=314787&r2=314788&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-cvt-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-cvt-2.ll Tue Oct 3 05:01:31 2017
@@ -50,7 +50,7 @@ define void @fptoui8(%f32vec_t %a, %i8ve
; CHECK-NEXT: vpshufb %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; CHECK-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; CHECK-NEXT: vpackuswb %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovq %xmm0, (%rdi)
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
@@ -68,7 +68,7 @@ define void @fptosi8(%f32vec_t %a, %i8ve
; CHECK-NEXT: vpshufb %xmm2, %xmm1, %xmm1
; CHECK-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; CHECK-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; CHECK-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovq %xmm0, (%rdi)
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
Modified: llvm/trunk/test/CodeGen/X86/avx2-shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-shift.ll?rev=314788&r1=314787&r2=314788&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-shift.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-shift.ll Tue Oct 3 05:01:31 2017
@@ -556,7 +556,7 @@ define <8 x i16> @variable_ashr16(<8 x i
; X32-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; X32-NEXT: vpmovsxwd %xmm0, %ymm0
; X32-NEXT: vpsravd %ymm1, %ymm0, %ymm0
-; X32-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
+; X32-NEXT: vpackssdw %ymm0, %ymm0, %ymm0
; X32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; X32-NEXT: vzeroupper
@@ -567,7 +567,7 @@ define <8 x i16> @variable_ashr16(<8 x i
; X64-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; X64-NEXT: vpmovsxwd %xmm0, %ymm0
; X64-NEXT: vpsravd %ymm1, %ymm0, %ymm0
-; X64-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
+; X64-NEXT: vpackssdw %ymm0, %ymm0, %ymm0
; X64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; X64-NEXT: vzeroupper
Modified: llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll?rev=314788&r1=314787&r2=314788&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll Tue Oct 3 05:01:31 2017
@@ -267,15 +267,15 @@ define <16 x i16> @broadcast_mem_v4i16_v
; X32-AVX2-LABEL: broadcast_mem_v4i16_v16i16:
; X32-AVX2: ## BB#0:
; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
-; X32-AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6,7,4,5,6,7,6,7],zero,zero
+; X32-AVX2-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
+; X32-AVX2-NEXT: vpackusdw %xmm0, %xmm0, %xmm0
; X32-AVX2-NEXT: vpbroadcastq %xmm0, %ymm0
; X32-AVX2-NEXT: retl
;
; X64-AVX2-LABEL: broadcast_mem_v4i16_v16i16:
; X64-AVX2: ## BB#0:
-; X64-AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
-; X64-AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6,7,4,5,6,7,6,7],zero,zero
+; X64-AVX2-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
+; X64-AVX2-NEXT: vpackusdw %xmm0, %xmm0, %xmm0
; X64-AVX2-NEXT: vpbroadcastq %xmm0, %ymm0
; X64-AVX2-NEXT: retq
;
Modified: llvm/trunk/test/CodeGen/X86/avx2-vector-shifts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-vector-shifts.ll?rev=314788&r1=314787&r2=314788&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-vector-shifts.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-vector-shifts.ll Tue Oct 3 05:01:31 2017
@@ -499,7 +499,7 @@ define <8 x i16> @ashr_8i16(<8 x i16> %r
; X32-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; X32-NEXT: vpmovsxwd %xmm0, %ymm0
; X32-NEXT: vpsravd %ymm1, %ymm0, %ymm0
-; X32-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
+; X32-NEXT: vpackssdw %ymm0, %ymm0, %ymm0
; X32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; X32-NEXT: vzeroupper
@@ -510,7 +510,7 @@ define <8 x i16> @ashr_8i16(<8 x i16> %r
; X64-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; X64-NEXT: vpmovsxwd %xmm0, %ymm0
; X64-NEXT: vpsravd %ymm1, %ymm0, %ymm0
-; X64-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
+; X64-NEXT: vpackssdw %ymm0, %ymm0, %ymm0
; X64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; X64-NEXT: vzeroupper
Modified: llvm/trunk/test/CodeGen/X86/avx512-any_extend_load.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-any_extend_load.ll?rev=314788&r1=314787&r2=314788&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-any_extend_load.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-any_extend_load.ll Tue Oct 3 05:01:31 2017
@@ -57,7 +57,7 @@ define void @any_extend_load_v8i16(<8 x
; KNL: # BB#0:
; KNL-NEXT: vpmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
; KNL-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0
-; KNL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; KNL-NEXT: vpackuswb %xmm0, %xmm0, %xmm0
; KNL-NEXT: vmovq %xmm0, (%rdi)
; KNL-NEXT: retq
;
Modified: llvm/trunk/test/CodeGen/X86/avx512-trunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-trunc.ll?rev=314788&r1=314787&r2=314788&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-trunc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-trunc.ll Tue Oct 3 05:01:31 2017
@@ -584,7 +584,7 @@ define void @usat_trunc_wb_128_mem(<8 x
; KNL-LABEL: usat_trunc_wb_128_mem:
; KNL: ## BB#0:
; KNL-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0
-; KNL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; KNL-NEXT: vpackuswb %xmm0, %xmm0, %xmm0
; KNL-NEXT: vmovq %xmm0, (%rdi)
; KNL-NEXT: retq
;
Modified: llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-256.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-256.ll?rev=314788&r1=314787&r2=314788&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-256.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-256.ll Tue Oct 3 05:01:31 2017
@@ -149,41 +149,18 @@ define i4 @v4f64(<4 x double> %a, <4 x d
}
define i16 @v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c, <16 x i16> %d) {
-; SSE2-LABEL: v16i16:
-; SSE2: # BB#0:
-; SSE2-NEXT: pcmpgtw %xmm3, %xmm1
-; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255]
-; SSE2-NEXT: pand %xmm3, %xmm1
-; SSE2-NEXT: pcmpgtw %xmm2, %xmm0
-; SSE2-NEXT: pand %xmm3, %xmm0
-; SSE2-NEXT: packuswb %xmm1, %xmm0
-; SSE2-NEXT: pcmpgtw %xmm7, %xmm5
-; SSE2-NEXT: pand %xmm3, %xmm5
-; SSE2-NEXT: pcmpgtw %xmm6, %xmm4
-; SSE2-NEXT: pand %xmm3, %xmm4
-; SSE2-NEXT: packuswb %xmm5, %xmm4
-; SSE2-NEXT: pand %xmm0, %xmm4
-; SSE2-NEXT: pmovmskb %xmm4, %eax
-; SSE2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
-; SSE2-NEXT: retq
-;
-; SSSE3-LABEL: v16i16:
-; SSSE3: # BB#0:
-; SSSE3-NEXT: pcmpgtw %xmm3, %xmm1
-; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
-; SSSE3-NEXT: pshufb %xmm3, %xmm1
-; SSSE3-NEXT: pcmpgtw %xmm2, %xmm0
-; SSSE3-NEXT: pshufb %xmm3, %xmm0
-; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; SSSE3-NEXT: pcmpgtw %xmm7, %xmm5
-; SSSE3-NEXT: pshufb %xmm3, %xmm5
-; SSSE3-NEXT: pcmpgtw %xmm6, %xmm4
-; SSSE3-NEXT: pshufb %xmm3, %xmm4
-; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0]
-; SSSE3-NEXT: pand %xmm0, %xmm4
-; SSSE3-NEXT: pmovmskb %xmm4, %eax
-; SSSE3-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
-; SSSE3-NEXT: retq
+; SSE2-SSSE3-LABEL: v16i16:
+; SSE2-SSSE3: # BB#0:
+; SSE2-SSSE3-NEXT: pcmpgtw %xmm3, %xmm1
+; SSE2-SSSE3-NEXT: pcmpgtw %xmm2, %xmm0
+; SSE2-SSSE3-NEXT: packsswb %xmm1, %xmm0
+; SSE2-SSSE3-NEXT: pcmpgtw %xmm7, %xmm5
+; SSE2-SSSE3-NEXT: pcmpgtw %xmm6, %xmm4
+; SSE2-SSSE3-NEXT: packsswb %xmm5, %xmm4
+; SSE2-SSSE3-NEXT: pand %xmm0, %xmm4
+; SSE2-SSSE3-NEXT: pmovmskb %xmm4, %eax
+; SSE2-SSSE3-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: retq
;
; AVX1-LABEL: v16i16:
; AVX1: # BB#0:
@@ -236,42 +213,33 @@ define i8 @v8i32(<8 x i32> %a, <8 x i32>
; SSE2-LABEL: v8i32:
; SSE2: # BB#0:
; SSE2-NEXT: pcmpgtd %xmm3, %xmm1
-; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7]
-; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
+; SSE2-NEXT: packssdw %xmm0, %xmm1
; SSE2-NEXT: pcmpgtd %xmm2, %xmm0
-; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE2-NEXT: packssdw %xmm0, %xmm0
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE2-NEXT: pcmpgtd %xmm7, %xmm5
-; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm5[0,2,2,3,4,5,6,7]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7]
-; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
+; SSE2-NEXT: packssdw %xmm0, %xmm5
; SSE2-NEXT: pcmpgtd %xmm6, %xmm4
-; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm4[0,2,2,3,4,5,6,7]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7]
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
-; SSE2-NEXT: pand %xmm0, %xmm2
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm2
-; SSE2-NEXT: packuswb %xmm2, %xmm2
-; SSE2-NEXT: pmovmskb %xmm2, %eax
+; SSE2-NEXT: packssdw %xmm0, %xmm4
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0]
+; SSE2-NEXT: pand %xmm0, %xmm4
+; SSE2-NEXT: pand {{.*}}(%rip), %xmm4
+; SSE2-NEXT: packuswb %xmm4, %xmm4
+; SSE2-NEXT: pmovmskb %xmm4, %eax
; SSE2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
; SSE2-NEXT: retq
;
; SSSE3-LABEL: v8i32:
; SSSE3: # BB#0:
; SSSE3-NEXT: pcmpgtd %xmm3, %xmm1
-; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
-; SSSE3-NEXT: pshufb %xmm3, %xmm1
+; SSSE3-NEXT: packssdw %xmm0, %xmm1
; SSSE3-NEXT: pcmpgtd %xmm2, %xmm0
-; SSSE3-NEXT: pshufb %xmm3, %xmm0
+; SSSE3-NEXT: packssdw %xmm0, %xmm0
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSSE3-NEXT: pcmpgtd %xmm7, %xmm5
-; SSSE3-NEXT: pshufb %xmm3, %xmm5
+; SSSE3-NEXT: packssdw %xmm0, %xmm5
; SSSE3-NEXT: pcmpgtd %xmm6, %xmm4
-; SSSE3-NEXT: pshufb %xmm3, %xmm4
+; SSSE3-NEXT: packssdw %xmm0, %xmm4
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0]
; SSSE3-NEXT: pand %xmm0, %xmm4
; SSSE3-NEXT: pshufb {{.*#+}} xmm4 = xmm4[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
Modified: llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-512.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-512.ll?rev=314788&r1=314787&r2=314788&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-512.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bitcast-and-setcc-512.ll Tue Oct 3 05:01:31 2017
@@ -40,7 +40,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64>
; SSE-NEXT: pand %xmm0, %xmm2
; SSE-NEXT: psllw $15, %xmm2
; SSE-NEXT: psraw $15, %xmm2
-; SSE-NEXT: pshufb {{.*#+}} xmm2 = xmm2[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; SSE-NEXT: packsswb %xmm0, %xmm2
; SSE-NEXT: pmovmskb %xmm2, %eax
; SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
; SSE-NEXT: retq
@@ -77,7 +77,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64>
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsllw $15, %xmm0, %xmm0
; AVX1-NEXT: vpsraw $15, %xmm0, %xmm0
-; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; AVX1-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vpmovmskb %xmm0, %eax
; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
; AVX1-NEXT: vzeroupper
@@ -107,7 +107,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64>
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpsllw $15, %xmm0, %xmm0
; AVX2-NEXT: vpsraw $15, %xmm0, %xmm0
-; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; AVX2-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vpmovmskb %xmm0, %eax
; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
; AVX2-NEXT: vzeroupper
@@ -172,7 +172,7 @@ define i8 @v8f64(<8 x double> %a, <8 x d
; SSE-NEXT: pand %xmm0, %xmm2
; SSE-NEXT: psllw $15, %xmm2
; SSE-NEXT: psraw $15, %xmm2
-; SSE-NEXT: pshufb {{.*#+}} xmm2 = xmm2[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; SSE-NEXT: packsswb %xmm0, %xmm2
; SSE-NEXT: pmovmskb %xmm2, %eax
; SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
; SSE-NEXT: retq
@@ -201,7 +201,7 @@ define i8 @v8f64(<8 x double> %a, <8 x d
; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX12-NEXT: vpsllw $15, %xmm0, %xmm0
; AVX12-NEXT: vpsraw $15, %xmm0, %xmm0
-; AVX12-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; AVX12-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
; AVX12-NEXT: vpmovmskb %xmm0, %eax
; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
; AVX12-NEXT: vzeroupper
@@ -235,33 +235,24 @@ define i32 @v32i16(<32 x i16> %a, <32 x
; SSE-LABEL: v32i16:
; SSE: # BB#0:
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
-; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
+; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11
; SSE-NEXT: pcmpgtw %xmm5, %xmm1
-; SSE-NEXT: movdqa {{.*#+}} xmm5 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
-; SSE-NEXT: pshufb %xmm5, %xmm1
; SSE-NEXT: pcmpgtw %xmm4, %xmm0
-; SSE-NEXT: pshufb %xmm5, %xmm0
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE-NEXT: packsswb %xmm1, %xmm0
; SSE-NEXT: pcmpgtw %xmm7, %xmm3
-; SSE-NEXT: pshufb %xmm5, %xmm3
; SSE-NEXT: pcmpgtw %xmm6, %xmm2
-; SSE-NEXT: pshufb %xmm5, %xmm2
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
+; SSE-NEXT: packsswb %xmm3, %xmm2
; SSE-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm11
-; SSE-NEXT: pshufb %xmm5, %xmm11
-; SSE-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm9
-; SSE-NEXT: pshufb %xmm5, %xmm9
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm9 = xmm9[0],xmm11[0]
-; SSE-NEXT: pand %xmm0, %xmm9
; SSE-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm10
-; SSE-NEXT: pshufb %xmm5, %xmm10
+; SSE-NEXT: packsswb %xmm11, %xmm10
+; SSE-NEXT: pand %xmm0, %xmm10
+; SSE-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm8
-; SSE-NEXT: pshufb %xmm5, %xmm8
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm8 = xmm8[0],xmm10[0]
+; SSE-NEXT: packsswb %xmm9, %xmm8
; SSE-NEXT: pand %xmm2, %xmm8
-; SSE-NEXT: pmovmskb %xmm9, %ecx
+; SSE-NEXT: pmovmskb %xmm10, %ecx
; SSE-NEXT: pmovmskb %xmm8, %eax
; SSE-NEXT: shll $16, %eax
; SSE-NEXT: orl %ecx, %eax
@@ -639,33 +630,27 @@ define i16 @v16i32(<16 x i32> %a, <16 x
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11
; SSE-NEXT: pcmpgtd %xmm7, %xmm3
-; SSE-NEXT: movdqa {{.*#+}} xmm7 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
-; SSE-NEXT: pshufb %xmm7, %xmm3
+; SSE-NEXT: packssdw %xmm0, %xmm3
; SSE-NEXT: pcmpgtd %xmm6, %xmm2
-; SSE-NEXT: pshufb %xmm7, %xmm2
+; SSE-NEXT: packssdw %xmm0, %xmm2
; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; SSE-NEXT: movdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
-; SSE-NEXT: pshufb %xmm3, %xmm2
; SSE-NEXT: pcmpgtd %xmm5, %xmm1
-; SSE-NEXT: pshufb %xmm7, %xmm1
+; SSE-NEXT: packssdw %xmm0, %xmm1
; SSE-NEXT: pcmpgtd %xmm4, %xmm0
-; SSE-NEXT: pshufb %xmm7, %xmm0
+; SSE-NEXT: packssdw %xmm0, %xmm0
; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; SSE-NEXT: pshufb %xmm3, %xmm0
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; SSE-NEXT: packsswb %xmm2, %xmm0
; SSE-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm11
-; SSE-NEXT: pshufb %xmm7, %xmm11
+; SSE-NEXT: packssdw %xmm0, %xmm11
; SSE-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm9
-; SSE-NEXT: pshufb %xmm7, %xmm9
+; SSE-NEXT: packssdw %xmm0, %xmm9
; SSE-NEXT: punpcklqdq {{.*#+}} xmm9 = xmm9[0],xmm11[0]
-; SSE-NEXT: pshufb %xmm3, %xmm9
; SSE-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm10
-; SSE-NEXT: pshufb %xmm7, %xmm10
+; SSE-NEXT: packssdw %xmm0, %xmm10
; SSE-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm8
-; SSE-NEXT: pshufb %xmm7, %xmm8
+; SSE-NEXT: packssdw %xmm0, %xmm8
; SSE-NEXT: punpcklqdq {{.*#+}} xmm8 = xmm8[0],xmm10[0]
-; SSE-NEXT: pshufb %xmm3, %xmm8
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm8 = xmm8[0],xmm9[0]
+; SSE-NEXT: packsswb %xmm9, %xmm8
; SSE-NEXT: pand %xmm0, %xmm8
; SSE-NEXT: pmovmskb %xmm8, %eax
; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
Modified: llvm/trunk/test/CodeGen/X86/bitcast-setcc-128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitcast-setcc-128.ll?rev=314788&r1=314787&r2=314788&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bitcast-setcc-128.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bitcast-setcc-128.ll Tue Oct 3 05:01:31 2017
@@ -6,27 +6,18 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl,+avx512bw | FileCheck %s --check-prefixes=AVX512
define i8 @v8i16(<8 x i16> %a, <8 x i16> %b) {
-; SSE2-LABEL: v8i16:
-; SSE2: # BB#0:
-; SSE2-NEXT: pcmpgtw %xmm1, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
-; SSE2-NEXT: packuswb %xmm0, %xmm0
-; SSE2-NEXT: pmovmskb %xmm0, %eax
-; SSE2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
-; SSE2-NEXT: retq
-;
-; SSSE3-LABEL: v8i16:
-; SSSE3: # BB#0:
-; SSSE3-NEXT: pcmpgtw %xmm1, %xmm0
-; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
-; SSSE3-NEXT: pmovmskb %xmm0, %eax
-; SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
-; SSSE3-NEXT: retq
+; SSE2-SSSE3-LABEL: v8i16:
+; SSE2-SSSE3: # BB#0:
+; SSE2-SSSE3-NEXT: pcmpgtw %xmm1, %xmm0
+; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm0
+; SSE2-SSSE3-NEXT: pmovmskb %xmm0, %eax
+; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v8i16:
; AVX12: # BB#0:
; AVX12-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0
-; AVX12-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; AVX12-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
; AVX12-NEXT: vpmovmskb %xmm0, %eax
; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
; AVX12-NEXT: retq
@@ -503,30 +494,17 @@ define i4 @v4i16(<4 x i16> %a, <4 x i16>
}
define i8 @v8i8(<8 x i8> %a, <8 x i8> %b) {
-; SSE2-LABEL: v8i8:
-; SSE2: # BB#0:
-; SSE2-NEXT: psllw $8, %xmm1
-; SSE2-NEXT: psraw $8, %xmm1
-; SSE2-NEXT: psllw $8, %xmm0
-; SSE2-NEXT: psraw $8, %xmm0
-; SSE2-NEXT: pcmpgtw %xmm1, %xmm0
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
-; SSE2-NEXT: packuswb %xmm0, %xmm0
-; SSE2-NEXT: pmovmskb %xmm0, %eax
-; SSE2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
-; SSE2-NEXT: retq
-;
-; SSSE3-LABEL: v8i8:
-; SSSE3: # BB#0:
-; SSSE3-NEXT: psllw $8, %xmm1
-; SSSE3-NEXT: psraw $8, %xmm1
-; SSSE3-NEXT: psllw $8, %xmm0
-; SSSE3-NEXT: psraw $8, %xmm0
-; SSSE3-NEXT: pcmpgtw %xmm1, %xmm0
-; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
-; SSSE3-NEXT: pmovmskb %xmm0, %eax
-; SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
-; SSSE3-NEXT: retq
+; SSE2-SSSE3-LABEL: v8i8:
+; SSE2-SSSE3: # BB#0:
+; SSE2-SSSE3-NEXT: psllw $8, %xmm1
+; SSE2-SSSE3-NEXT: psraw $8, %xmm1
+; SSE2-SSSE3-NEXT: psllw $8, %xmm0
+; SSE2-SSSE3-NEXT: psraw $8, %xmm0
+; SSE2-SSSE3-NEXT: pcmpgtw %xmm1, %xmm0
+; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm0
+; SSE2-SSSE3-NEXT: pmovmskb %xmm0, %eax
+; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
+; SSE2-SSSE3-NEXT: retq
;
; AVX12-LABEL: v8i8:
; AVX12: # BB#0:
@@ -535,7 +513,7 @@ define i8 @v8i8(<8 x i8> %a, <8 x i8> %b
; AVX12-NEXT: vpsllw $8, %xmm0, %xmm0
; AVX12-NEXT: vpsraw $8, %xmm0, %xmm0
; AVX12-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0
-; AVX12-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; AVX12-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
; AVX12-NEXT: vpmovmskb %xmm0, %eax
; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
; AVX12-NEXT: retq
Modified: llvm/trunk/test/CodeGen/X86/psubus.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/psubus.ll?rev=314788&r1=314787&r2=314788&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/psubus.ll (original)
+++ llvm/trunk/test/CodeGen/X86/psubus.ll Tue Oct 3 05:01:31 2017
@@ -464,20 +464,17 @@ define <8 x i16> @test13(<8 x i16> %x, <
; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648]
; SSE2-NEXT: movdqa %xmm0, %xmm5
; SSE2-NEXT: psubd %xmm2, %xmm0
-; SSE2-NEXT: pxor %xmm4, %xmm2
+; SSE2-NEXT: movdqa %xmm2, %xmm6
+; SSE2-NEXT: pxor %xmm4, %xmm6
; SSE2-NEXT: pxor %xmm4, %xmm5
-; SSE2-NEXT: pcmpgtd %xmm5, %xmm2
-; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7]
-; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm2[0,2,2,3]
+; SSE2-NEXT: pcmpgtd %xmm5, %xmm6
+; SSE2-NEXT: packssdw %xmm0, %xmm6
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pxor %xmm4, %xmm2
; SSE2-NEXT: pxor %xmm3, %xmm4
; SSE2-NEXT: pcmpgtd %xmm4, %xmm2
-; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7]
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm5[0]
+; SSE2-NEXT: packssdw %xmm0, %xmm2
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm6[0]
; SSE2-NEXT: psubd %xmm1, %xmm3
; SSE2-NEXT: pslld $16, %xmm0
; SSE2-NEXT: psrad $16, %xmm0
@@ -501,17 +498,17 @@ define <8 x i16> @test13(<8 x i16> %x, <
; SSSE3-NEXT: pxor %xmm4, %xmm6
; SSSE3-NEXT: pxor %xmm4, %xmm5
; SSSE3-NEXT: pcmpgtd %xmm5, %xmm6
-; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
-; SSSE3-NEXT: pshufb %xmm5, %xmm6
+; SSSE3-NEXT: packssdw %xmm0, %xmm6
; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pxor %xmm4, %xmm2
; SSSE3-NEXT: pxor %xmm3, %xmm4
; SSSE3-NEXT: pcmpgtd %xmm4, %xmm2
-; SSSE3-NEXT: pshufb %xmm5, %xmm2
+; SSSE3-NEXT: packssdw %xmm0, %xmm2
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm6[0]
; SSSE3-NEXT: psubd %xmm1, %xmm3
-; SSSE3-NEXT: pshufb %xmm5, %xmm0
-; SSSE3-NEXT: pshufb %xmm5, %xmm3
+; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
+; SSSE3-NEXT: pshufb %xmm1, %xmm0
+; SSSE3-NEXT: pshufb %xmm1, %xmm3
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0]
; SSSE3-NEXT: pandn %xmm3, %xmm2
; SSSE3-NEXT: movdqa %xmm2, %xmm0
@@ -529,15 +526,15 @@ define <8 x i16> @test13(<8 x i16> %x, <
; SSE41-NEXT: pxor %xmm5, %xmm0
; SSE41-NEXT: pxor %xmm5, %xmm6
; SSE41-NEXT: pcmpgtd %xmm6, %xmm0
-; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
-; SSE41-NEXT: pshufb %xmm1, %xmm0
-; SSE41-NEXT: movdqa %xmm2, %xmm6
-; SSE41-NEXT: pxor %xmm5, %xmm6
+; SSE41-NEXT: packssdw %xmm0, %xmm0
+; SSE41-NEXT: movdqa %xmm2, %xmm1
+; SSE41-NEXT: pxor %xmm5, %xmm1
; SSE41-NEXT: pxor %xmm4, %xmm5
-; SSE41-NEXT: pcmpgtd %xmm5, %xmm6
-; SSE41-NEXT: pshufb %xmm1, %xmm6
-; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm6[0]
+; SSE41-NEXT: pcmpgtd %xmm5, %xmm1
+; SSE41-NEXT: packssdw %xmm0, %xmm1
+; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE41-NEXT: psubd %xmm2, %xmm4
+; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; SSE41-NEXT: pshufb %xmm1, %xmm3
; SSE41-NEXT: pshufb %xmm1, %xmm4
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0]
@@ -855,35 +852,30 @@ vector.ph:
define <8 x i16> @test15(<8 x i16> %x, <8 x i32> %y) nounwind {
; SSE2-LABEL: test15:
; SSE2: # BB#0: # %vector.ph
-; SSE2-NEXT: pxor %xmm4, %xmm4
; SSE2-NEXT: movdqa %xmm0, %xmm3
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3]
-; SSE2-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]
+; SSE2-NEXT: pxor %xmm4, %xmm4
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3]
+; SSE2-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7]
; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648]
-; SSE2-NEXT: movdqa %xmm0, %xmm5
-; SSE2-NEXT: psubd %xmm2, %xmm0
+; SSE2-NEXT: movdqa %xmm3, %xmm5
+; SSE2-NEXT: psubd %xmm2, %xmm3
; SSE2-NEXT: pxor %xmm4, %xmm2
; SSE2-NEXT: pxor %xmm4, %xmm5
; SSE2-NEXT: pcmpgtd %xmm2, %xmm5
-; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm5[0,2,2,3,4,5,6,7]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7]
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
-; SSE2-NEXT: movdqa %xmm1, %xmm5
-; SSE2-NEXT: pxor %xmm4, %xmm5
-; SSE2-NEXT: pxor %xmm3, %xmm4
-; SSE2-NEXT: pcmpgtd %xmm5, %xmm4
-; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[0,2,2,3,4,5,6,7]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm4 = xmm4[0,1,2,3,4,6,6,7]
-; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm2[0]
-; SSE2-NEXT: psubd %xmm1, %xmm3
-; SSE2-NEXT: pslld $16, %xmm0
-; SSE2-NEXT: psrad $16, %xmm0
+; SSE2-NEXT: packssdw %xmm0, %xmm5
+; SSE2-NEXT: movdqa %xmm1, %xmm2
+; SSE2-NEXT: pxor %xmm4, %xmm2
+; SSE2-NEXT: pxor %xmm0, %xmm4
+; SSE2-NEXT: pcmpgtd %xmm2, %xmm4
+; SSE2-NEXT: packssdw %xmm0, %xmm4
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0]
+; SSE2-NEXT: psubd %xmm1, %xmm0
; SSE2-NEXT: pslld $16, %xmm3
; SSE2-NEXT: psrad $16, %xmm3
-; SSE2-NEXT: packssdw %xmm0, %xmm3
-; SSE2-NEXT: pand %xmm4, %xmm3
-; SSE2-NEXT: movdqa %xmm3, %xmm0
+; SSE2-NEXT: pslld $16, %xmm0
+; SSE2-NEXT: psrad $16, %xmm0
+; SSE2-NEXT: packssdw %xmm3, %xmm0
+; SSE2-NEXT: pand %xmm4, %xmm0
; SSE2-NEXT: retq
;
; SSSE3-LABEL: test15:
@@ -898,17 +890,17 @@ define <8 x i16> @test15(<8 x i16> %x, <
; SSSE3-NEXT: pxor %xmm4, %xmm2
; SSSE3-NEXT: pxor %xmm4, %xmm5
; SSSE3-NEXT: pcmpgtd %xmm2, %xmm5
-; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
-; SSSE3-NEXT: pshufb %xmm2, %xmm5
-; SSSE3-NEXT: movdqa %xmm1, %xmm6
-; SSSE3-NEXT: pxor %xmm4, %xmm6
+; SSSE3-NEXT: packssdw %xmm0, %xmm5
+; SSSE3-NEXT: movdqa %xmm1, %xmm2
+; SSSE3-NEXT: pxor %xmm4, %xmm2
; SSSE3-NEXT: pxor %xmm3, %xmm4
-; SSSE3-NEXT: pcmpgtd %xmm6, %xmm4
-; SSSE3-NEXT: pshufb %xmm2, %xmm4
+; SSSE3-NEXT: pcmpgtd %xmm2, %xmm4
+; SSSE3-NEXT: packssdw %xmm0, %xmm4
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0]
; SSSE3-NEXT: psubd %xmm1, %xmm3
-; SSSE3-NEXT: pshufb %xmm2, %xmm0
-; SSSE3-NEXT: pshufb %xmm2, %xmm3
+; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
+; SSSE3-NEXT: pshufb %xmm1, %xmm0
+; SSSE3-NEXT: pshufb %xmm1, %xmm3
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0]
; SSSE3-NEXT: pand %xmm4, %xmm3
; SSSE3-NEXT: movdqa %xmm3, %xmm0
@@ -925,15 +917,15 @@ define <8 x i16> @test15(<8 x i16> %x, <
; SSE41-NEXT: pxor %xmm4, %xmm1
; SSE41-NEXT: pxor %xmm4, %xmm5
; SSE41-NEXT: pcmpgtd %xmm1, %xmm5
-; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
-; SSE41-NEXT: pshufb %xmm1, %xmm5
-; SSE41-NEXT: movdqa %xmm2, %xmm6
-; SSE41-NEXT: pxor %xmm4, %xmm6
+; SSE41-NEXT: packssdw %xmm0, %xmm5
+; SSE41-NEXT: movdqa %xmm2, %xmm1
+; SSE41-NEXT: pxor %xmm4, %xmm1
; SSE41-NEXT: pxor %xmm3, %xmm4
-; SSE41-NEXT: pcmpgtd %xmm6, %xmm4
-; SSE41-NEXT: pshufb %xmm1, %xmm4
+; SSE41-NEXT: pcmpgtd %xmm1, %xmm4
+; SSE41-NEXT: packssdw %xmm0, %xmm4
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
; SSE41-NEXT: psubd %xmm2, %xmm3
+; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; SSE41-NEXT: pshufb %xmm1, %xmm0
; SSE41-NEXT: pshufb %xmm1, %xmm3
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
@@ -1000,35 +992,30 @@ vector.ph:
define <8 x i16> @test16(<8 x i16> %x, <8 x i32> %y) nounwind {
; SSE2-LABEL: test16:
; SSE2: # BB#0: # %vector.ph
-; SSE2-NEXT: pxor %xmm4, %xmm4
; SSE2-NEXT: movdqa %xmm0, %xmm3
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3]
-; SSE2-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]
+; SSE2-NEXT: pxor %xmm4, %xmm4
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3]
+; SSE2-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7]
; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648]
-; SSE2-NEXT: movdqa %xmm0, %xmm5
-; SSE2-NEXT: psubd %xmm2, %xmm0
+; SSE2-NEXT: movdqa %xmm3, %xmm5
+; SSE2-NEXT: psubd %xmm2, %xmm3
; SSE2-NEXT: pxor %xmm4, %xmm2
; SSE2-NEXT: pxor %xmm4, %xmm5
; SSE2-NEXT: pcmpgtd %xmm2, %xmm5
-; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm5[0,2,2,3,4,5,6,7]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7]
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
-; SSE2-NEXT: movdqa %xmm1, %xmm5
-; SSE2-NEXT: pxor %xmm4, %xmm5
-; SSE2-NEXT: pxor %xmm3, %xmm4
-; SSE2-NEXT: pcmpgtd %xmm5, %xmm4
-; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[0,2,2,3,4,5,6,7]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm4 = xmm4[0,1,2,3,4,6,6,7]
-; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm2[0]
-; SSE2-NEXT: psubd %xmm1, %xmm3
-; SSE2-NEXT: pslld $16, %xmm0
-; SSE2-NEXT: psrad $16, %xmm0
+; SSE2-NEXT: packssdw %xmm0, %xmm5
+; SSE2-NEXT: movdqa %xmm1, %xmm2
+; SSE2-NEXT: pxor %xmm4, %xmm2
+; SSE2-NEXT: pxor %xmm0, %xmm4
+; SSE2-NEXT: pcmpgtd %xmm2, %xmm4
+; SSE2-NEXT: packssdw %xmm0, %xmm4
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0]
+; SSE2-NEXT: psubd %xmm1, %xmm0
; SSE2-NEXT: pslld $16, %xmm3
; SSE2-NEXT: psrad $16, %xmm3
-; SSE2-NEXT: packssdw %xmm0, %xmm3
-; SSE2-NEXT: pand %xmm4, %xmm3
-; SSE2-NEXT: movdqa %xmm3, %xmm0
+; SSE2-NEXT: pslld $16, %xmm0
+; SSE2-NEXT: psrad $16, %xmm0
+; SSE2-NEXT: packssdw %xmm3, %xmm0
+; SSE2-NEXT: pand %xmm4, %xmm0
; SSE2-NEXT: retq
;
; SSSE3-LABEL: test16:
@@ -1043,17 +1030,17 @@ define <8 x i16> @test16(<8 x i16> %x, <
; SSSE3-NEXT: pxor %xmm4, %xmm2
; SSSE3-NEXT: pxor %xmm4, %xmm5
; SSSE3-NEXT: pcmpgtd %xmm2, %xmm5
-; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
-; SSSE3-NEXT: pshufb %xmm2, %xmm5
-; SSSE3-NEXT: movdqa %xmm1, %xmm6
-; SSSE3-NEXT: pxor %xmm4, %xmm6
+; SSSE3-NEXT: packssdw %xmm0, %xmm5
+; SSSE3-NEXT: movdqa %xmm1, %xmm2
+; SSSE3-NEXT: pxor %xmm4, %xmm2
; SSSE3-NEXT: pxor %xmm3, %xmm4
-; SSSE3-NEXT: pcmpgtd %xmm6, %xmm4
-; SSSE3-NEXT: pshufb %xmm2, %xmm4
+; SSSE3-NEXT: pcmpgtd %xmm2, %xmm4
+; SSSE3-NEXT: packssdw %xmm0, %xmm4
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0]
; SSSE3-NEXT: psubd %xmm1, %xmm3
-; SSSE3-NEXT: pshufb %xmm2, %xmm0
-; SSSE3-NEXT: pshufb %xmm2, %xmm3
+; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
+; SSSE3-NEXT: pshufb %xmm1, %xmm0
+; SSSE3-NEXT: pshufb %xmm1, %xmm3
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0]
; SSSE3-NEXT: pand %xmm4, %xmm3
; SSSE3-NEXT: movdqa %xmm3, %xmm0
@@ -1070,15 +1057,15 @@ define <8 x i16> @test16(<8 x i16> %x, <
; SSE41-NEXT: pxor %xmm4, %xmm1
; SSE41-NEXT: pxor %xmm4, %xmm5
; SSE41-NEXT: pcmpgtd %xmm1, %xmm5
-; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
-; SSE41-NEXT: pshufb %xmm1, %xmm5
-; SSE41-NEXT: movdqa %xmm2, %xmm6
-; SSE41-NEXT: pxor %xmm4, %xmm6
+; SSE41-NEXT: packssdw %xmm0, %xmm5
+; SSE41-NEXT: movdqa %xmm2, %xmm1
+; SSE41-NEXT: pxor %xmm4, %xmm1
; SSE41-NEXT: pxor %xmm3, %xmm4
-; SSE41-NEXT: pcmpgtd %xmm6, %xmm4
-; SSE41-NEXT: pshufb %xmm1, %xmm4
+; SSE41-NEXT: pcmpgtd %xmm1, %xmm4
+; SSE41-NEXT: packssdw %xmm0, %xmm4
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
; SSE41-NEXT: psubd %xmm2, %xmm3
+; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; SSE41-NEXT: pshufb %xmm1, %xmm0
; SSE41-NEXT: pshufb %xmm1, %xmm3
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
Modified: llvm/trunk/test/CodeGen/X86/shuffle-strided-with-offset-256.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shuffle-strided-with-offset-256.ll?rev=314788&r1=314787&r2=314788&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/shuffle-strided-with-offset-256.ll (original)
+++ llvm/trunk/test/CodeGen/X86/shuffle-strided-with-offset-256.ll Tue Oct 3 05:01:31 2017
@@ -88,7 +88,8 @@ define void @shuffle_v16i16_to_v8i16_1(<
; AVX2-LABEL: shuffle_v16i16_to_v8i16_1:
; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa (%rdi), %ymm0
-; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[2,3,6,7,10,11,14,15,10,11,14,15,14,15],zero,zero,ymm0[18,19,22,23,26,27,30,31,26,27,30,31,30,31],zero,zero
+; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0
+; AVX2-NEXT: vpackusdw %ymm0, %ymm0, %ymm0
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; AVX2-NEXT: vmovdqa %xmm0, (%rsi)
; AVX2-NEXT: vzeroupper
Modified: llvm/trunk/test/CodeGen/X86/vector-compare-results.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-compare-results.ll?rev=314788&r1=314787&r2=314788&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-compare-results.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector-compare-results.ll Tue Oct 3 05:01:31 2017
@@ -886,16 +886,11 @@ define <32 x i1> @test_cmp_v32i16(<32 x
; SSE2-LABEL: test_cmp_v32i16:
; SSE2: # BB#0:
; SSE2-NEXT: pcmpgtw %xmm5, %xmm1
-; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [255,255,255,255,255,255,255,255]
-; SSE2-NEXT: pand %xmm5, %xmm1
; SSE2-NEXT: pcmpgtw %xmm4, %xmm0
-; SSE2-NEXT: pand %xmm5, %xmm0
-; SSE2-NEXT: packuswb %xmm1, %xmm0
+; SSE2-NEXT: packsswb %xmm1, %xmm0
; SSE2-NEXT: pcmpgtw %xmm7, %xmm3
-; SSE2-NEXT: pand %xmm5, %xmm3
; SSE2-NEXT: pcmpgtw %xmm6, %xmm2
-; SSE2-NEXT: pand %xmm5, %xmm2
-; SSE2-NEXT: packuswb %xmm3, %xmm2
+; SSE2-NEXT: packsswb %xmm3, %xmm2
; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al
; SSE2-NEXT: andb $1, %al
@@ -3410,48 +3405,27 @@ define <32 x i1> @test_cmp_v32i32(<32 x
; SSE2-LABEL: test_cmp_v32i32:
; SSE2: # BB#0:
; SSE2-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm3
-; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,2,2,3,4,5,6,7]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,6,6,7]
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
+; SSE2-NEXT: packssdw %xmm0, %xmm3
; SSE2-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm2
-; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7]
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
+; SSE2-NEXT: packssdw %xmm0, %xmm2
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255]
-; SSE2-NEXT: pand %xmm3, %xmm2
; SSE2-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm1
-; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7]
-; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
+; SSE2-NEXT: packssdw %xmm0, %xmm1
; SSE2-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm0
-; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE2-NEXT: packssdw %xmm0, %xmm0
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; SSE2-NEXT: pand %xmm3, %xmm0
-; SSE2-NEXT: packuswb %xmm2, %xmm0
+; SSE2-NEXT: packsswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm7
-; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm7[0,2,2,3,4,5,6,7]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7]
-; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
+; SSE2-NEXT: packssdw %xmm0, %xmm7
; SSE2-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm6
-; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm6[0,2,2,3,4,5,6,7]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7]
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
-; SSE2-NEXT: pand %xmm3, %xmm2
+; SSE2-NEXT: packssdw %xmm0, %xmm6
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm7[0]
; SSE2-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm5
-; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm5[0,2,2,3,4,5,6,7]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7]
-; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
+; SSE2-NEXT: packssdw %xmm0, %xmm5
; SSE2-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm4
-; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[0,2,2,3,4,5,6,7]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm4 = xmm4[0,1,2,3,4,6,6,7]
-; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm1[0]
-; SSE2-NEXT: pand %xmm3, %xmm4
-; SSE2-NEXT: packuswb %xmm2, %xmm4
+; SSE2-NEXT: packssdw %xmm0, %xmm4
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0]
+; SSE2-NEXT: packsswb %xmm6, %xmm4
; SSE2-NEXT: movdqa %xmm4, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al
; SSE2-NEXT: andb $1, %al
@@ -3555,105 +3529,119 @@ define <32 x i1> @test_cmp_v32i32(<32 x
;
; SSE42-LABEL: test_cmp_v32i32:
; SSE42: # BB#0:
-; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm0
-; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm1
-; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm2
; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm3
-; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm4
-; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm5
-; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm6
+; SSE42-NEXT: packssdw %xmm0, %xmm3
+; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm2
+; SSE42-NEXT: packssdw %xmm0, %xmm2
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
+; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm1
+; SSE42-NEXT: packssdw %xmm0, %xmm1
+; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm0
+; SSE42-NEXT: packssdw %xmm0, %xmm0
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE42-NEXT: packsswb %xmm2, %xmm0
; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm7
-; SSE42-NEXT: pextrb $12, %xmm7, %eax
+; SSE42-NEXT: packssdw %xmm0, %xmm7
+; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm6
+; SSE42-NEXT: packssdw %xmm0, %xmm6
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm7[0]
+; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm5
+; SSE42-NEXT: packssdw %xmm0, %xmm5
+; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm4
+; SSE42-NEXT: packssdw %xmm0, %xmm4
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0]
+; SSE42-NEXT: packsswb %xmm6, %xmm4
+; SSE42-NEXT: pextrb $15, %xmm4, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $8, %xmm7, %eax
+; SSE42-NEXT: pextrb $14, %xmm4, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $4, %xmm7, %eax
+; SSE42-NEXT: pextrb $13, %xmm4, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $0, %xmm7, %eax
+; SSE42-NEXT: pextrb $12, %xmm4, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $12, %xmm6, %eax
+; SSE42-NEXT: pextrb $11, %xmm4, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $8, %xmm6, %eax
+; SSE42-NEXT: pextrb $10, %xmm4, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $4, %xmm6, %eax
+; SSE42-NEXT: pextrb $9, %xmm4, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $0, %xmm6, %eax
+; SSE42-NEXT: pextrb $8, %xmm4, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $12, %xmm5, %eax
+; SSE42-NEXT: pextrb $7, %xmm4, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $8, %xmm5, %eax
+; SSE42-NEXT: pextrb $6, %xmm4, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $4, %xmm5, %eax
+; SSE42-NEXT: pextrb $5, %xmm4, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $0, %xmm5, %eax
+; SSE42-NEXT: pextrb $4, %xmm4, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $12, %xmm4, %eax
+; SSE42-NEXT: pextrb $3, %xmm4, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $8, %xmm4, %eax
+; SSE42-NEXT: pextrb $2, %xmm4, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $4, %xmm4, %eax
+; SSE42-NEXT: pextrb $1, %xmm4, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
; SSE42-NEXT: pextrb $0, %xmm4, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $12, %xmm3, %eax
+; SSE42-NEXT: pextrb $15, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $8, %xmm3, %eax
+; SSE42-NEXT: pextrb $14, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $4, %xmm3, %eax
+; SSE42-NEXT: pextrb $13, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $0, %xmm3, %eax
+; SSE42-NEXT: pextrb $12, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $12, %xmm2, %eax
+; SSE42-NEXT: pextrb $11, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $8, %xmm2, %eax
+; SSE42-NEXT: pextrb $10, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $4, %xmm2, %eax
+; SSE42-NEXT: pextrb $9, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $0, %xmm2, %eax
+; SSE42-NEXT: pextrb $8, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $12, %xmm1, %eax
+; SSE42-NEXT: pextrb $7, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $8, %xmm1, %eax
+; SSE42-NEXT: pextrb $6, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $4, %xmm1, %eax
+; SSE42-NEXT: pextrb $5, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $0, %xmm1, %eax
+; SSE42-NEXT: pextrb $4, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $12, %xmm0, %eax
+; SSE42-NEXT: pextrb $3, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $8, %xmm0, %eax
+; SSE42-NEXT: pextrb $2, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $4, %xmm0, %eax
+; SSE42-NEXT: pextrb $1, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
; SSE42-NEXT: pextrb $0, %xmm0, %eax
@@ -4365,26 +4353,17 @@ define <64 x i1> @test_cmp_v64i16(<64 x
; SSE2-LABEL: test_cmp_v64i16:
; SSE2: # BB#0:
; SSE2-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm1
-; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [255,255,255,255,255,255,255,255]
-; SSE2-NEXT: pand %xmm8, %xmm1
; SSE2-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm0
-; SSE2-NEXT: pand %xmm8, %xmm0
-; SSE2-NEXT: packuswb %xmm1, %xmm0
+; SSE2-NEXT: packsswb %xmm1, %xmm0
; SSE2-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm3
-; SSE2-NEXT: pand %xmm8, %xmm3
; SSE2-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm2
-; SSE2-NEXT: pand %xmm8, %xmm2
-; SSE2-NEXT: packuswb %xmm3, %xmm2
+; SSE2-NEXT: packsswb %xmm3, %xmm2
; SSE2-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm5
-; SSE2-NEXT: pand %xmm8, %xmm5
; SSE2-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm4
-; SSE2-NEXT: pand %xmm8, %xmm4
-; SSE2-NEXT: packuswb %xmm5, %xmm4
+; SSE2-NEXT: packsswb %xmm5, %xmm4
; SSE2-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm7
-; SSE2-NEXT: pand %xmm8, %xmm7
; SSE2-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm6
-; SSE2-NEXT: pand %xmm8, %xmm6
-; SSE2-NEXT: packuswb %xmm7, %xmm6
+; SSE2-NEXT: packsswb %xmm7, %xmm6
; SSE2-NEXT: movdqa %xmm6, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al
; SSE2-NEXT: andb $1, %al
@@ -9358,121 +9337,155 @@ define <32 x i1> @test_cmp_v32i64(<32 x
;
; SSE42-LABEL: test_cmp_v32i64:
; SSE42: # BB#0:
-; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm15
-; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm14
-; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm13
-; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm12
-; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11
; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10
; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
+; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11
; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
-; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm0
-; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm1
-; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm2
-; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm3
-; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm4
-; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm5
-; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm6
+; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm14
+; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm13
+; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm15
+; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm12
; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm7
-; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm8
-; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm9
-; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm10
-; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm11
+; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm6
+; SSE42-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,2],xmm7[0,2]
+; SSE42-NEXT: movdqa {{.*#+}} xmm7 = [0,1,4,5,4,5,6,7,0,1,4,5,8,9,12,13]
+; SSE42-NEXT: pshufb %xmm7, %xmm6
+; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm5
+; SSE42-NEXT: pshufd {{.*#+}} xmm5 = xmm5[0,2,2,3]
+; SSE42-NEXT: pshuflw {{.*#+}} xmm5 = xmm5[0,2,2,3,4,5,6,7]
+; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm4
+; SSE42-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
+; SSE42-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[0,2,2,3,4,5,6,7]
+; SSE42-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
+; SSE42-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1,2,3],xmm6[4,5,6,7]
+; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm3
+; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm2
+; SSE42-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm3[0,2]
+; SSE42-NEXT: pshufb %xmm7, %xmm2
+; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm1
+; SSE42-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
+; SSE42-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
+; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm0
+; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE42-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
+; SSE42-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE42-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
+; SSE42-NEXT: packsswb %xmm4, %xmm0
; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm12
+; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [0,1,8,9,2,3,10,11,8,9,12,13,10,11,14,15]
+; SSE42-NEXT: pshufb %xmm1, %xmm12
+; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm15
; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm13
+; SSE42-NEXT: shufps {{.*#+}} xmm13 = xmm13[0,2],xmm15[0,2]
+; SSE42-NEXT: pshufb %xmm7, %xmm13
; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm14
-; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm15
-; SSE42-NEXT: pextrb $8, %xmm15, %eax
+; SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm14[0,2,2,3]
+; SSE42-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,1,0,2,4,5,6,7]
+; SSE42-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm13[4,5,6,7]
+; SSE42-NEXT: pblendw {{.*#+}} xmm2 = xmm12[0,1],xmm2[2,3,4,5,6,7]
+; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm8
+; SSE42-NEXT: pshufb %xmm1, %xmm8
+; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm11
+; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm9
+; SSE42-NEXT: shufps {{.*#+}} xmm9 = xmm9[0,2],xmm11[0,2]
+; SSE42-NEXT: pshufb %xmm7, %xmm9
+; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm10
+; SSE42-NEXT: pshufd {{.*#+}} xmm1 = xmm10[0,2,2,3]
+; SSE42-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,0,2,4,5,6,7]
+; SSE42-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm9[4,5,6,7]
+; SSE42-NEXT: pblendw {{.*#+}} xmm1 = xmm8[0,1],xmm1[2,3,4,5,6,7]
+; SSE42-NEXT: packsswb %xmm2, %xmm1
+; SSE42-NEXT: pextrb $15, %xmm1, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $0, %xmm15, %eax
+; SSE42-NEXT: pextrb $14, %xmm1, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $8, %xmm14, %eax
+; SSE42-NEXT: pextrb $13, %xmm1, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $0, %xmm14, %eax
+; SSE42-NEXT: pextrb $12, %xmm1, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $8, %xmm13, %eax
+; SSE42-NEXT: pextrb $11, %xmm1, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $0, %xmm13, %eax
+; SSE42-NEXT: pextrb $10, %xmm1, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $8, %xmm12, %eax
+; SSE42-NEXT: pextrb $9, %xmm1, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $0, %xmm12, %eax
+; SSE42-NEXT: pextrb $8, %xmm1, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $8, %xmm11, %eax
+; SSE42-NEXT: pextrb $7, %xmm1, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $0, %xmm11, %eax
+; SSE42-NEXT: pextrb $6, %xmm1, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $8, %xmm10, %eax
+; SSE42-NEXT: pextrb $5, %xmm1, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $0, %xmm10, %eax
+; SSE42-NEXT: pextrb $4, %xmm1, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $8, %xmm9, %eax
+; SSE42-NEXT: pextrb $3, %xmm1, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $0, %xmm9, %eax
+; SSE42-NEXT: pextrb $2, %xmm1, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $8, %xmm8, %eax
+; SSE42-NEXT: pextrb $1, %xmm1, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $0, %xmm8, %eax
+; SSE42-NEXT: pextrb $0, %xmm1, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, 2(%rdi)
-; SSE42-NEXT: pextrb $8, %xmm7, %eax
+; SSE42-NEXT: pextrb $15, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $0, %xmm7, %eax
+; SSE42-NEXT: pextrb $14, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $8, %xmm6, %eax
+; SSE42-NEXT: pextrb $13, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $0, %xmm6, %eax
+; SSE42-NEXT: pextrb $12, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $8, %xmm5, %eax
+; SSE42-NEXT: pextrb $11, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $0, %xmm5, %eax
+; SSE42-NEXT: pextrb $10, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $8, %xmm4, %eax
+; SSE42-NEXT: pextrb $9, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $0, %xmm4, %eax
+; SSE42-NEXT: pextrb $8, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $8, %xmm3, %eax
+; SSE42-NEXT: pextrb $7, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $0, %xmm3, %eax
+; SSE42-NEXT: pextrb $6, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $8, %xmm2, %eax
+; SSE42-NEXT: pextrb $5, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $0, %xmm2, %eax
+; SSE42-NEXT: pextrb $4, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $8, %xmm1, %eax
+; SSE42-NEXT: pextrb $3, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $0, %xmm1, %eax
+; SSE42-NEXT: pextrb $2, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
-; SSE42-NEXT: pextrb $8, %xmm0, %eax
+; SSE42-NEXT: pextrb $1, %xmm0, %eax
; SSE42-NEXT: andb $1, %al
; SSE42-NEXT: movb %al, (%rdi)
; SSE42-NEXT: pextrb $0, %xmm0, %eax
Modified: llvm/trunk/test/CodeGen/X86/vector-shift-ashr-128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shift-ashr-128.ll?rev=314788&r1=314787&r2=314788&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-shift-ashr-128.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector-shift-ashr-128.ll Tue Oct 3 05:01:31 2017
@@ -320,7 +320,7 @@ define <8 x i16> @var_shift_v8i16(<8 x i
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0
; AVX2-NEXT: vpsravd %ymm1, %ymm0, %ymm0
-; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
+; AVX2-NEXT: vpackssdw %ymm0, %ymm0, %ymm0
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX2-NEXT: vzeroupper
@@ -1253,7 +1253,7 @@ define <8 x i16> @constant_shift_v8i16(<
; AVX2: # BB#0:
; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0
; AVX2-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0
-; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
+; AVX2-NEXT: vpackssdw %ymm0, %ymm0, %ymm0
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX2-NEXT: vzeroupper
Modified: llvm/trunk/test/CodeGen/X86/vector-trunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-trunc.ll?rev=314788&r1=314787&r2=314788&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-trunc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector-trunc.ll Tue Oct 3 05:01:31 2017
@@ -398,9 +398,8 @@ define <8 x i16> @trunc8i32_8i16_ashr(<8
; SSSE3: # BB#0: # %entry
; SSSE3-NEXT: psrad $16, %xmm0
; SSSE3-NEXT: psrad $16, %xmm1
-; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
-; SSSE3-NEXT: pshufb %xmm2, %xmm1
-; SSSE3-NEXT: pshufb %xmm2, %xmm0
+; SSSE3-NEXT: packssdw %xmm0, %xmm1
+; SSSE3-NEXT: packssdw %xmm0, %xmm0
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSSE3-NEXT: retq
;
@@ -408,9 +407,8 @@ define <8 x i16> @trunc8i32_8i16_ashr(<8
; SSE41: # BB#0: # %entry
; SSE41-NEXT: psrad $16, %xmm0
; SSE41-NEXT: psrad $16, %xmm1
-; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
-; SSE41-NEXT: pshufb %xmm2, %xmm1
-; SSE41-NEXT: pshufb %xmm2, %xmm0
+; SSE41-NEXT: packssdw %xmm0, %xmm1
+; SSE41-NEXT: packssdw %xmm0, %xmm0
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE41-NEXT: retq
;
@@ -419,9 +417,8 @@ define <8 x i16> @trunc8i32_8i16_ashr(<8
; AVX1-NEXT: vpsrad $16, %xmm0, %xmm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpsrad $16, %xmm0, %xmm0
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
-; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
+; AVX1-NEXT: vpackssdw %xmm0, %xmm0, %xmm0
+; AVX1-NEXT: vpackssdw %xmm0, %xmm1, %xmm1
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
@@ -429,7 +426,7 @@ define <8 x i16> @trunc8i32_8i16_ashr(<8
; AVX2-LABEL: trunc8i32_8i16_ashr:
; AVX2: # BB#0: # %entry
; AVX2-NEXT: vpsrad $16, %ymm0, %ymm0
-; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
+; AVX2-NEXT: vpackssdw %ymm0, %ymm0, %ymm0
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX2-NEXT: vzeroupper
@@ -492,25 +489,26 @@ define <8 x i16> @trunc8i32_8i16_lshr(<8
;
; SSE41-LABEL: trunc8i32_8i16_lshr:
; SSE41: # BB#0: # %entry
-; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [2,3,6,7,10,11,14,15,10,11,14,15,14,15,255,255]
-; SSE41-NEXT: pshufb %xmm2, %xmm1
-; SSE41-NEXT: pshufb %xmm2, %xmm0
+; SSE41-NEXT: psrld $16, %xmm0
+; SSE41-NEXT: psrld $16, %xmm1
+; SSE41-NEXT: packusdw %xmm0, %xmm1
+; SSE41-NEXT: packusdw %xmm0, %xmm0
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE41-NEXT: retq
;
; AVX1-LABEL: trunc8i32_8i16_lshr:
; AVX1: # BB#0: # %entry
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [2,3,6,7,10,11,14,15,10,11,14,15,14,15,255,255]
-; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX1-NEXT: vpsrld $16, %xmm1, %xmm1
+; AVX1-NEXT: vpsrld $16, %xmm0, %xmm0
+; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: trunc8i32_8i16_lshr:
; AVX2: # BB#0: # %entry
-; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[2,3,6,7,10,11,14,15,10,11,14,15,14,15],zero,zero,ymm0[18,19,22,23,26,27,30,31,26,27,30,31,30,31],zero,zero
+; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0
+; AVX2-NEXT: vpackusdw %ymm0, %ymm0, %ymm0
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
; AVX2-NEXT: vzeroupper
@@ -786,10 +784,9 @@ define void @trunc16i32_16i16_ashr(<16 x
; AVX2: # BB#0: # %entry
; AVX2-NEXT: vpsrad $16, %ymm1, %ymm1
; AVX2-NEXT: vpsrad $16, %ymm0, %ymm0
-; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
-; AVX2-NEXT: vpshufb %ymm2, %ymm0, %ymm0
+; AVX2-NEXT: vpackssdw %ymm0, %ymm0, %ymm0
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
-; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpackssdw %ymm0, %ymm1, %ymm1
; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: vmovdqu %ymm0, (%rax)
@@ -879,10 +876,11 @@ define void @trunc16i32_16i16_lshr(<16 x
;
; AVX2-LABEL: trunc16i32_16i16_lshr:
; AVX2: # BB#0: # %entry
-; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [2,3,6,7,10,11,14,15,10,11,14,15,14,15,255,255,18,19,22,23,26,27,30,31,26,27,30,31,30,31,255,255]
-; AVX2-NEXT: vpshufb %ymm2, %ymm0, %ymm0
+; AVX2-NEXT: vpsrld $16, %ymm1, %ymm1
+; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0
+; AVX2-NEXT: vpackusdw %ymm0, %ymm0, %ymm0
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
-; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpackusdw %ymm0, %ymm1, %ymm1
; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: vmovdqu %ymm0, (%rax)
@@ -1000,14 +998,13 @@ define void @trunc16i32_16i8_ashr(<16 x
; AVX2: # BB#0: # %entry
; AVX2-NEXT: vpsrad $24, %ymm0, %ymm0
; AVX2-NEXT: vpsrad $24, %ymm1, %ymm1
-; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
-; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpackssdw %ymm0, %ymm1, %ymm1
; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
-; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
-; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm1
-; AVX2-NEXT: vpshufb %ymm2, %ymm0, %ymm0
+; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
+; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1
+; AVX2-NEXT: vpackssdw %ymm0, %ymm0, %ymm0
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
-; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0
+; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX2-NEXT: vmovdqu %xmm0, (%rax)
; AVX2-NEXT: vzeroupper
@@ -1056,14 +1053,15 @@ define void @trunc16i32_16i8_lshr(<16 x
;
; AVX2-LABEL: trunc16i32_16i8_lshr:
; AVX2: # BB#0: # %entry
-; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [3,255,7,255,11,255,15,255,11,255,15,255,15,255,255,255,19,255,23,255,27,255,31,255,27,255,31,255,31,255,255,255]
-; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpsrld $24, %ymm0, %ymm0
+; AVX2-NEXT: vpsrld $24, %ymm1, %ymm1
+; AVX2-NEXT: vpackssdw %ymm0, %ymm1, %ymm1
; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
-; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
-; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm1
-; AVX2-NEXT: vpshufb %ymm2, %ymm0, %ymm0
+; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
+; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1
+; AVX2-NEXT: vpackssdw %ymm0, %ymm0, %ymm0
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
-; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0
+; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX2-NEXT: vmovdqu %xmm0, (%rax)
; AVX2-NEXT: vzeroupper
@@ -1169,38 +1167,13 @@ entry:
}
define void @trunc16i16_16i8_ashr(<16 x i16> %a) {
-; SSE2-LABEL: trunc16i16_16i8_ashr:
-; SSE2: # BB#0: # %entry
-; SSE2-NEXT: psraw $8, %xmm0
-; SSE2-NEXT: psraw $8, %xmm1
-; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
-; SSE2-NEXT: pand %xmm2, %xmm1
-; SSE2-NEXT: pand %xmm2, %xmm0
-; SSE2-NEXT: packuswb %xmm1, %xmm0
-; SSE2-NEXT: movdqu %xmm0, (%rax)
-; SSE2-NEXT: retq
-;
-; SSSE3-LABEL: trunc16i16_16i8_ashr:
-; SSSE3: # BB#0: # %entry
-; SSSE3-NEXT: psraw $8, %xmm0
-; SSSE3-NEXT: psraw $8, %xmm1
-; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
-; SSSE3-NEXT: pshufb %xmm2, %xmm1
-; SSSE3-NEXT: pshufb %xmm2, %xmm0
-; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; SSSE3-NEXT: movdqu %xmm0, (%rax)
-; SSSE3-NEXT: retq
-;
-; SSE41-LABEL: trunc16i16_16i8_ashr:
-; SSE41: # BB#0: # %entry
-; SSE41-NEXT: psraw $8, %xmm0
-; SSE41-NEXT: psraw $8, %xmm1
-; SSE41-NEXT: movdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
-; SSE41-NEXT: pshufb %xmm2, %xmm1
-; SSE41-NEXT: pshufb %xmm2, %xmm0
-; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; SSE41-NEXT: movdqu %xmm0, (%rax)
-; SSE41-NEXT: retq
+; SSE-LABEL: trunc16i16_16i8_ashr:
+; SSE: # BB#0: # %entry
+; SSE-NEXT: psraw $8, %xmm1
+; SSE-NEXT: psraw $8, %xmm0
+; SSE-NEXT: packsswb %xmm1, %xmm0
+; SSE-NEXT: movdqu %xmm0, (%rax)
+; SSE-NEXT: retq
;
; AVX1-LABEL: trunc16i16_16i8_ashr:
; AVX1: # BB#0: # %entry
@@ -1267,31 +1240,13 @@ entry:
}
define void @trunc16i16_16i8_lshr(<16 x i16> %a) {
-; SSE2-LABEL: trunc16i16_16i8_lshr:
-; SSE2: # BB#0: # %entry
-; SSE2-NEXT: psrlw $8, %xmm1
-; SSE2-NEXT: psrlw $8, %xmm0
-; SSE2-NEXT: packuswb %xmm1, %xmm0
-; SSE2-NEXT: movdqu %xmm0, (%rax)
-; SSE2-NEXT: retq
-;
-; SSSE3-LABEL: trunc16i16_16i8_lshr:
-; SSSE3: # BB#0: # %entry
-; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = <1,3,5,7,9,11,13,15,u,u,u,u,u,u,u,u>
-; SSSE3-NEXT: pshufb %xmm2, %xmm1
-; SSSE3-NEXT: pshufb %xmm2, %xmm0
-; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; SSSE3-NEXT: movdqu %xmm0, (%rax)
-; SSSE3-NEXT: retq
-;
-; SSE41-LABEL: trunc16i16_16i8_lshr:
-; SSE41: # BB#0: # %entry
-; SSE41-NEXT: movdqa {{.*#+}} xmm2 = <1,3,5,7,9,11,13,15,u,u,u,u,u,u,u,u>
-; SSE41-NEXT: pshufb %xmm2, %xmm1
-; SSE41-NEXT: pshufb %xmm2, %xmm0
-; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; SSE41-NEXT: movdqu %xmm0, (%rax)
-; SSE41-NEXT: retq
+; SSE-LABEL: trunc16i16_16i8_lshr:
+; SSE: # BB#0: # %entry
+; SSE-NEXT: psrlw $8, %xmm1
+; SSE-NEXT: psrlw $8, %xmm0
+; SSE-NEXT: packuswb %xmm1, %xmm0
+; SSE-NEXT: movdqu %xmm0, (%rax)
+; SSE-NEXT: retq
;
; AVX1-LABEL: trunc16i16_16i8_lshr:
; AVX1: # BB#0: # %entry
@@ -1308,10 +1263,7 @@ define void @trunc16i16_16i8_lshr(<16 x
; AVX2: # BB#0: # %entry
; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
-; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1
-; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm0
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX2-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vmovdqu %xmm0, (%rax)
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
Modified: llvm/trunk/test/CodeGen/X86/vselect-avx.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vselect-avx.ll?rev=314788&r1=314787&r2=314788&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vselect-avx.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vselect-avx.ll Tue Oct 3 05:01:31 2017
@@ -99,10 +99,9 @@ define void @test3(<4 x i32> %induction3
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX1-NEXT: vpcmpeqd %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm1
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
-; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vpackssdw %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vmovq %xmm0, (%rdi)
-; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm0
+; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm1[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; AVX1-NEXT: vmovq %xmm0, (%rsi)
; AVX1-NEXT: retq
;
@@ -123,10 +122,9 @@ define void @test3(<4 x i32> %induction3
; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX2-NEXT: vpcmpeqd %xmm3, %xmm0, %xmm0
; AVX2-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm1
-; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
-; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm0
+; AVX2-NEXT: vpackssdw %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vmovq %xmm0, (%rdi)
-; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm0
+; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm1[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; AVX2-NEXT: vmovq %xmm0, (%rsi)
; AVX2-NEXT: retq
%tmp6 = srem <4 x i32> %induction30, <i32 3, i32 3, i32 3, i32 3>
Modified: llvm/trunk/test/CodeGen/X86/widen_arith-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-2.ll?rev=314788&r1=314787&r2=314788&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/widen_arith-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/widen_arith-2.ll Tue Oct 3 05:01:31 2017
@@ -10,7 +10,6 @@ define void @update(i64* %dst_i, i64* %s
; CHECK-NEXT: movl $0, (%esp)
; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [4,4,4,4,4,4,4,4]
-; CHECK-NEXT: movdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
; CHECK-NEXT: jmp .LBB0_1
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_2: # %forbody
@@ -22,11 +21,11 @@ define void @update(i64* %dst_i, i64* %s
; CHECK-NEXT: movl %edx, {{[0-9]+}}(%esp)
; CHECK-NEXT: addl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; CHECK-NEXT: pmovzxbw {{.*#+}} xmm3 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
-; CHECK-NEXT: psubw %xmm0, %xmm3
-; CHECK-NEXT: pand %xmm1, %xmm3
-; CHECK-NEXT: pshufb %xmm2, %xmm3
-; CHECK-NEXT: movq %xmm3, (%edx,%eax,8)
+; CHECK-NEXT: pmovzxbw {{.*#+}} xmm2 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
+; CHECK-NEXT: psubw %xmm0, %xmm2
+; CHECK-NEXT: pand %xmm1, %xmm2
+; CHECK-NEXT: packsswb %xmm0, %xmm2
+; CHECK-NEXT: movq %xmm2, (%edx,%eax,8)
; CHECK-NEXT: incl (%esp)
; CHECK-NEXT: .LBB0_1: # %forcond
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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