[PATCH] D38472: [X86][SSE] Add support for lowering shuffles to PACKSS/PACKUS

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.

If the upper bits of a truncation shuffle patterns have at least the minimum number of sign/zero bits on their inputs then we can safely use PACKSS/PACKUS as shuffles.

Partial fix for https://bugs.llvm.org/show_bug.cgi?id=34773


Repository:
  rL LLVM

https://reviews.llvm.org/D38472

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/avx-cvt-2.ll
  test/CodeGen/X86/avx2-intrinsics-x86.ll
  test/CodeGen/X86/avx2-shift.ll
  test/CodeGen/X86/avx2-vbroadcast.ll
  test/CodeGen/X86/avx2-vector-shifts.ll
  test/CodeGen/X86/avx512-any_extend_load.ll
  test/CodeGen/X86/avx512-trunc.ll
  test/CodeGen/X86/bitcast-and-setcc-256.ll
  test/CodeGen/X86/bitcast-and-setcc-512.ll
  test/CodeGen/X86/bitcast-setcc-128.ll
  test/CodeGen/X86/psubus.ll
  test/CodeGen/X86/shuffle-strided-with-offset-256.ll
  test/CodeGen/X86/sse2-intrinsics-x86.ll
  test/CodeGen/X86/sse41-intrinsics-x86.ll
  test/CodeGen/X86/vector-compare-results.ll
  test/CodeGen/X86/vector-shift-ashr-128.ll
  test/CodeGen/X86/vector-trunc.ll
  test/CodeGen/X86/vselect-avx.ll
  test/CodeGen/X86/widen_arith-2.ll

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