[PATCH] D38454: [mips] Place certain 64 bit FPU instructions in their own decoder namespace

[Simon Dardis via Phabricator via llvm-commits]

sdardis created this revision.
Herald added a subscriber: arichardson.

Previously, instructions that were defined to use the FGR64 register class
were associated with the Mips64 table which was incorrect.


Repository:
  rL LLVM

https://reviews.llvm.org/D38454

Files:
  lib/Target/Mips/Disassembler/MipsDisassembler.cpp
  lib/Target/Mips/MicroMips32r6InstrInfo.td
  lib/Target/Mips/MipsCondMov.td
  lib/Target/Mips/MipsInstrFPU.td
  test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt
  test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
  test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt
  test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
  test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt
  test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt

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