[llvm] r314641 - [Hexagon] Patch to Extract i1 element from vector of i1

[Ron Lieberman via llvm-commits]

Author: ronl
Date: Sun Oct  1 17:16:15 2017
New Revision: 314641

URL: http://llvm.org/viewvc/llvm-project?rev=314641&view=rev
Log:
[Hexagon] Patch to Extract i1 element from vector of i1

This patch extracts 1 element from vector consisting
of elements of size 1 bit at given index.



Added:
    llvm/trunk/test/CodeGen/Hexagon/vect/vect-extract-i1.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=314641&r1=314640&r2=314641&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Sun Oct  1 17:16:15 2017
@@ -2750,7 +2750,13 @@ HexagonTargetLowering::LowerEXTRACT_VECT
     MVT SVT = VecVT.getSimpleVT();
     uint64_t W = CW->getZExtValue();
 
-    if (W == 32) {
+    if (W == 1) {
+      MVT LocVT = MVT::getIntegerVT(SVT.getSizeInBits());
+      SDValue VecCast = DAG.getNode(ISD::BITCAST, dl, LocVT, Vec);
+      SDValue Shifted = DAG.getNode(ISD::SRA, dl, LocVT, VecCast, Offset);
+      return DAG.getNode(ISD::AND, dl, LocVT, Shifted,
+                         DAG.getConstant(1, dl, LocVT));
+    } else if (W == 32) {
       // Translate this node into EXTRACT_SUBREG.
       unsigned Subreg = (X == 0) ? Hexagon::isub_lo : 0;
 

Added: llvm/trunk/test/CodeGen/Hexagon/vect/vect-extract-i1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/vect/vect-extract-i1.ll?rev=314641&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/vect/vect-extract-i1.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/vect/vect-extract-i1.ll Sun Oct  1 17:16:15 2017
@@ -0,0 +1,9 @@
+; RUN: llc -march=hexagon < %s
+
+define i1 @t_i4x8(<4 x i8> %a, <4 x i8> %b) nounwind {
+entry:
+	%0 = add <4 x i8> %a, %b
+        %1 = bitcast <4 x i8> %0 to <32 x i1>
+        %2 = extractelement <32 x i1> %1, i32 0
+	ret i1 %2
+}