[llvm] r314639 - [X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMem
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 1 16:53:53 PDT 2017
Author: ctopper
Date: Sun Oct 1 16:53:53 2017
New Revision: 314639
URL: http://llvm.org/viewvc/llvm-project?rev=314639&view=rev
Log:
[X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMem
Summary:
Intel documentation shows the memory operand as the first operand. But we currently treat it as the second operand. Conceptually the order doesn't matter since it doesn't write memory. We have aliases to parse with the operands in either order and the isel matching is commutable.
For the register®ister form order does matter for the assembly parser. PR22995 was previously filed and fixed by changing the register®ister form from MRMSrcReg to MRMDestReg to match gas. Ideally the memory form should match by using MRMDestMem.
I believe this supercedes D38025 which was trying to switch the register®ister form back to pre-PR22995.
Reviewers: aymanmus, RKSimon, zvi
Reviewed By: aymanmus
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38120
Modified:
llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/lib/Target/X86/X86MacroFusion.cpp
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/test/CodeGen/X86/absolute-bit-mask.ll
llvm/trunk/test/CodeGen/X86/post-ra-sched-with-debug.mir
llvm/trunk/test/CodeGen/X86/testl-commute.ll
llvm/trunk/test/MC/Disassembler/X86/x86-16.txt
llvm/trunk/test/MC/X86/intel-syntax.s
llvm/trunk/test/MC/X86/x86-16.s
llvm/trunk/test/MC/X86/x86-32.s
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp?rev=314639&r1=314638&r2=314639&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp Sun Oct 1 16:53:53 2017
@@ -380,7 +380,7 @@ void X86MCCodeEmitter::emitMemModRMByte(
return X86::reloc_riprel_4byte_movq_load;
case X86::CALL64m:
case X86::JMP64m:
- case X86::TEST64rm:
+ case X86::TEST64mr:
case X86::ADC64rm:
case X86::ADD64rm:
case X86::AND64rm:
Modified: llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrArithmetic.td?rev=314639&r1=314638&r2=314639&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrArithmetic.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrArithmetic.td Sun Oct 1 16:53:53 2017
@@ -652,9 +652,8 @@ class ITy<bits<8> opcode, Format f, X86T
// BinOpRR - Instructions like "add reg, reg, reg".
class BinOpRR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
- dag outlist, list<dag> pattern, InstrItinClass itin,
- Format f = MRMDestReg>
- : ITy<opcode, f, typeinfo, outlist,
+ dag outlist, list<dag> pattern, InstrItinClass itin>
+ : ITy<opcode, MRMDestReg, typeinfo, outlist,
(ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
mnemonic, "{$src2, $src1|$src1, $src2}", pattern, itin>,
Sched<[WriteALU]>;
@@ -662,11 +661,11 @@ class BinOpRR<bits<8> opcode, string mne
// BinOpRR_F - Instructions like "cmp reg, Reg", where the pattern has
// just a EFLAGS as a result.
class BinOpRR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
- SDPatternOperator opnode, Format f = MRMDestReg>
+ SDPatternOperator opnode>
: BinOpRR<opcode, mnemonic, typeinfo, (outs),
[(set EFLAGS,
(opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
- IIC_BIN_NONMEM, f>;
+ IIC_BIN_NONMEM>;
// BinOpRR_RF - Instructions like "add reg, reg, reg", where the pattern has
// both a regclass and EFLAGS as a result.
@@ -727,7 +726,7 @@ class BinOpRM<bits<8> opcode, string mne
// BinOpRM_F - Instructions like "cmp reg, [mem]".
class BinOpRM_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
- SDPatternOperator opnode>
+ SDNode opnode>
: BinOpRM<opcode, mnemonic, typeinfo, (outs),
[(set EFLAGS,
(opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
@@ -837,7 +836,7 @@ class BinOpMR_RMW_FF<bits<8> opcode, str
// BinOpMR_F - Instructions like "cmp [mem], reg".
class BinOpMR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
- SDNode opnode>
+ SDPatternOperator opnode>
: BinOpMR<opcode, mnemonic, typeinfo,
[(set EFLAGS, (opnode (load addr:$dst), typeinfo.RegClass:$src))]>;
@@ -1224,10 +1223,10 @@ let isCompare = 1 in {
def TEST64rr : BinOpRR_F<0x84, "test", Xi64, X86testpat>;
} // isCommutable
- def TEST8rm : BinOpRM_F<0x84, "test", Xi8 , X86testpat>;
- def TEST16rm : BinOpRM_F<0x84, "test", Xi16, X86testpat>;
- def TEST32rm : BinOpRM_F<0x84, "test", Xi32, X86testpat>;
- def TEST64rm : BinOpRM_F<0x84, "test", Xi64, X86testpat>;
+ def TEST8mr : BinOpMR_F<0x84, "test", Xi8 , X86testpat>;
+ def TEST16mr : BinOpMR_F<0x84, "test", Xi16, X86testpat>;
+ def TEST32mr : BinOpMR_F<0x84, "test", Xi32, X86testpat>;
+ def TEST64mr : BinOpMR_F<0x84, "test", Xi64, X86testpat>;
def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>;
def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>;
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=314639&r1=314638&r2=314639&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sun Oct 1 16:53:53 2017
@@ -375,9 +375,13 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
{ X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
{ X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
+ { X86::TEST16rr, X86::TEST16mr, TB_FOLDED_LOAD },
{ X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
+ { X86::TEST32rr, X86::TEST32mr, TB_FOLDED_LOAD },
{ X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
+ { X86::TEST64rr, X86::TEST64mr, TB_FOLDED_LOAD },
{ X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
+ { X86::TEST8rr, X86::TEST8mr, TB_FOLDED_LOAD },
// AVX 128-bit versions of foldable instructions
{ X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
@@ -608,10 +612,6 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::SQRTSDr_Int, X86::SQRTSDm_Int, TB_NO_REVERSE },
{ X86::SQRTSSr, X86::SQRTSSm, 0 },
{ X86::SQRTSSr_Int, X86::SQRTSSm_Int, TB_NO_REVERSE },
- { X86::TEST16rr, X86::TEST16rm, 0 },
- { X86::TEST32rr, X86::TEST32rm, 0 },
- { X86::TEST64rr, X86::TEST64rm, 0 },
- { X86::TEST8rr, X86::TEST8rm, 0 },
// FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
{ X86::UCOMISDrr, X86::UCOMISDrm, 0 },
{ X86::UCOMISSrr, X86::UCOMISSrm, 0 },
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=314639&r1=314638&r2=314639&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sun Oct 1 16:53:53 2017
@@ -3236,14 +3236,14 @@ defm : ShiftRotateByOneAlias<"ror", "ROR
FIXME */
// test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
-def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}",
- (TEST8rm GR8 :$val, i8mem :$mem), 0>;
-def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}",
- (TEST16rm GR16:$val, i16mem:$mem), 0>;
-def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}",
- (TEST32rm GR32:$val, i32mem:$mem), 0>;
-def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}",
- (TEST64rm GR64:$val, i64mem:$mem), 0>;
+def : InstAlias<"test{b}\t{$mem, $val|$val, $mem}",
+ (TEST8mr i8mem :$mem, GR8 :$val), 0>;
+def : InstAlias<"test{w}\t{$mem, $val|$val, $mem}",
+ (TEST16mr i16mem:$mem, GR16:$val), 0>;
+def : InstAlias<"test{l}\t{$mem, $val|$val, $mem}",
+ (TEST32mr i32mem:$mem, GR32:$val), 0>;
+def : InstAlias<"test{q}\t{$mem, $val|$val, $mem}",
+ (TEST64mr i64mem:$mem, GR64:$val), 0>;
// xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}",
Modified: llvm/trunk/lib/Target/X86/X86MacroFusion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MacroFusion.cpp?rev=314639&r1=314638&r2=314639&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MacroFusion.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MacroFusion.cpp Sun Oct 1 16:53:53 2017
@@ -82,10 +82,10 @@ static bool shouldScheduleAdjacent(const
case X86::TEST32i32:
case X86::TEST64i32:
case X86::TEST64ri32:
- case X86::TEST8rm:
- case X86::TEST16rm:
- case X86::TEST32rm:
- case X86::TEST64rm:
+ case X86::TEST8mr:
+ case X86::TEST16mr:
+ case X86::TEST32mr:
+ case X86::TEST64mr:
case X86::TEST8ri_NOREX:
case X86::AND16i16:
case X86::AND16ri:
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=314639&r1=314638&r2=314639&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Sun Oct 1 16:53:53 2017
@@ -2099,9 +2099,9 @@ def: InstRW<[HWWriteResGroup18], (instre
def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)r(mr?)")>;
def: InstRW<[HWWriteResGroup18], (instregex "SUB(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "SUB8rm")>;
-def: InstRW<[HWWriteResGroup18], (instregex "TEST(16|32|64)rm")>;
+def: InstRW<[HWWriteResGroup18], (instregex "TEST(16|32|64)mr")>;
def: InstRW<[HWWriteResGroup18], (instregex "TEST8mi")>;
-def: InstRW<[HWWriteResGroup18], (instregex "TEST8rm")>;
+def: InstRW<[HWWriteResGroup18], (instregex "TEST8mr")>;
def: InstRW<[HWWriteResGroup18], (instregex "XOR(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "XOR8rm")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=314639&r1=314638&r2=314639&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Sun Oct 1 16:53:53 2017
@@ -2010,9 +2010,9 @@ def: InstRW<[SBWriteResGroup70], (instre
def: InstRW<[SBWriteResGroup70], (instregex "SUB(16|32|64)mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "SUB8mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "SUB8mr")>;
-def: InstRW<[SBWriteResGroup70], (instregex "TEST(16|32|64)rm")>;
+def: InstRW<[SBWriteResGroup70], (instregex "TEST(16|32|64)mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "TEST8mi")>;
-def: InstRW<[SBWriteResGroup70], (instregex "TEST8rm")>;
+def: InstRW<[SBWriteResGroup70], (instregex "TEST8mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "XOR(16|32|64)mi8")>;
def: InstRW<[SBWriteResGroup70], (instregex "XOR(16|32|64)mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "XOR8mi")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=314639&r1=314638&r2=314639&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Sun Oct 1 16:53:53 2017
@@ -1634,9 +1634,9 @@ def: InstRW<[SKLWriteResGroup21], (instr
def: InstRW<[SKLWriteResGroup21], (instregex "POP(16|32|64)r(mr?)")>;
def: InstRW<[SKLWriteResGroup21], (instregex "SUB(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup21], (instregex "SUB8rm")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "TEST(16|32|64)rm")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "TEST(16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup21], (instregex "TEST8mi")>;
-def: InstRW<[SKLWriteResGroup21], (instregex "TEST8rm")>;
+def: InstRW<[SKLWriteResGroup21], (instregex "TEST8mr")>;
def: InstRW<[SKLWriteResGroup21], (instregex "XOR(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup21], (instregex "XOR8rm")>;
Modified: llvm/trunk/test/CodeGen/X86/absolute-bit-mask.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/absolute-bit-mask.ll?rev=314639&r1=314638&r2=314639&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/absolute-bit-mask.ll (original)
+++ llvm/trunk/test/CodeGen/X86/absolute-bit-mask.ll Sun Oct 1 16:53:53 2017
@@ -43,7 +43,7 @@ f:
define void @foo64(i64* %ptr) {
%load = load i64, i64* %ptr
; CHECK: movabsq $bit_mask64, %rax
- ; CHECK: testq (%rdi), %rax
+ ; CHECK: testq %rax, (%rdi)
%and = and i64 %load, ptrtoint (i8* @bit_mask64 to i64)
%icmp = icmp eq i64 %and, 0
br i1 %icmp, label %t, label %f
Modified: llvm/trunk/test/CodeGen/X86/post-ra-sched-with-debug.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/post-ra-sched-with-debug.mir?rev=314639&r1=314638&r2=314639&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/post-ra-sched-with-debug.mir (original)
+++ llvm/trunk/test/CodeGen/X86/post-ra-sched-with-debug.mir Sun Oct 1 16:53:53 2017
@@ -292,7 +292,7 @@ body: |
%rcx = CMOVNE64rr killed %rcx, killed %rdx, implicit killed %eflags
%rcx = OR64rr killed %rcx, killed %rsi, implicit-def dead %eflags
%rdx = MOVSX64rm32 %rbx, 1, _, 0, _ :: (load 4, align 8)
- TEST32rm killed %eax, killed %rcx, 4, killed %rdx, 0, _, implicit-def %eflags :: (load 4)
+ TEST32mr killed %rcx, 4, killed %rdx, 0, _, killed %eax, implicit-def %eflags :: (load 4)
JNE_1 %bb.2, implicit %eflags
JMP_1 %bb.3
Modified: llvm/trunk/test/CodeGen/X86/testl-commute.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/testl-commute.ll?rev=314639&r1=314638&r2=314639&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/testl-commute.ll (original)
+++ llvm/trunk/test/CodeGen/X86/testl-commute.ll Sun Oct 1 16:53:53 2017
@@ -9,7 +9,7 @@ target triple = "x86_64-apple-darwin7"
define i32 @test(i32* %P, i32* %G) nounwind {
; CHECK-LABEL: test:
; CHECK-NOT: ret
-; CHECK: testl (%{{.*}}), %{{.*}}
+; CHECK: testl %{{.*}}, (%{{.*}})
; CHECK: ret
entry:
@@ -30,7 +30,7 @@ bb1: ; preds = %entry
define i32 @test2(i32* %P, i32* %G) nounwind {
; CHECK-LABEL: test2:
; CHECK-NOT: ret
-; CHECK: testl (%{{.*}}), %{{.*}}
+; CHECK: testl %{{.*}}, (%{{.*}})
; CHECK: ret
entry:
@@ -51,7 +51,7 @@ bb1: ; preds = %entry
define i32 @test3(i32* %P, i32* %G) nounwind {
; CHECK-LABEL: test3:
; CHECK-NOT: ret
-; CHECK: testl (%{{.*}}), %{{.*}}
+; CHECK: testl %{{.*}}, (%{{.*}})
; CHECK: ret
entry:
Modified: llvm/trunk/test/MC/Disassembler/X86/x86-16.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-16.txt?rev=314639&r1=314638&r2=314639&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-16.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-16.txt Sun Oct 1 16:53:53 2017
@@ -318,10 +318,10 @@
# CHECK: sysretl
0x0f 0x07
-# CHECK: testl -24(%ebp), %ecx
+# CHECK: testl %ecx, -24(%ebp)
0x67 0x66 0x85 0x4d 0xe8
-# CHECK: testl -24(%ebp), %ecx
+# CHECK: testl %ecx, -24(%ebp)
0x67 0x66 0x85 0x4d 0xe8
# CHECK: pushw %cs
Modified: llvm/trunk/test/MC/X86/intel-syntax.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/intel-syntax.s?rev=314639&r1=314638&r2=314639&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/intel-syntax.s (original)
+++ llvm/trunk/test/MC/X86/intel-syntax.s Sun Oct 1 16:53:53 2017
@@ -532,14 +532,14 @@ xchg [ECX], EAX
xchg AX, [ECX]
xchg [ECX], AX
-// CHECK: testq (%ecx), %rax
-// CHECK: testq (%ecx), %rax
-// CHECK: testl (%ecx), %eax
-// CHECK: testl (%ecx), %eax
-// CHECK: testw (%ecx), %ax
-// CHECK: testw (%ecx), %ax
-// CHECK: testb (%ecx), %al
-// CHECK: testb (%ecx), %al
+// CHECK: testq %rax, (%ecx)
+// CHECK: testq %rax, (%ecx)
+// CHECK: testl %eax, (%ecx)
+// CHECK: testl %eax, (%ecx)
+// CHECK: testw %ax, (%ecx)
+// CHECK: testw %ax, (%ecx)
+// CHECK: testb %al, (%ecx)
+// CHECK: testb %al, (%ecx)
test RAX, [ECX]
test [ECX], RAX
test EAX, [ECX]
Modified: llvm/trunk/test/MC/X86/x86-16.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-16.s?rev=314639&r1=314638&r2=314639&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-16.s (original)
+++ llvm/trunk/test/MC/X86/x86-16.s Sun Oct 1 16:53:53 2017
@@ -406,9 +406,9 @@ sysretl
// CHECK: encoding: [0x0f,0x07]
testl %ecx, -24(%ebp)
-// CHECK: testl -24(%ebp), %ecx
+// CHECK: testl %ecx, -24(%ebp)
testl -24(%ebp), %ecx
-// CHECK: testl -24(%ebp), %ecx
+// CHECK: testl %ecx, -24(%ebp)
push %cs
Modified: llvm/trunk/test/MC/X86/x86-32.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32.s?rev=314639&r1=314638&r2=314639&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-32.s (original)
+++ llvm/trunk/test/MC/X86/x86-32.s Sun Oct 1 16:53:53 2017
@@ -528,9 +528,9 @@ sysretl
// rdar://8018260
testl %ecx, -24(%ebp)
-// CHECK: testl -24(%ebp), %ecx
+// CHECK: testl %ecx, -24(%ebp)
testl -24(%ebp), %ecx
-// CHECK: testl -24(%ebp), %ecx
+// CHECK: testl %ecx, -24(%ebp)
// rdar://8407242
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