[PATCH] D38447: [MiSched] - Simply ProcResEntry access
Javed Absar via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 1 12:07:36 PDT 2017
javed.absar created this revision.
Simplify the way ProcResource is iterated over.
https://reviews.llvm.org/D38447
Files:
lib/CodeGen/MachineScheduler.cpp
Index: lib/CodeGen/MachineScheduler.cpp
===================================================================
--- lib/CodeGen/MachineScheduler.cpp
+++ lib/CodeGen/MachineScheduler.cpp
@@ -1962,16 +1962,18 @@
if (SchedModel->hasInstrSchedModel() && SU->hasReservedResource) {
const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
- for (TargetSchedModel::ProcResIter
- PI = SchedModel->getWriteProcResBegin(SC),
- PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
- unsigned NRCycle = getNextResourceCycle(PI->ProcResourceIdx, PI->Cycles);
+ for (const MCWriteProcResEntry &PE :
+ make_range(SchedModel->getWriteProcResBegin(SC),
+ SchedModel->getWriteProcResEnd(SC))) {
+ unsigned ResIdx = PE.ProcResourceIdx;
+ unsigned Cycles = PE.Cycles;
+ unsigned NRCycle = getNextResourceCycle(ResIdx, Cycles);
if (NRCycle > CurrCycle) {
#ifndef NDEBUG
- MaxObservedStall = std::max(PI->Cycles, MaxObservedStall);
+ MaxObservedStall = std::max(Cycles, MaxObservedStall);
#endif
DEBUG(dbgs() << " SU(" << SU->NodeNum << ") "
- << SchedModel->getResourceName(PI->ProcResourceIdx)
+ << SchedModel->getResourceName(ResIdx)
<< "=" << NRCycle << "c\n");
return true;
}
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