[PATCH] D38443: [X86][SKX] Adding the scheduling information for the SKX target.

[Gadi Haber via Phabricator via llvm-commits]

gadi.haber added a comment.

Good point. We had multiple rounds of checks and it seems that indeed some (not all) of the memory instructions do need to include additional latency based on whether they are load of an address or data, load of 128 or 256 or 512 bits vector, load and store and store alone.
I intend to go back and fix it for the Skylake Client and for Haswell.


Repository:
  rL LLVM

https://reviews.llvm.org/D38443