[llvm] r314516 - [SystemZ] implement shouldCoalesce()
Jonas Paulsson via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 29 07:31:40 PDT 2017
Author: jonpa
Date: Fri Sep 29 07:31:39 2017
New Revision: 314516
URL: http://llvm.org/viewvc/llvm-project?rev=314516&view=rev
Log:
[SystemZ] implement shouldCoalesce()
Implement shouldCoalesce() to help regalloc avoid running out of GR128
registers.
If a COPY involving a subreg of a GR128 is coalesced, the live range of the
GR128 virtual register will be extended. If this happens where there are
enough phys-reg clobbers present, regalloc will run out of registers (if
there is not a single GR128 allocatable register available).
This patch tries to allow coalescing only when it can prove that this will be
safe by checking the (local) interval in question.
Review: Ulrich Weigand, Quentin Colombet
https://reviews.llvm.org/D37899
https://bugs.llvm.org/show_bug.cgi?id=34610
Added:
llvm/trunk/test/CodeGen/SystemZ/regalloc-GR128.ll
Modified:
llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h
llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp
llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h
Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=314516&r1=314515&r2=314516&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Fri Sep 29 07:31:39 2017
@@ -40,6 +40,7 @@ class MachineFunction;
class MachineInstr;
class RegScavenger;
class VirtRegMap;
+class LiveIntervals;
class TargetRegisterClass {
public:
@@ -959,7 +960,8 @@ public:
unsigned SubReg,
const TargetRegisterClass *DstRC,
unsigned DstSubReg,
- const TargetRegisterClass *NewRC) const
+ const TargetRegisterClass *NewRC,
+ LiveIntervals &LIS) const
{ return true; }
//===--------------------------------------------------------------------===//
Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=314516&r1=314515&r2=314516&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Fri Sep 29 07:31:39 2017
@@ -1583,7 +1583,7 @@ bool RegisterCoalescer::joinCopy(Machine
std::swap(SrcRC, DstRC);
}
if (!TRI->shouldCoalesce(CopyMI, SrcRC, SrcIdx, DstRC, DstIdx,
- CP.getNewRC())) {
+ CP.getNewRC(), *LIS)) {
DEBUG(dbgs() << "\tSubtarget bailed on coalescing.\n");
return false;
}
Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=314516&r1=314515&r2=314516&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp Fri Sep 29 07:31:39 2017
@@ -1474,7 +1474,8 @@ bool SIRegisterInfo::shouldCoalesce(Mach
unsigned SubReg,
const TargetRegisterClass *DstRC,
unsigned DstSubReg,
- const TargetRegisterClass *NewRC) const {
+ const TargetRegisterClass *NewRC,
+ LiveIntervals &LIS) const {
unsigned SrcSize = getRegSizeInBits(*SrcRC);
unsigned DstSize = getRegSizeInBits(*DstRC);
unsigned NewSize = getRegSizeInBits(*NewRC);
Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h?rev=314516&r1=314515&r2=314516&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h Fri Sep 29 07:31:39 2017
@@ -22,6 +22,7 @@
namespace llvm {
+class LiveIntervals;
class MachineRegisterInfo;
class SISubtarget;
class SIMachineFunctionInfo;
@@ -212,7 +213,8 @@ public:
unsigned SubReg,
const TargetRegisterClass *DstRC,
unsigned DstSubReg,
- const TargetRegisterClass *NewRC) const override;
+ const TargetRegisterClass *NewRC,
+ LiveIntervals &LIS) const override;
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const override;
Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=314516&r1=314515&r2=314516&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Fri Sep 29 07:31:39 2017
@@ -807,7 +807,8 @@ bool ARMBaseRegisterInfo::shouldCoalesce
unsigned SubReg,
const TargetRegisterClass *DstRC,
unsigned DstSubReg,
- const TargetRegisterClass *NewRC) const {
+ const TargetRegisterClass *NewRC,
+ LiveIntervals &LIS) const {
auto MBB = MI->getParent();
auto MF = MBB->getParent();
const MachineRegisterInfo &MRI = MF->getRegInfo();
Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=314516&r1=314515&r2=314516&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Fri Sep 29 07:31:39 2017
@@ -27,6 +27,8 @@
namespace llvm {
+class LiveIntervals;
+
/// Register allocation hints.
namespace ARMRI {
@@ -204,7 +206,8 @@ public:
unsigned SubReg,
const TargetRegisterClass *DstRC,
unsigned DstSubReg,
- const TargetRegisterClass *NewRC) const override;
+ const TargetRegisterClass *NewRC,
+ LiveIntervals &LIS) const override;
};
} // end namespace llvm
Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp?rev=314516&r1=314515&r2=314516&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp Fri Sep 29 07:31:39 2017
@@ -10,6 +10,7 @@
#include "SystemZRegisterInfo.h"
#include "SystemZInstrInfo.h"
#include "SystemZSubtarget.h"
+#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
@@ -152,6 +153,72 @@ SystemZRegisterInfo::eliminateFrameIndex
MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
}
+bool SystemZRegisterInfo::shouldCoalesce(MachineInstr *MI,
+ const TargetRegisterClass *SrcRC,
+ unsigned SubReg,
+ const TargetRegisterClass *DstRC,
+ unsigned DstSubReg,
+ const TargetRegisterClass *NewRC,
+ LiveIntervals &LIS) const {
+ assert (MI->isCopy() && "Only expecting COPY instructions");
+
+ // Coalesce anything which is not a COPY involving a subreg to/from GR128.
+ if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) &&
+ (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64)))
+ return true;
+
+ // Allow coalescing of a GR128 subreg COPY only if the live ranges are small
+ // and local to one MBB with not too much interferring registers. Otherwise
+ // regalloc may run out of registers.
+
+ unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0);
+ unsigned GR128Reg = MI->getOperand(WideOpNo).getReg();
+ unsigned GRNarReg = MI->getOperand((WideOpNo == 1) ? 0 : 1).getReg();
+ LiveInterval &IntGR128 = LIS.getInterval(GR128Reg);
+ LiveInterval &IntGRNar = LIS.getInterval(GRNarReg);
+
+ // Check that the two virtual registers are local to MBB.
+ MachineBasicBlock *MBB = MI->getParent();
+ if (LIS.isLiveInToMBB(IntGR128, MBB) || LIS.isLiveOutOfMBB(IntGR128, MBB) ||
+ LIS.isLiveInToMBB(IntGRNar, MBB) || LIS.isLiveOutOfMBB(IntGRNar, MBB))
+ return false;
+
+ // Find the first and last MIs of the registers.
+ MachineInstr *FirstMI = nullptr, *LastMI = nullptr;
+ if (WideOpNo == 1) {
+ FirstMI = LIS.getInstructionFromIndex(IntGR128.beginIndex());
+ LastMI = LIS.getInstructionFromIndex(IntGRNar.endIndex());
+ } else {
+ FirstMI = LIS.getInstructionFromIndex(IntGRNar.beginIndex());
+ LastMI = LIS.getInstructionFromIndex(IntGR128.endIndex());
+ }
+ assert (FirstMI && LastMI && "No instruction from index?");
+
+ // Check if coalescing seems safe by finding the set of clobbered physreg
+ // pairs in the region.
+ BitVector PhysClobbered(getNumRegs());
+ MachineBasicBlock::iterator MII = FirstMI, MEE = LastMI;
+ MEE++;
+ for (; MII != MEE; ++MII) {
+ for (const MachineOperand &MO : MII->operands())
+ if (MO.isReg() && isPhysicalRegister(MO.getReg())) {
+ for (MCSuperRegIterator SI(MO.getReg(), this, true/*IncludeSelf*/);
+ SI.isValid(); ++SI)
+ if (NewRC->contains(*SI)) {
+ PhysClobbered.set(*SI);
+ break;
+ }
+ }
+ }
+
+ // Demand an arbitrary margin of free regs.
+ unsigned const DemandedFreeGR128 = 3;
+ if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128))
+ return false;
+
+ return true;
+}
+
unsigned
SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const SystemZFrameLowering *TFI = getFrameLowering(MF);
Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h?rev=314516&r1=314515&r2=314516&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h Fri Sep 29 07:31:39 2017
@@ -18,6 +18,8 @@
namespace llvm {
+class LiveIntervals;
+
namespace SystemZ {
// Return the subreg to use for referring to the even and odd registers
// in a GR128 pair. Is32Bit says whether we want a GR32 or GR64.
@@ -59,6 +61,16 @@ public:
void eliminateFrameIndex(MachineBasicBlock::iterator MI,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS) const override;
+
+ /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true.
+ bool shouldCoalesce(MachineInstr *MI,
+ const TargetRegisterClass *SrcRC,
+ unsigned SubReg,
+ const TargetRegisterClass *DstRC,
+ unsigned DstSubReg,
+ const TargetRegisterClass *NewRC,
+ LiveIntervals &LIS) const override;
+
unsigned getFrameRegister(const MachineFunction &MF) const override;
};
Added: llvm/trunk/test/CodeGen/SystemZ/regalloc-GR128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/regalloc-GR128.ll?rev=314516&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/regalloc-GR128.ll (added)
+++ llvm/trunk/test/CodeGen/SystemZ/regalloc-GR128.ll Fri Sep 29 07:31:39 2017
@@ -0,0 +1,18 @@
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -O3 -o /dev/null
+;
+; Test that regalloc does not run out of registers
+
+; This test will include a GR128 virtual reg.
+define void @test0(i64 %dividend, i64 %divisor) {
+ %rem = urem i64 %dividend, %divisor
+ call void asm sideeffect "", "{r0},{r1},{r2},{r3},{r4},{r5},{r6},{r7},{r8},{r9},{r10},{r11},{r12},{r13},{r14}"(i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 %rem)
+ ret void
+}
+
+; This test will include an ADDR128 virtual reg.
+define i64 @test1(i64 %dividend, i64 %divisor) {
+%rem = urem i64 %dividend, %divisor
+call void asm sideeffect "", "{r2},{r3},{r4},{r5},{r6},{r7},{r8},{r9},{r10},{r11},{r12},{r13},{r14}"(i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 %rem)
+%ret = add i64 %rem, 1
+ret i64 %ret
+}
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